Update the copyright notice format

[mirror_edk2.git] / Omap35xxPkg / PciEmulation / PciEmulation.c

diff --git a/Omap35xxPkg/PciEmulation/PciEmulation.c b/Omap35xxPkg/PciEmulation/PciEmulation.c
index bdba40353f52c59336aa430b00bf33f4a56ae2e4..b264349b99b06df44338defa454beae9e1951260 100644 (file)
--- a/Omap35xxPkg/PciEmulation/PciEmulation.c
+++ b/Omap35xxPkg/PciEmulation/PciEmulation.c
@@ -1,8 +1,8 @@
 /** @file
 
-  Copyright (c) 2008-2009, Apple Inc. All rights reserved.
+  Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
   
-  All rights reserved. This program and the accompanying materials
+  This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD License
   which accompanies this distribution.  The full text of the license may be found at
   http://opensource.org/licenses/bsd-license.php
@@ -62,21 +62,21 @@ ConfigureUSBHost (
   EFI_STATUS Status;
   UINT8      Data = 0;
 
-  // Take USB host out of force-standby mode
+   // Take USB host out of force-standby mode
   MmioWrite32 (UHH_SYSCONFIG, UHH_SYSCONFIG_MIDLEMODE_NO_STANDBY
-                             | UHH_SYSCONFIG_CLOCKACTIVITY_ON
-                             | UHH_SYSCONFIG_SIDLEMODE_NO_STANDBY
-                             | UHH_SYSCONFIG_ENAWAKEUP_ENABLE    
-                             | UHH_SYSCONFIG_AUTOIDLE_ALWAYS_RUN);
+                            | UHH_SYSCONFIG_CLOCKACTIVITY_ON
+                            | UHH_SYSCONFIG_SIDLEMODE_NO_STANDBY
+                            | UHH_SYSCONFIG_ENAWAKEUP_ENABLE
+                            | UHH_SYSCONFIG_AUTOIDLE_ALWAYS_RUN);
   MmioWrite32 (UHH_HOSTCONFIG, UHH_HOSTCONFIG_P3_CONNECT_STATUS_DISCONNECT
-                              | UHH_HOSTCONFIG_P2_CONNECT_STATUS_DISCONNECT
-                              | UHH_HOSTCONFIG_P1_CONNECT_STATUS_DISCONNECT
-                              | UHH_HOSTCONFIG_ENA_INCR_ALIGN_DISABLE      
-                              | UHH_HOSTCONFIG_ENA_INCR16_ENABLE           
-                              | UHH_HOSTCONFIG_ENA_INCR8_ENABLE            
-                              | UHH_HOSTCONFIG_ENA_INCR4_ENABLE            
-                              | UHH_HOSTCONFIG_AUTOPPD_ON_OVERCUR_EN_ON    
-                              | UHH_HOSTCONFIG_P1_ULPI_BYPASS_ULPI_MODE);
+                             | UHH_HOSTCONFIG_P2_CONNECT_STATUS_DISCONNECT
+                             | UHH_HOSTCONFIG_P1_CONNECT_STATUS_DISCONNECT
+                             | UHH_HOSTCONFIG_ENA_INCR_ALIGN_DISABLE
+                             | UHH_HOSTCONFIG_ENA_INCR16_ENABLE
+                             | UHH_HOSTCONFIG_ENA_INCR8_ENABLE
+                             | UHH_HOSTCONFIG_ENA_INCR4_ENABLE
+                             | UHH_HOSTCONFIG_AUTOPPD_ON_OVERCUR_EN_ON
+                             | UHH_HOSTCONFIG_P1_ULPI_BYPASS_ULPI_MODE);
 
   // USB reset (GPIO 147 - Port 5 pin 19) output high
   MmioAnd32(GPIO5_BASE + GPIO_OE, ~BIT19);
@@ -97,6 +97,7 @@ ConfigureUSBHost (
   ASSERT_EFI_ERROR(Status);
 }
 
+
 EFI_STATUS
 PciIoPollMem (
   IN EFI_PCI_IO_PROTOCOL           *This,
@@ -528,7 +529,7 @@ PciEmulationEntryPoint (
 
   // Find out the capability register length and number of physical ports.
   CapabilityLength = MmioRead8(Private->RootBridge.MemoryStart);
-  PhysicalPorts    = (MmioRead32(Private->RootBridge.MemoryStart + 0x4)) & 0x0000000F;
+  PhysicalPorts    = (MmioRead32 (Private->RootBridge.MemoryStart + 0x4)) & 0x0000000F;
 
   // Calculate the total size of the USB registers.
   Private->RootBridge.MemorySize = CapabilityLength + (HOST_CONTROLLER_OPERATION_REG_SIZE + ((4 * PhysicalPorts) - 1));
@@ -537,7 +538,7 @@ PciEmulationEntryPoint (
   // Port Power Control (PPC) bit in the HCSPARAMS register is already set which indicates
   // host controller implementation includes port power control.
   for (Count = 0; Count < PhysicalPorts; Count++) {
-    MmioOr32((Private->RootBridge.MemoryStart + CapabilityLength + HOST_CONTROLLER_OPERATION_REG_SIZE + 4*Count), 0x00001000);
+    MmioOr32 ((Private->RootBridge.MemoryStart + CapabilityLength + HOST_CONTROLLER_OPERATION_REG_SIZE + 4*Count), 0x00001000);
   }
 
   // Create fake PCI config space.