--- /dev/null
+/** @file\r
+ Definitions for network adapter card.\r
+\r
+Copyright (c) 2006 - 2007, Intel Corporation\r
+All rights reserved. This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#ifndef _E100B_H_\r
+#define _E100B_H_\r
+\r
+// pci config offsets:\r
+\r
+#define RX_BUFFER_COUNT 32\r
+#define TX_BUFFER_COUNT 32\r
+\r
+#define PCI_VENDOR_ID_INTEL 0x8086\r
+#define PCI_DEVICE_ID_INTEL_82557 0x1229\r
+#define D100_VENDOR_ID 0x8086\r
+#define D100_DEVICE_ID 0x1229\r
+#define D102_DEVICE_ID 0x2449\r
+\r
+#define ICH3_DEVICE_ID_1 0x1031\r
+#define ICH3_DEVICE_ID_2 0x1032\r
+#define ICH3_DEVICE_ID_3 0x1033\r
+#define ICH3_DEVICE_ID_4 0x1034\r
+#define ICH3_DEVICE_ID_5 0x1035\r
+#define ICH3_DEVICE_ID_6 0x1036\r
+#define ICH3_DEVICE_ID_7 0x1037\r
+#define ICH3_DEVICE_ID_8 0x1038\r
+\r
+#define SPEEDO_DEVICE_ID 0x1227\r
+#define SPLASH1_DEVICE_ID 0x1226\r
+\r
+\r
+// bit fields for the command\r
+#define PCI_COMMAND_MASTER 0x04 // bit 2\r
+#define PCI_COMMAND_IO 0x01 // bit 0\r
+#define PCI_COMMAND 0x04\r
+#define PCI_LATENCY_TIMER 0x0D\r
+\r
+#define ETHER_MAC_ADDR_LEN 6\r
+#ifdef AVL_XXX\r
+#define ETHER_HEADER_LEN 14\r
+// media interface type\r
+// #define INTERFACE_TYPE "\r
+\r
+// Hardware type values\r
+#define HW_ETHER_TYPE 1\r
+#define HW_EXPERIMENTAL_ETHER_TYPE 2\r
+#define HW_IEEE_TYPE 6\r
+#define HW_ARCNET_TYPE 7\r
+\r
+#endif // AVL_XXX\r
+\r
+#define MAX_ETHERNET_PKT_SIZE 1514 // including eth header\r
+#define RX_BUFFER_SIZE 1536 // including crc and padding\r
+#define TX_BUFFER_SIZE 64\r
+#define ETH_MTU 1500 // does not include ethernet header length\r
+\r
+#define SPEEDO3_TOTAL_SIZE 0x20\r
+\r
+#pragma pack(1)\r
+\r
+typedef struct eth {\r
+ UINT8 dest_addr[PXE_HWADDR_LEN_ETHER];\r
+ UINT8 src_addr[PXE_HWADDR_LEN_ETHER];\r
+ UINT16 type;\r
+} EtherHeader;\r
+\r
+#pragma pack(1)\r
+typedef struct CONFIG_HEADER {\r
+ UINT16 VendorID;\r
+ UINT16 DeviceID;\r
+ UINT16 Command;\r
+ UINT16 Status;\r
+ UINT16 RevID;\r
+ UINT16 ClassID;\r
+ UINT8 CacheLineSize;\r
+ UINT8 LatencyTimer;\r
+ UINT8 HeaderType; // must be zero to impose this structure...\r
+ UINT8 BIST; // built-in self test\r
+ UINT32 BaseAddressReg_0; // memory mapped address\r
+ UINT32 BaseAddressReg_1; //io mapped address, Base IO address\r
+ UINT32 BaseAddressReg_2; // option rom address\r
+ UINT32 BaseAddressReg_3;\r
+ UINT32 BaseAddressReg_4;\r
+ UINT32 BaseAddressReg_5;\r
+ UINT32 CardBusCISPtr;\r
+ UINT16 SubVendorID;\r
+ UINT16 SubSystemID;\r
+ UINT32 ExpansionROMBaseAddr;\r
+ UINT8 CapabilitiesPtr;\r
+ UINT8 reserved1;\r
+ UINT16 Reserved2;\r
+ UINT32 Reserved3;\r
+ UINT8 int_line;\r
+ UINT8 int_pin;\r
+ UINT8 Min_gnt;\r
+ UINT8 Max_lat;\r
+} PCI_CONFIG_HEADER;\r
+#pragma pack()\r
+\r
+//-------------------------------------------------------------------------\r
+// Offsets to the various registers.\r
+// All accesses need not be longword aligned.\r
+//-------------------------------------------------------------------------\r
+enum speedo_offsets {\r
+ SCBStatus = 0, SCBCmd = 2, // Rx/Command Unit command and status.\r
+ SCBPointer = 4, // General purpose pointer.\r
+ SCBPort = 8, // Misc. commands and operands.\r
+ SCBflash = 12, SCBeeprom = 14, // EEPROM and flash memory control.\r
+ SCBCtrlMDI = 16, // MDI interface control.\r
+ SCBEarlyRx = 20, // Early receive byte count.\r
+ SCBEarlyRxInt = 24, SCBFlowCtrlReg = 25, SCBPmdr = 27,\r
+ // offsets for general control registers (GCRs)\r
+ SCBGenCtrl = 28, SCBGenStatus = 29, SCBGenCtrl2 = 30, SCBRsvd = 31\r
+};\r
+\r
+#define GCR2_EEPROM_ACCESS_SEMAPHORE 0x80 // bit offset into the gcr2\r
+\r
+//-------------------------------------------------------------------------\r
+// Action commands - Commands that can be put in a command list entry.\r
+//-------------------------------------------------------------------------\r
+enum commands {\r
+ CmdNOp = 0, CmdIASetup = 1, CmdConfigure = 2, CmdMulticastList = 3,\r
+ CmdTx = 4, CmdTDR = 5, CmdDump = 6, CmdDiagnose = 7,\r
+ CmdSuspend = 0x4000, /* Suspend after completion. */\r
+ CmdIntr = 0x2000, /* Interrupt after completion. */\r
+ CmdTxFlex = 0x0008 /* Use "Flexible mode" for CmdTx command. */\r
+};\r
+\r
+//-------------------------------------------------------------------------\r
+// port commands\r
+//-------------------------------------------------------------------------\r
+#define PORT_RESET 0\r
+#define PORT_SELF_TEST 1\r
+#define POR_SELECTIVE_RESET 2\r
+#define PORT_DUMP_POINTER 2\r
+\r
+//-------------------------------------------------------------------------\r
+// SCB Command Word bit definitions\r
+//-------------------------------------------------------------------------\r
+//- CUC fields\r
+#define CU_START 0x0010\r
+#define CU_RESUME 0x0020\r
+#define CU_STATSADDR 0x0040\r
+#define CU_SHOWSTATS 0x0050 /* Dump statistics counters. */\r
+#define CU_CMD_BASE 0x0060 /* Base address to add to add CU commands. */\r
+#define CU_DUMPSTATS 0x0070 /* Dump then reset stats counters. */\r
+\r
+//- RUC fields\r
+#define RX_START 0x0001\r
+#define RX_RESUME 0x0002\r
+#define RX_ABORT 0x0004\r
+#define RX_ADDR_LOAD 0x0006 /* load ru_base_reg */\r
+#define RX_RESUMENR 0x0007\r
+\r
+// Interrupt fields (assuming byte addressing)\r
+#define INT_MASK 0x0100\r
+#define DRVR_INT 0x0200 /* Driver generated interrupt. */\r
+\r
+//- CB Status Word\r
+#define CMD_STATUS_COMPLETE 0x8000\r
+#define RX_STATUS_COMPLETE 0x8000\r
+#define CMD_STATUS_MASK 0xF000\r
+\r
+//-------------------------------------------------------------------------\r
+//- SCB Status bits:\r
+// Interrupts are ACKed by writing to the upper 6 interrupt bits\r
+//-------------------------------------------------------------------------\r
+#define SCB_STATUS_MASK 0xFC00 // bits 2-7 - STATUS/ACK Mask\r
+#define SCB_STATUS_CX_TNO 0x8000 // BIT_15 - CX or TNO Interrupt\r
+#define SCB_STATUS_FR 0x4000 // BIT_14 - FR Interrupt\r
+#define SCB_STATUS_CNA 0x2000 // BIT_13 - CNA Interrupt\r
+#define SCB_STATUS_RNR 0x1000 // BIT_12 - RNR Interrupt\r
+#define SCB_STATUS_MDI 0x0800 // BIT_11 - MDI R/W Done Interrupt\r
+#define SCB_STATUS_SWI 0x0400 // BIT_10 - SWI Interrupt\r
+\r
+// CU STATUS: bits 6 & 7\r
+#define SCB_STATUS_CU_MASK 0x00C0 // bits 6 & 7\r
+#define SCB_STATUS_CU_IDLE 0x0000 // 00\r
+#define SCB_STATUS_CU_SUSPEND 0x0040 // 01\r
+#define SCB_STATUS_CU_ACTIVE 0x0080 // 10\r
+\r
+// RU STATUS: bits 2-5\r
+#define SCB_RUS_IDLE 0x0000\r
+#define SCB_RUS_SUSPENDED 0x0004 // bit 2\r
+#define SCB_RUS_NO_RESOURCES 0x0008 // bit 3\r
+#define SCB_RUS_READY 0x0010 // bit 4\r
+\r
+//-------------------------------------------------------------------------\r
+// Bit Mask definitions\r
+//-------------------------------------------------------------------------\r
+#define BIT_0 0x0001\r
+#define BIT_1 0x0002\r
+#define BIT_2 0x0004\r
+#define BIT_3 0x0008\r
+#define BIT_4 0x0010\r
+#define BIT_5 0x0020\r
+#define BIT_6 0x0040\r
+#define BIT_7 0x0080\r
+#define BIT_8 0x0100\r
+#define BIT_9 0x0200\r
+#define BIT_10 0x0400\r
+#define BIT_11 0x0800\r
+#define BIT_12 0x1000\r
+#define BIT_13 0x2000\r
+#define BIT_14 0x4000\r
+#define BIT_15 0x8000\r
+#define BIT_24 0x01000000\r
+#define BIT_28 0x10000000\r
+\r
+\r
+//-------------------------------------------------------------------------\r
+// MDI Control register bit definitions\r
+//-------------------------------------------------------------------------\r
+#define MDI_DATA_MASK BIT_0_15 // MDI Data port\r
+#define MDI_REG_ADDR BIT_16_20 // which MDI register to read/write\r
+#define MDI_PHY_ADDR BIT_21_25 // which PHY to read/write\r
+#define MDI_PHY_OPCODE BIT_26_27 // which PHY to read/write\r
+#define MDI_PHY_READY BIT_28 // PHY is ready for another MDI cycle\r
+#define MDI_PHY_INT_ENABLE BIT_29 // Assert INT at MDI cycle completion\r
+\r
+#define BIT_0_2 0x0007\r
+#define BIT_0_3 0x000F\r
+#define BIT_0_4 0x001F\r
+#define BIT_0_5 0x003F\r
+#define BIT_0_6 0x007F\r
+#define BIT_0_7 0x00FF\r
+#define BIT_0_8 0x01FF\r
+#define BIT_0_13 0x3FFF\r
+#define BIT_0_15 0xFFFF\r
+#define BIT_1_2 0x0006\r
+#define BIT_1_3 0x000E\r
+#define BIT_2_5 0x003C\r
+#define BIT_3_4 0x0018\r
+#define BIT_4_5 0x0030\r
+#define BIT_4_6 0x0070\r
+#define BIT_4_7 0x00F0\r
+#define BIT_5_7 0x00E0\r
+#define BIT_5_9 0x03E0\r
+#define BIT_5_12 0x1FE0\r
+#define BIT_5_15 0xFFE0\r
+#define BIT_6_7 0x00c0\r
+#define BIT_7_11 0x0F80\r
+#define BIT_8_10 0x0700\r
+#define BIT_9_13 0x3E00\r
+#define BIT_12_15 0xF000\r
+\r
+#define BIT_16_20 0x001F0000\r
+#define BIT_21_25 0x03E00000\r
+#define BIT_26_27 0x0C000000\r
+\r
+//-------------------------------------------------------------------------\r
+// MDI Control register opcode definitions\r
+//-------------------------------------------------------------------------\r
+#define MDI_WRITE 1 // Phy Write\r
+#define MDI_READ 2 // Phy read\r
+\r
+//-------------------------------------------------------------------------\r
+// PHY 100 MDI Register/Bit Definitions\r
+//-------------------------------------------------------------------------\r
+// MDI register set\r
+#define MDI_CONTROL_REG 0x00 // MDI control register\r
+#define MDI_STATUS_REG 0x01 // MDI Status regiser\r
+#define PHY_ID_REG_1 0x02 // Phy indentification reg (word 1)\r
+#define PHY_ID_REG_2 0x03 // Phy indentification reg (word 2)\r
+#define AUTO_NEG_ADVERTISE_REG 0x04 // Auto-negotiation advertisement\r
+#define AUTO_NEG_LINK_PARTNER_REG 0x05 // Auto-negotiation link partner ability\r
+#define AUTO_NEG_EXPANSION_REG 0x06 // Auto-negotiation expansion\r
+#define AUTO_NEG_NEXT_PAGE_REG 0x07 // Auto-negotiation next page transmit\r
+#define EXTENDED_REG_0 0x10 // Extended reg 0 (Phy 100 modes)\r
+#define EXTENDED_REG_1 0x14 // Extended reg 1 (Phy 100 error indications)\r
+#define NSC_CONG_CONTROL_REG 0x17 // National (TX) congestion control\r
+#define NSC_SPEED_IND_REG 0x19 // National (TX) speed indication\r
+\r
+// MDI Control register bit definitions\r
+#define MDI_CR_COLL_TEST_ENABLE BIT_7 // Collision test enable\r
+#define MDI_CR_FULL_HALF BIT_8 // FDX =1, half duplex =0\r
+#define MDI_CR_RESTART_AUTO_NEG BIT_9 // Restart auto negotiation\r
+#define MDI_CR_ISOLATE BIT_10 // Isolate PHY from MII\r
+#define MDI_CR_POWER_DOWN BIT_11 // Power down\r
+#define MDI_CR_AUTO_SELECT BIT_12 // Auto speed select enable\r
+#define MDI_CR_10_100 BIT_13 // 0 = 10Mbs, 1 = 100Mbs\r
+#define MDI_CR_LOOPBACK BIT_14 // 0 = normal, 1 = loopback\r
+#define MDI_CR_RESET BIT_15 // 0 = normal, 1 = PHY reset\r
+\r
+// MDI Status register bit definitions\r
+#define MDI_SR_EXT_REG_CAPABLE BIT_0 // Extended register capabilities\r
+#define MDI_SR_JABBER_DETECT BIT_1 // Jabber detected\r
+#define MDI_SR_LINK_STATUS BIT_2 // Link Status -- 1 = link\r
+#define MDI_SR_AUTO_SELECT_CAPABLE BIT_3 // Auto speed select capable\r
+#define MDI_SR_REMOTE_FAULT_DETECT BIT_4 // Remote fault detect\r
+#define MDI_SR_AUTO_NEG_COMPLETE BIT_5 // Auto negotiation complete\r
+#define MDI_SR_10T_HALF_DPX BIT_11 // 10BaseT Half Duplex capable\r
+#define MDI_SR_10T_FULL_DPX BIT_12 // 10BaseT full duplex capable\r
+#define MDI_SR_TX_HALF_DPX BIT_13 // TX Half Duplex capable\r
+#define MDI_SR_TX_FULL_DPX BIT_14 // TX full duplex capable\r
+#define MDI_SR_T4_CAPABLE BIT_15 // T4 capable\r
+\r
+// Auto-Negotiation advertisement register bit definitions\r
+#define NWAY_AD_SELCTOR_FIELD BIT_0_4 // identifies supported protocol\r
+#define NWAY_AD_ABILITY BIT_5_12 // technologies that are supported\r
+#define NWAY_AD_10T_HALF_DPX BIT_5 // 10BaseT Half Duplex capable\r
+#define NWAY_AD_10T_FULL_DPX BIT_6 // 10BaseT full duplex capable\r
+#define NWAY_AD_TX_HALF_DPX BIT_7 // TX Half Duplex capable\r
+#define NWAY_AD_TX_FULL_DPX BIT_8 // TX full duplex capable\r
+#define NWAY_AD_T4_CAPABLE BIT_9 // T4 capable\r
+#define NWAY_AD_REMOTE_FAULT BIT_13 // indicates local remote fault\r
+#define NWAY_AD_RESERVED BIT_14 // reserved\r
+#define NWAY_AD_NEXT_PAGE BIT_15 // Next page (not supported)\r
+\r
+// Auto-Negotiation link partner ability register bit definitions\r
+#define NWAY_LP_SELCTOR_FIELD BIT_0_4 // identifies supported protocol\r
+#define NWAY_LP_ABILITY BIT_5_9 // technologies that are supported\r
+#define NWAY_LP_REMOTE_FAULT BIT_13 // indicates partner remote fault\r
+#define NWAY_LP_ACKNOWLEDGE BIT_14 // acknowledge\r
+#define NWAY_LP_NEXT_PAGE BIT_15 // Next page (not supported)\r
+\r
+// Auto-Negotiation expansion register bit definitions\r
+#define NWAY_EX_LP_NWAY BIT_0 // link partner is NWAY\r
+#define NWAY_EX_PAGE_RECEIVED BIT_1 // link code word received\r
+#define NWAY_EX_NEXT_PAGE_ABLE BIT_2 // local is next page able\r
+#define NWAY_EX_LP_NEXT_PAGE_ABLE BIT_3 // partner is next page able\r
+#define NWAY_EX_PARALLEL_DET_FLT BIT_4 // parallel detection fault\r
+#define NWAY_EX_RESERVED BIT_5_15 // reserved\r
+\r
+\r
+// PHY 100 Extended Register 0 bit definitions\r
+#define PHY_100_ER0_FDX_INDIC BIT_0 // 1 = FDX, 0 = half duplex\r
+#define PHY_100_ER0_SPEED_INDIC BIT_1 // 1 = 100mbs, 0= 10mbs\r
+#define PHY_100_ER0_WAKE_UP BIT_2 // Wake up DAC\r
+#define PHY_100_ER0_RESERVED BIT_3_4 // Reserved\r
+#define PHY_100_ER0_REV_CNTRL BIT_5_7 // Revsion control (A step = 000)\r
+#define PHY_100_ER0_FORCE_FAIL BIT_8 // Force Fail is enabled\r
+#define PHY_100_ER0_TEST BIT_9_13 // Revsion control (A step = 000)\r
+#define PHY_100_ER0_LINKDIS BIT_14 // Link integrity test is disabled\r
+#define PHY_100_ER0_JABDIS BIT_15 // Jabber function is disabled\r
+\r
+\r
+// PHY 100 Extended Register 1 bit definitions\r
+#define PHY_100_ER1_RESERVED BIT_0_8 // Reserved\r
+#define PHY_100_ER1_CH2_DET_ERR BIT_9 // Channel 2 EOF detection error\r
+#define PHY_100_ER1_MANCH_CODE_ERR BIT_10 // Manchester code error\r
+#define PHY_100_ER1_EOP_ERR BIT_11 // EOP error\r
+#define PHY_100_ER1_BAD_CODE_ERR BIT_12 // bad code error\r
+#define PHY_100_ER1_INV_CODE_ERR BIT_13 // invalid code error\r
+#define PHY_100_ER1_DC_BAL_ERR BIT_14 // DC balance error\r
+#define PHY_100_ER1_PAIR_SKEW_ERR BIT_15 // Pair skew error\r
+\r
+// National Semiconductor TX phy congestion control register bit definitions\r
+#define NSC_TX_CONG_TXREADY BIT_10 // Makes TxReady an input\r
+#define NSC_TX_CONG_ENABLE BIT_8 // Enables congestion control\r
+#define NSC_TX_CONG_F_CONNECT BIT_5 // Enables congestion control\r
+\r
+// National Semiconductor TX phy speed indication register bit definitions\r
+#define NSC_TX_SPD_INDC_SPEED BIT_6 // 0 = 100mb, 1=10mb\r
+\r
+//-------------------------------------------------------------------------\r
+// Phy related constants\r
+//-------------------------------------------------------------------------\r
+#define PHY_503 0\r
+#define PHY_100_A 0x000003E0\r
+#define PHY_100_C 0x035002A8\r
+#define PHY_TX_ID 0x015002A8\r
+#define PHY_NSC_TX 0x5c002000\r
+#define PHY_OTHER 0xFFFF\r
+\r
+#define PHY_MODEL_REV_ID_MASK 0xFFF0FFFF\r
+#define PARALLEL_DETECT 0\r
+#define N_WAY 1\r
+\r
+#define RENEGOTIATE_TIME 35 // (3.5 Seconds)\r
+\r
+#define CONNECTOR_AUTO 0\r
+#define CONNECTOR_TPE 1\r
+#define CONNECTOR_MII 2\r
+\r
+//-------------------------------------------------------------------------\r
+\r
+/* The Speedo3 Rx and Tx frame/buffer descriptors. */\r
+#pragma pack(1)\r
+struct CB_Header { /* A generic descriptor. */\r
+ UINT16 status; /* Offset 0. */\r
+ UINT16 command; /* Offset 2. */\r
+ UINT32 link; /* struct descriptor * */\r
+};\r
+\r
+/* transmit command block structure */\r
+#pragma pack(1)\r
+typedef struct s_TxCB {\r
+ struct CB_Header cb_header;\r
+ UINT32 PhysTBDArrayAddres; /* address of an array that contains\r
+ physical TBD pointers */\r
+ UINT16 ByteCount; /* immediate data count = 0 always */\r
+ UINT8 Threshold;\r
+ UINT8 TBDCount;\r
+ UINT8 ImmediateData[TX_BUFFER_SIZE];\r
+ /* following fields are not seen by the 82557 */\r
+ struct TBD {\r
+ UINT32 phys_buf_addr;\r
+ UINT32 buf_len;\r
+ } TBDArray[MAX_XMIT_FRAGMENTS];\r
+ UINT32 PhysArrayAddr; /* in case the one in the header is lost */\r
+ UINT32 PhysTCBAddress; /* for this TCB */\r
+ struct s_TxCB *NextTCBVirtualLinkPtr;\r
+ struct s_TxCB *PrevTCBVirtualLinkPtr;\r
+ UINT64 free_data_ptr; // to be given to the upper layer when this xmit completes1\r
+}TxCB;\r
+\r
+/* The Speedo3 Rx and Tx buffer descriptors. */\r
+#pragma pack(1)\r
+typedef struct s_RxFD { /* Receive frame descriptor. */\r
+ struct CB_Header cb_header;\r
+ UINT32 rx_buf_addr; /* VOID * */\r
+ UINT16 ActualCount;\r
+ UINT16 RFDSize;\r
+ UINT8 RFDBuffer[RX_BUFFER_SIZE];\r
+ UINT8 forwarded;\r
+ UINT8 junk[3];\r
+}RxFD;\r
+\r
+/* Elements of the RxFD.status word. */\r
+#define RX_COMPLETE 0x8000\r
+#define RX_FRAME_OK 0x2000\r
+\r
+/* Elements of the dump_statistics block. This block must be lword aligned. */\r
+#pragma pack(1)\r
+struct speedo_stats {\r
+ UINT32 tx_good_frames;\r
+ UINT32 tx_coll16_errs;\r
+ UINT32 tx_late_colls;\r
+ UINT32 tx_underruns;\r
+ UINT32 tx_lost_carrier;\r
+ UINT32 tx_deferred;\r
+ UINT32 tx_one_colls;\r
+ UINT32 tx_multi_colls;\r
+ UINT32 tx_total_colls;\r
+ UINT32 rx_good_frames;\r
+ UINT32 rx_crc_errs;\r
+ UINT32 rx_align_errs;\r
+ UINT32 rx_resource_errs;\r
+ UINT32 rx_overrun_errs;\r
+ UINT32 rx_colls_errs;\r
+ UINT32 rx_runt_errs;\r
+ UINT32 done_marker;\r
+};\r
+#pragma pack()\r
+\r
+\r
+struct Krn_Mem{\r
+ RxFD rx_ring[RX_BUFFER_COUNT];\r
+ TxCB tx_ring[TX_BUFFER_COUNT];\r
+ struct speedo_stats statistics;\r
+};\r
+#define MEMORY_NEEDED sizeof(struct Krn_Mem)\r
+\r
+/* The parameters for a CmdConfigure operation.\r
+ There are so many options that it would be difficult to document each bit.\r
+ We mostly use the default or recommended settings.\r
+*/\r
+\r
+/*\r
+ *--------------------------------------------------------------------------\r
+ * Configuration CB Parameter Bit Definitions\r
+ *--------------------------------------------------------------------------\r
+ */\r
+// - Byte 0 (Default Value = 16h)\r
+#define CFIG_BYTE_COUNT 0x16 // 22 Configuration Bytes\r
+\r
+//- Byte 1 (Default Value = 88h)\r
+#define CFIG_TXRX_FIFO_LIMIT 0x88\r
+\r
+//- Byte 2 (Default Value = 0)\r
+#define CFIG_ADAPTIVE_IFS 0\r
+\r
+//- Byte 3 (Default Value = 0, ALWAYS. This byte is RESERVED)\r
+#define CFIG_RESERVED 0\r
+\r
+//- Byte 4 (Default Value = 0. Default implies that Rx DMA cannot be\r
+//- preempted).\r
+#define CFIG_RXDMA_BYTE_COUNT 0\r
+\r
+//- Byte 5 (Default Value = 80h. Default implies that Tx DMA cannot be\r
+//- preempted. However, setting these counters is enabled.)\r
+#define CFIG_DMBC_ENABLE 0x80\r
+\r
+//- Byte 6 (Default Value = 33h. Late SCB enabled, No TNO interrupts,\r
+//- CNA interrupts and do not save bad frames.)\r
+#define CFIG_LATE_SCB 1 // BIT 0\r
+#define CFIG_TNO_INTERRUPT 0x4 // BIT 2\r
+#define CFIG_CI_INTERRUPT 0x8 // BIT 3\r
+#define CFIG_SAVE_BAD_FRAMES 0x80 // BIT_7\r
+\r
+//- Byte 7 (Default Value = 7h. Discard short frames automatically and\r
+//- attempt upto 3 retries on transmit.)\r
+#define CFIG_DISCARD_SHORTRX 0x00001\r
+#define CFIG_URUN_RETRY BIT_1 OR BIT_2\r
+\r
+//- Byte 8 (Default Value = 1. Enable MII mode.)\r
+#define CFIG_503_MII BIT_0\r
+\r
+//- Byte 9 (Default Value = 0, ALWAYS)\r
+\r
+//- Byte 10 (Default Value = 2Eh)\r
+#define CFIG_NSAI BIT_3\r
+#define CFIG_PREAMBLE_LENGTH BIT_5 ;- Bit 5-4 = 1-0\r
+#define CFIG_NO_LOOPBACK 0\r
+#define CFIG_INTERNAL_LOOPBACK BIT_6\r
+#define CFIG_EXT_LOOPBACK BIT_7\r
+#define CFIG_EXT_PIN_LOOPBACK BIT_6 OR BIT_7\r
+\r
+//- Byte 11 (Default Value = 0)\r
+#define CFIG_LINEAR_PRIORITY 0\r
+\r
+//- Byte 12 (Default Value = 60h)\r
+#define CFIG_LPRIORITY_MODE 0\r
+#define CFIG_IFS 6 ;- 6 * 16 = 96\r
+\r
+//- Byte 13 (Default Value = 0, ALWAYS)\r
+\r
+//- Byte 14 (Default Value = 0F2h, ALWAYS)\r
+\r
+//- Byte 15 (Default Value = E8h)\r
+#define CFIG_PROMISCUOUS_MODE BIT_0\r
+#define CFIG_BROADCAST_DISABLE BIT_1\r
+#define CFIG_CRS_CDT BIT_7\r
+\r
+//- Byte 16 (Default Value = 0, ALWAYS)\r
+\r
+//- Byte 17 (Default Value = 40h, ALWAYS)\r
+\r
+//- Byte 18 (Default Value = F2h)\r
+#define CFIG_STRIPPING BIT_0\r
+#define CFIG_PADDING BIT_1\r
+#define CFIG_RX_CRC_TRANSFER BIT_2\r
+\r
+//- Byte 19 (Default Value = 80h)\r
+#define CFIG_FORCE_FDX BIT_6\r
+#define CFIG_FDX_PIN_ENABLE BIT_7\r
+\r
+//- Byte 20 (Default Value = 3Fh)\r
+#define CFIG_MULTI_IA BIT_6\r
+\r
+//- Byte 21 (Default Value = 05)\r
+#define CFIG_MC_ALL BIT_3\r
+\r
+/*-----------------------------------------------------------------------*/\r
+#define D102_REVID 0x0b\r
+\r
+#define HALF_DUPLEX 1\r
+#define FULL_DUPLEX 2\r
+\r
+typedef struct s_data_instance {\r
+\r
+ UINT16 State; // stopped, started or initialized\r
+ UINT16 Bus;\r
+ UINT8 Device;\r
+ UINT8 Function;\r
+ UINT16 VendorID;\r
+ UINT16 DeviceID;\r
+ UINT16 RevID;\r
+ UINT16 SubVendorID;\r
+ UINT16 SubSystemID;\r
+\r
+ UINT8 PermNodeAddress[PXE_MAC_LENGTH];\r
+ UINT8 CurrentNodeAddress[PXE_MAC_LENGTH];\r
+ UINT8 BroadcastNodeAddress[PXE_MAC_LENGTH];\r
+ UINT32 Config[MAX_PCI_CONFIG_LEN];\r
+ UINT32 NVData[MAX_EEPROM_LEN];\r
+\r
+ UINT32 ioaddr;\r
+ UINT32 flash_addr;\r
+\r
+ UINT16 LinkSpeed; // actual link speed setting\r
+ UINT16 LinkSpeedReq; // requested (forced) link speed\r
+ UINT8 DuplexReq; // requested duplex\r
+ UINT8 Duplex; // Duplex set\r
+ UINT8 CableDetect; // 1 to detect and 0 not to detect the cable\r
+ UINT8 LoopBack;\r
+\r
+ UINT16 TxBufCnt;\r
+ UINT16 TxBufSize;\r
+ UINT16 RxBufCnt;\r
+ UINT16 RxBufSize;\r
+ UINT32 RxTotals;\r
+ UINT32 TxTotals;\r
+\r
+ UINT16 int_mask;\r
+ UINT16 Int_Status;\r
+ UINT16 PhyRecord[2]; // primary and secondary PHY record registers from eeprom\r
+ UINT8 PhyAddress;\r
+ UINT8 int_num;\r
+ UINT16 NVData_Len;\r
+ UINT32 MemoryLength;\r
+\r
+ RxFD *rx_ring; // array of rx buffers\r
+ TxCB *tx_ring; // array of tx buffers\r
+ struct speedo_stats *statistics;\r
+ TxCB *FreeTxHeadPtr;\r
+ TxCB *FreeTxTailPtr;\r
+ RxFD *RFDTailPtr;\r
+\r
+ UINT64 rx_phy_addr; // physical addresses\r
+ UINT64 tx_phy_addr;\r
+ UINT64 stat_phy_addr;\r
+ UINT64 MemoryPtr;\r
+ UINT64 Mapped_MemoryPtr;\r
+\r
+ UINT64 xmit_done[TX_BUFFER_COUNT << 1]; // circular buffer\r
+ UINT16 xmit_done_head; // index into the xmit_done array\r
+ UINT16 xmit_done_tail; // where are we filling now (index into xmit_done)\r
+ UINT16 cur_rx_ind; // current RX Q head index\r
+ UINT16 FreeCBCount;\r
+\r
+ BOOLEAN in_interrupt;\r
+ BOOLEAN in_transmit;\r
+ BOOLEAN Receive_Started;\r
+ UINT8 Rx_Filter;\r
+ UINT8 VersionFlag; // UNDI30 or UNDI31??\r
+ UINT8 rsvd[3];\r
+\r
+ struct mc{\r
+ UINT16 reserved [3]; // padding for this structure to make it 8 byte aligned\r
+ UINT16 list_len;\r
+ UINT8 mc_list[MAX_MCAST_ADDRESS_CNT][PXE_MAC_LENGTH]; // 8*32 is the size\r
+ } mcast_list;\r
+\r
+ UINT64 Unique_ID;\r
+\r
+ EFI_PCI_IO_PROTOCOL *Io_Function;\r
+ //\r
+ // Original PCI attributes\r
+ //\r
+ UINT64 OriginalPciAttributes;\r
+\r
+ VOID (*Delay_30)(UINTN); // call back routine\r
+ VOID (*Virt2Phys_30)(UINT64 virtual_addr, UINT64 physical_ptr); // call back routine\r
+ VOID (*Block_30)(UINT32 enable); // call back routine\r
+ VOID (*Mem_Io_30)(UINT8 read_write, UINT8 len, UINT64 port, UINT64 buf_addr);\r
+ VOID (*Delay)(UINT64, UINTN); // call back routine\r
+ VOID (*Virt2Phys)(UINT64 unq_id, UINT64 virtual_addr, UINT64 physical_ptr); // call back routine\r
+ VOID (*Block)(UINT64 unq_id, UINT32 enable); // call back routine\r
+ VOID (*Mem_Io)(UINT64 unq_id, UINT8 read_write, UINT8 len, UINT64 port,\r
+ UINT64 buf_addr);\r
+ VOID (*Map_Mem)(UINT64 unq_id, UINT64 virtual_addr, UINT32 size,\r
+ UINT32 Direction, UINT64 mapped_addr);\r
+ VOID (*UnMap_Mem)(UINT64 unq_id, UINT64 virtual_addr, UINT32 size,\r
+ UINT32 Direction, UINT64 mapped_addr);\r
+ VOID (*Sync_Mem)(UINT64 unq_id, UINT64 virtual_addr,\r
+ UINT32 size, UINT32 Direction, UINT64 mapped_addr);\r
+} NIC_DATA_INSTANCE;\r
+\r
+#pragma pack(1)\r
+struct MC_CB_STRUCT{\r
+ UINT16 count;\r
+ UINT8 m_list[MAX_MCAST_ADDRESS_CNT][ETHER_MAC_ADDR_LEN];\r
+};\r
+#pragma pack()\r
+\r
+#define FOUR_GIGABYTE (UINT64)0x100000000ULL\r
+\r
+#endif\r
+\r
projects / mirror_edk2.git / blobdiff