--- /dev/null
+/** @file\r
+ OVMF Platform definitions\r
+\r
+ Copyright (c) 2014, Gabriel L. Somlo <somlo@cmu.edu>\r
+\r
+ This program and the accompanying materials are licensed and made\r
+ available under the terms and conditions of the BSD License which\r
+ accompanies this distribution. The full text of the license may\r
+ be found at http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+**/\r
+\r
+#ifndef __OVMF_PLATFORMS_H__\r
+#define __OVMF_PLATFORMS_H__\r
+\r
+#include <Library/PciLib.h>\r
+#include <IndustryStandard/Pci22.h>\r
+\r
+//\r
+// Host Bridge Device ID (DID) values for PIIX4 and Q35/MCH\r
+//\r
+#define INTEL_82441_DEVICE_ID 0x1237 // PIIX4\r
+#define INTEL_Q35_MCH_DEVICE_ID 0x29C0 // Q35\r
+\r
+//\r
+// OVMF Host Bridge DID Address\r
+//\r
+#define OVMF_HOSTBRIDGE_DID \\r
+ PCI_LIB_ADDRESS (0, 0, 0, PCI_DEVICE_ID_OFFSET)\r
+\r
+//\r
+// Power Management Device and Function numbers for PIIX4 and Q35/MCH\r
+//\r
+#define OVMF_PM_DEVICE_PIIX4 0x01\r
+#define OVMF_PM_FUNC_PIIX4 0x03\r
+#define OVMF_PM_DEVICE_Q35 0x1f\r
+#define OVMF_PM_FUNC_Q35 0x00\r
+\r
+//\r
+// Power Management Register access for PIIX4 and Q35/MCH\r
+//\r
+#define POWER_MGMT_REGISTER_PIIX4(Offset) \\r
+ PCI_LIB_ADDRESS (0, OVMF_PM_DEVICE_PIIX4, OVMF_PM_FUNC_PIIX4, (Offset))\r
+#define POWER_MGMT_REGISTER_Q35(Offset) \\r
+ PCI_LIB_ADDRESS (0, OVMF_PM_DEVICE_Q35, OVMF_PM_FUNC_Q35, (Offset))\r
+\r
+#endif\r