\r
Virtual Memory Management Services to set or clear the memory encryption bit\r
\r
-Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>\r
-Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r
+ Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r
\r
-This program and the accompanying materials\r
-are licensed and made available under the terms and conditions of the BSD License\r
-which accompanies this distribution. The full text of the license may be found at\r
-http://opensource.org/licenses/bsd-license.php\r
+ This program and the accompanying materials are licensed and made available\r
+ under the terms and conditions of the BSD License which accompanies this\r
+ distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
\r
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT\r
+ WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
-Code is derived from MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.h\r
+ Code is derived from MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.h\r
\r
**/\r
\r
\r
typedef union {\r
struct {\r
- UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory\r
+ UINT64 Present:1; // 0 = Not present in memory,\r
+ // 1 = Present in memory\r
UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write\r
UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User\r
- UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching\r
+ UINT64 WriteThrough:1; // 0 = Write-Back caching,\r
+ // 1 = Write-Through caching\r
UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached\r
- UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)\r
+ UINT64 Accessed:1; // 0 = Not accessed,\r
+ // 1 = Accessed (set by CPU)\r
UINT64 Reserved:1; // Reserved\r
UINT64 MustBeZero:2; // Must Be Zero\r
UINT64 Available:3; // Available for use by system software\r
//\r
typedef union {\r
struct {\r
- UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory\r
+ UINT64 Present:1; // 0 = Not present in memory,\r
+ // 1 = Present in memory\r
UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write\r
UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User\r
- UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching\r
+ UINT64 WriteThrough:1; // 0 = Write-Back caching,\r
+ // 1 = Write-Through caching\r
UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached\r
- UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)\r
- UINT64 Dirty:1; // 0 = Not Dirty, 1 = written by processor on access to page\r
+ UINT64 Accessed:1; // 0 = Not accessed,\r
+ // 1 = Accessed (set by CPU)\r
+ UINT64 Dirty:1; // 0 = Not Dirty, 1 = written by\r
+ // processor on access to page\r
UINT64 PAT:1; //\r
- UINT64 Global:1; // 0 = Not global page, 1 = global page TLB not cleared on CR3 write\r
+ UINT64 Global:1; // 0 = Not global page, 1 = global page\r
+ // TLB not cleared on CR3 write\r
UINT64 Available:3; // Available for use by system software\r
UINT64 PageTableBaseAddress:40; // Page Table Base Address\r
UINT64 AvabilableHigh:11; // Available for use by system software\r
- UINT64 Nx:1; // 0 = Execute Code, 1 = No Code Execution\r
+ UINT64 Nx:1; // 0 = Execute Code,\r
+ // 1 = No Code Execution\r
} Bits;\r
UINT64 Uint64;\r
} PAGE_TABLE_4K_ENTRY;\r
//\r
typedef union {\r
struct {\r
- UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory\r
+ UINT64 Present:1; // 0 = Not present in memory,\r
+ // 1 = Present in memory\r
UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write\r
UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User\r
- UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching\r
+ UINT64 WriteThrough:1; // 0 = Write-Back caching,\r
+ // 1=Write-Through caching\r
UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached\r
- UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)\r
- UINT64 Dirty:1; // 0 = Not Dirty, 1 = written by processor on access to page\r
+ UINT64 Accessed:1; // 0 = Not accessed,\r
+ // 1 = Accessed (set by CPU)\r
+ UINT64 Dirty:1; // 0 = Not Dirty, 1 = written by\r
+ // processor on access to page\r
UINT64 MustBe1:1; // Must be 1\r
- UINT64 Global:1; // 0 = Not global page, 1 = global page TLB not cleared on CR3 write\r
+ UINT64 Global:1; // 0 = Not global page, 1 = global page\r
+ // TLB not cleared on CR3 write\r
UINT64 Available:3; // Available for use by system software\r
UINT64 PAT:1; //\r
UINT64 MustBeZero:8; // Must be zero;\r
UINT64 PageTableBaseAddress:31; // Page Table Base Address\r
UINT64 AvabilableHigh:11; // Available for use by system software\r
- UINT64 Nx:1; // 0 = Execute Code, 1 = No Code Execution\r
+ UINT64 Nx:1; // 0 = Execute Code,\r
+ // 1 = No Code Execution\r
} Bits;\r
UINT64 Uint64;\r
} PAGE_TABLE_ENTRY;\r
//\r
typedef union {\r
struct {\r
- UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory\r
+ UINT64 Present:1; // 0 = Not present in memory,\r
+ // 1 = Present in memory\r
UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write\r
UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User\r
- UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching\r
+ UINT64 WriteThrough:1; // 0 = Write-Back caching,\r
+ // 1 = Write-Through caching\r
UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached\r
- UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)\r
- UINT64 Dirty:1; // 0 = Not Dirty, 1 = written by processor on access to page\r
+ UINT64 Accessed:1; // 0 = Not accessed,\r
+ // 1 = Accessed (set by CPU)\r
+ UINT64 Dirty:1; // 0 = Not Dirty, 1 = written by\r
+ // processor on access to page\r
UINT64 MustBe1:1; // Must be 1\r
- UINT64 Global:1; // 0 = Not global page, 1 = global page TLB not cleared on CR3 write\r
+ UINT64 Global:1; // 0 = Not global page, 1 = global page\r
+ // TLB not cleared on CR3 write\r
UINT64 Available:3; // Available for use by system software\r
UINT64 PAT:1; //\r
UINT64 MustBeZero:17; // Must be zero;\r
UINT64 PageTableBaseAddress:22; // Page Table Base Address\r
UINT64 AvabilableHigh:11; // Available for use by system software\r
- UINT64 Nx:1; // 0 = Execute Code, 1 = No Code Execution\r
+ UINT64 Nx:1; // 0 = Execute Code,\r
+ // 1 = No Code Execution\r
} Bits;\r
UINT64 Uint64;\r
} PAGE_TABLE_1G_ENTRY;\r
\r
#define PAGE_TABLE_POOL_ALIGNMENT BASE_2MB\r
#define PAGE_TABLE_POOL_UNIT_SIZE SIZE_2MB\r
-#define PAGE_TABLE_POOL_UNIT_PAGES EFI_SIZE_TO_PAGES (PAGE_TABLE_POOL_UNIT_SIZE)\r
+#define PAGE_TABLE_POOL_UNIT_PAGES \\r
+ EFI_SIZE_TO_PAGES (PAGE_TABLE_POOL_UNIT_SIZE)\r
#define PAGE_TABLE_POOL_ALIGN_MASK \\r
(~(EFI_PHYSICAL_ADDRESS)(PAGE_TABLE_POOL_ALIGNMENT - 1))\r
\r
\r
\r
/**\r
- This function clears memory encryption bit for the memory region specified by PhysicalAddress\r
- and length from the current page table context.\r
+ This function clears memory encryption bit for the memory region specified by\r
+ PhysicalAddress and length from the current page table context.\r
\r
- @param[in] PhysicalAddress The physical address that is the start address of a memory region.\r
+ @param[in] PhysicalAddress The physical address that is the start\r
+ address of a memory region.\r
@param[in] Length The length of memory region\r
- @param[in] Flush Flush the caches before applying the encryption mask\r
+ @param[in] Flush Flush the caches before applying the\r
+ encryption mask\r
\r
- @retval RETURN_SUCCESS The attributes were cleared for the memory region.\r
+ @retval RETURN_SUCCESS The attributes were cleared for the\r
+ memory region.\r
@retval RETURN_INVALID_PARAMETER Number of pages is zero.\r
- @retval RETURN_UNSUPPORTED Setting the memory encyrption attribute is not supported\r
+ @retval RETURN_UNSUPPORTED Setting the memory encyrption attribute\r
+ is not supported\r
**/\r
RETURN_STATUS\r
EFIAPI\r
This function sets memory encryption bit for the memory region specified by\r
PhysicalAddress and length from the current page table context.\r
\r
- @param[in] PhysicalAddress The physical address that is the start address\r
- of a memory region.\r
+ @param[in] PhysicalAddress The physical address that is the start\r
+ address of a memory region.\r
@param[in] Length The length of memory region\r
@param[in] Flush Flush the caches before applying the\r
encryption mask\r
\r
- @retval RETURN_SUCCESS The attributes were cleared for the memory region.\r
+ @retval RETURN_SUCCESS The attributes were cleared for the\r
+ memory region.\r
@retval RETURN_INVALID_PARAMETER Number of pages is zero.\r
- @retval RETURN_UNSUPPORTED Setting the memory encyrption attribute is\r
- not supported\r
+ @retval RETURN_UNSUPPORTED Setting the memory encyrption attribute\r
+ is not supported\r
**/\r
RETURN_STATUS\r
EFIAPI\r
projects / mirror_edk2.git / blobdiff