\r
Copyright (c) 2011 - 2013, Intel Corporation. All rights reserved.<BR>\r
Copyright (C) 2013, Red Hat, Inc.\r
+ Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r
\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
#include "QemuFwCfgLibInternal.h"\r
\r
\r
-/**\r
- Reads an 8-bit I/O port fifo into a block of memory.\r
-\r
- Reads the 8-bit I/O fifo port specified by Port.\r
-\r
- The port is read Count times, and the read data is\r
- stored in the provided Buffer.\r
-\r
- This function must guarantee that all I/O read and write operations are\r
- serialized.\r
-\r
- If 8-bit I/O port operations are not supported, then ASSERT().\r
-\r
- @param Port The I/O port to read.\r
- @param Count The number of times to read I/O port.\r
- @param Buffer The buffer to store the read data into.\r
-\r
-**/\r
-VOID\r
-EFIAPI\r
-IoReadFifo8 (\r
- IN UINTN Port,\r
- IN UINTN Count,\r
- OUT VOID *Buffer\r
- );\r
-\r
-/**\r
- Writes an 8-bit I/O port fifo from a block of memory.\r
-\r
- Writes the 8-bit I/O fifo port specified by Port.\r
-\r
- The port is written Count times, and the data are obtained\r
- from the provided Buffer.\r
-\r
- This function must guarantee that all I/O read and write operations are\r
- serialized.\r
-\r
- If 8-bit I/O port operations are not supported, then ASSERT().\r
-\r
- @param Port The I/O port to read.\r
- @param Count The number of times to read I/O port.\r
- @param Buffer The buffer to store the read data into.\r
-\r
-**/\r
-VOID\r
-EFIAPI\r
-IoWriteFifo8 (\r
- IN UINTN Port,\r
- IN UINTN Count,\r
- OUT VOID *Buffer\r
- );\r
-\r
-\r
/**\r
Selects a firmware configuration item for reading.\r
\r
}\r
\r
\r
+/**\r
+ Transfer an array of bytes using the DMA interface.\r
+\r
+ @param[in] Size Size in bytes to transfer.\r
+ @param[in,out] Buffer Buffer to read data into or write data from. May be\r
+ NULL if Size is zero.\r
+ @param[in] Write TRUE if writing to fw_cfg from Buffer, FALSE if\r
+ reading from fw_cfg into Buffer.\r
+**/\r
+VOID\r
+InternalQemuFwCfgDmaBytes (\r
+ IN UINT32 Size,\r
+ IN OUT VOID *Buffer OPTIONAL,\r
+ IN BOOLEAN Write\r
+ )\r
+{\r
+ volatile FW_CFG_DMA_ACCESS Access;\r
+ UINT32 AccessHigh, AccessLow;\r
+ UINT32 Status;\r
+\r
+ if (Size == 0) {\r
+ return;\r
+ }\r
+\r
+ Access.Control = SwapBytes32 (\r
+ Write ? FW_CFG_DMA_CTL_WRITE : FW_CFG_DMA_CTL_READ\r
+ );\r
+ Access.Length = SwapBytes32 (Size);\r
+ Access.Address = SwapBytes64 ((UINTN)Buffer);\r
+\r
+ //\r
+ // Delimit the transfer from (a) modifications to Access, (b) in case of a\r
+ // write, from writes to Buffer by the caller.\r
+ //\r
+ MemoryFence ();\r
+\r
+ //\r
+ // Start the transfer.\r
+ //\r
+ AccessHigh = (UINT32)RShiftU64 ((UINTN)&Access, 32);\r
+ AccessLow = (UINT32)(UINTN)&Access;\r
+ IoWrite32 (0x514, SwapBytes32 (AccessHigh));\r
+ IoWrite32 (0x518, SwapBytes32 (AccessLow));\r
+\r
+ //\r
+ // Don't look at Access.Control before starting the transfer.\r
+ //\r
+ MemoryFence ();\r
+\r
+ //\r
+ // Wait for the transfer to complete.\r
+ //\r
+ do {\r
+ Status = SwapBytes32 (Access.Control);\r
+ ASSERT ((Status & FW_CFG_DMA_CTL_ERROR) == 0);\r
+ } while (Status != 0);\r
+\r
+ //\r
+ // After a read, the caller will want to use Buffer.\r
+ //\r
+ MemoryFence ();\r
+}\r
+\r
+\r
/**\r
Reads firmware configuration bytes into a buffer\r
\r
IN VOID *Buffer OPTIONAL\r
)\r
{\r
+ if (InternalQemuFwCfgDmaIsAvailable () && Size <= MAX_UINT32) {\r
+ InternalQemuFwCfgDmaBytes ((UINT32)Size, Buffer, FALSE);\r
+ return;\r
+ }\r
IoReadFifo8 (0x511, Size, Buffer);\r
}\r
\r
)\r
{\r
if (InternalQemuFwCfgIsAvailable ()) {\r
+ if (InternalQemuFwCfgDmaIsAvailable () && Size <= MAX_UINT32) {\r
+ InternalQemuFwCfgDmaBytes ((UINT32)Size, Buffer, TRUE);\r
+ return;\r
+ }\r
IoWriteFifo8 (0x511, Size, Buffer);\r
}\r
}\r