OvmfPkg: SmmCpuFeaturesLib: customize state save map format

[mirror_edk2.git] / OvmfPkg / Library / SmmCpuFeaturesLib / SmmCpuFeaturesLib.c

diff --git a/OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c b/OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c
index b3d0e3a8fb5b4c7f9a7be96b9c1d5a40f3802a26..a307f64c9c6123963a6f1748fe9716057bc77040 100644 (file)
--- a/OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c
+++ b/OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c
@@ -20,7 +20,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 #include <Library/MemoryAllocationLib.h>\r
 #include <Library/SmmServicesTableLib.h>\r
 #include <Library/DebugLib.h>\r
-#include <Register/SmramSaveStateMap.h>\r
+#include <Register/QemuSmramSaveStateMap.h>\r
 \r
 //\r
 // EFER register LMA bit\r
@@ -82,13 +82,17 @@ SmmCpuFeaturesInitializeProcessor (
   IN CPU_HOT_PLUG_DATA          *CpuHotPlugData\r
   )\r
 {\r
-  SMRAM_SAVE_STATE_MAP  *CpuState;\r
+  QEMU_SMRAM_SAVE_STATE_MAP  *CpuState;\r
 \r
   //\r
   // Configure SMBASE.\r
   //\r
-  CpuState = (SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET);\r
-  CpuState->x86.SMBASE = (UINT32)CpuHotPlugData->SmBase[CpuIndex];\r
+  CpuState = (QEMU_SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET);\r
+  if ((CpuState->x86.SMMRevId & 0xFFFF) == 0) {\r
+    CpuState->x86.SMBASE = (UINT32)CpuHotPlugData->SmBase[CpuIndex];\r
+  } else {\r
+    CpuState->x64.SMBASE = (UINT32)CpuHotPlugData->SmBase[CpuIndex];\r
+  }\r
 \r
   //\r
   // No need to program SMRRs on our virtual platform.\r
@@ -135,8 +139,8 @@ SmmCpuFeaturesHookReturnFromSmm (
   IN UINT64                NewInstructionPointer\r
   )\r
 {\r
-  UINT64                 OriginalInstructionPointer;\r
-  SMRAM_SAVE_STATE_MAP  *CpuSaveState = (SMRAM_SAVE_STATE_MAP *)CpuState;\r
+  UINT64                      OriginalInstructionPointer;\r
+  QEMU_SMRAM_SAVE_STATE_MAP  *CpuSaveState = (QEMU_SMRAM_SAVE_STATE_MAP *)CpuState;\r
 \r
   if ((CpuSaveState->x86.SMMRevId & 0xFFFF) == 0) {\r
     OriginalInstructionPointer = (UINT64)CpuSaveState->x86._EIP;\r
@@ -397,7 +401,7 @@ SmmCpuFeaturesSetSmmRegister (
 ///\r
 /// Macro used to simplify the lookup table entries of type CPU_SMM_SAVE_STATE_LOOKUP_ENTRY\r
 ///\r
-#define SMM_CPU_OFFSET(Field) OFFSET_OF (SMRAM_SAVE_STATE_MAP, Field)\r
+#define SMM_CPU_OFFSET(Field) OFFSET_OF (QEMU_SMRAM_SAVE_STATE_MAP, Field)\r
 \r
 ///\r
 /// Macro used to simplify the lookup table entries of type CPU_SMM_SAVE_STATE_REGISTER_RANGE\r
@@ -450,13 +454,13 @@ static CONST CPU_SMM_SAVE_STATE_LOOKUP_ENTRY mSmmCpuWidthOffset[] = {
   //\r
   // CPU Save State registers defined in PI SMM CPU Protocol.\r
   //\r
-  {0, 8, 0                            , SMM_CPU_OFFSET (x64.GdtBaseLoDword) , SMM_CPU_OFFSET (x64.GdtBaseHiDword), FALSE},  //  EFI_SMM_SAVE_STATE_REGISTER_GDTBASE  = 4\r
-  {0, 8, 0                            , SMM_CPU_OFFSET (x64.IdtBaseLoDword) , SMM_CPU_OFFSET (x64.IdtBaseHiDword), FALSE},  //  EFI_SMM_SAVE_STATE_REGISTER_IDTBASE  = 5\r
-  {0, 8, 0                            , SMM_CPU_OFFSET (x64.LdtBaseLoDword) , SMM_CPU_OFFSET (x64.LdtBaseHiDword), FALSE},  //  EFI_SMM_SAVE_STATE_REGISTER_LDTBASE  = 6\r
-  {0, 0, 0                            , 0                                   , 0                                  , FALSE},  //  EFI_SMM_SAVE_STATE_REGISTER_GDTLIMIT = 7\r
-  {0, 0, 0                            , 0                                   , 0                                  , FALSE},  //  EFI_SMM_SAVE_STATE_REGISTER_IDTLIMIT = 8\r
-  {0, 0, 0                            , 0                                   , 0                                  , FALSE},  //  EFI_SMM_SAVE_STATE_REGISTER_LDTLIMIT = 9\r
-  {0, 0, 0                            , 0                                   , 0                                  , FALSE},  //  EFI_SMM_SAVE_STATE_REGISTER_LDTINFO  = 10\r
+  {0, 8, 0                            , SMM_CPU_OFFSET (x64._GDTRBase) , SMM_CPU_OFFSET (x64._GDTRBase)  + 4, FALSE},  //  EFI_SMM_SAVE_STATE_REGISTER_GDTBASE  = 4\r
+  {0, 8, 0                            , SMM_CPU_OFFSET (x64._IDTRBase) , SMM_CPU_OFFSET (x64._IDTRBase)  + 4, FALSE},  //  EFI_SMM_SAVE_STATE_REGISTER_IDTBASE  = 5\r
+  {0, 8, 0                            , SMM_CPU_OFFSET (x64._LDTRBase) , SMM_CPU_OFFSET (x64._LDTRBase)  + 4, FALSE},  //  EFI_SMM_SAVE_STATE_REGISTER_LDTBASE  = 6\r
+  {0, 0, 0                            , SMM_CPU_OFFSET (x64._GDTRLimit), SMM_CPU_OFFSET (x64._GDTRLimit) + 4, FALSE},  //  EFI_SMM_SAVE_STATE_REGISTER_GDTLIMIT = 7\r
+  {0, 0, 0                            , SMM_CPU_OFFSET (x64._IDTRLimit), SMM_CPU_OFFSET (x64._IDTRLimit) + 4, FALSE},  //  EFI_SMM_SAVE_STATE_REGISTER_IDTLIMIT = 8\r
+  {0, 0, 0                            , SMM_CPU_OFFSET (x64._LDTRLimit), SMM_CPU_OFFSET (x64._LDTRLimit) + 4, FALSE},  //  EFI_SMM_SAVE_STATE_REGISTER_LDTLIMIT = 9\r
+  {0, 0, 0                            , 0                              , 0                               + 4, FALSE},  //  EFI_SMM_SAVE_STATE_REGISTER_LDTINFO  = 10\r
 \r
   {4, 4, SMM_CPU_OFFSET (x86._ES)     , SMM_CPU_OFFSET (x64._ES)     , 0                               , FALSE},  //  EFI_SMM_SAVE_STATE_REGISTER_ES       = 20\r
   {4, 4, SMM_CPU_OFFSET (x86._CS)     , SMM_CPU_OFFSET (x64._CS)     , 0                               , FALSE},  //  EFI_SMM_SAVE_STATE_REGISTER_CS       = 21\r
@@ -489,7 +493,7 @@ static CONST CPU_SMM_SAVE_STATE_LOOKUP_ENTRY mSmmCpuWidthOffset[] = {
   {4, 8, SMM_CPU_OFFSET (x86._EFLAGS) , SMM_CPU_OFFSET (x64._RFLAGS) , SMM_CPU_OFFSET (x64._RFLAGS) + 4, TRUE },  //  EFI_SMM_SAVE_STATE_REGISTER_RFLAGS   = 51\r
   {4, 8, SMM_CPU_OFFSET (x86._CR0)    , SMM_CPU_OFFSET (x64._CR0)    , SMM_CPU_OFFSET (x64._CR0)    + 4, FALSE},  //  EFI_SMM_SAVE_STATE_REGISTER_CR0      = 52\r
   {4, 8, SMM_CPU_OFFSET (x86._CR3)    , SMM_CPU_OFFSET (x64._CR3)    , SMM_CPU_OFFSET (x64._CR3)    + 4, FALSE},  //  EFI_SMM_SAVE_STATE_REGISTER_CR3      = 53\r
-  {0, 4, 0                            , SMM_CPU_OFFSET (x64._CR4)    , 0                               , FALSE},  //  EFI_SMM_SAVE_STATE_REGISTER_CR4      = 54\r
+  {0, 4, 0                            , SMM_CPU_OFFSET (x64._CR4)    , SMM_CPU_OFFSET (x64._CR4)    + 4, FALSE},  //  EFI_SMM_SAVE_STATE_REGISTER_CR4      = 54\r
 };\r
 \r
 //\r
@@ -548,9 +552,9 @@ ReadSaveStateRegisterByIndex (
   OUT VOID   *Buffer\r
   )\r
 {\r
-  SMRAM_SAVE_STATE_MAP  *CpuSaveState;\r
+  QEMU_SMRAM_SAVE_STATE_MAP  *CpuSaveState;\r
 \r
-  CpuSaveState = gSmst->CpuSaveState[CpuIndex];\r
+  CpuSaveState = (QEMU_SMRAM_SAVE_STATE_MAP *)gSmst->CpuSaveState[CpuIndex];\r
 \r
   if ((CpuSaveState->x86.SMMRevId & 0xFFFF) == 0) {\r
     //\r
@@ -628,8 +632,8 @@ SmmCpuFeaturesReadSaveStateRegister (
   OUT VOID                         *Buffer\r
   )\r
 {\r
-  UINTN                  RegisterIndex;\r
-  SMRAM_SAVE_STATE_MAP  *CpuSaveState;\r
+  UINTN                       RegisterIndex;\r
+  QEMU_SMRAM_SAVE_STATE_MAP  *CpuSaveState;\r
 \r
   //\r
   // Check for special EFI_SMM_SAVE_STATE_REGISTER_LMA\r
@@ -642,7 +646,7 @@ SmmCpuFeaturesReadSaveStateRegister (
       return EFI_INVALID_PARAMETER;\r
     }\r
 \r
-    CpuSaveState = gSmst->CpuSaveState[CpuIndex];\r
+    CpuSaveState = (QEMU_SMRAM_SAVE_STATE_MAP *)gSmst->CpuSaveState[CpuIndex];\r
 \r
     //\r
     // Check CPU mode\r
@@ -701,8 +705,8 @@ SmmCpuFeaturesWriteSaveStateRegister (
   IN CONST VOID                   *Buffer\r
   )\r
 {\r
-  UINTN                 RegisterIndex;\r
-  SMRAM_SAVE_STATE_MAP  *CpuSaveState;\r
+  UINTN                       RegisterIndex;\r
+  QEMU_SMRAM_SAVE_STATE_MAP  *CpuSaveState;\r
 \r
   //\r
   // Writes to EFI_SMM_SAVE_STATE_REGISTER_LMA are ignored\r
@@ -728,7 +732,7 @@ SmmCpuFeaturesWriteSaveStateRegister (
     return Register < EFI_SMM_SAVE_STATE_REGISTER_IO ? EFI_NOT_FOUND : EFI_UNSUPPORTED;\r
   }\r
 \r
-  CpuSaveState = gSmst->CpuSaveState[CpuIndex];\r
+  CpuSaveState = (QEMU_SMRAM_SAVE_STATE_MAP *)gSmst->CpuSaveState[CpuIndex];\r
 \r
   //\r
   // Do not write non-writable SaveState, because it will cause exception.\r