/** @file\r
-The CPU specific programming for PiSmmCpuDxeSmm module.\r
+ The CPU specific programming for PiSmmCpuDxeSmm module.\r
\r
-Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>\r
-This program and the accompanying materials\r
-are licensed and made available under the terms and conditions of the BSD License\r
-which accompanies this distribution. The full text of the license may be found at\r
-http://opensource.org/licenses/bsd-license.php\r
+ Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>\r
\r
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+ This program and the accompanying materials are licensed and made available\r
+ under the terms and conditions of the BSD License which accompanies this\r
+ distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT\r
+ WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
**/\r
\r
#include <PiSmm.h>\r
//\r
// Configure SMBASE.\r
//\r
- CpuState = (QEMU_SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET);\r
+ CpuState = (QEMU_SMRAM_SAVE_STATE_MAP *)(UINTN)(\r
+ SMM_DEFAULT_SMBASE +\r
+ SMRAM_SAVE_STATE_MAP_OFFSET\r
+ );\r
if ((CpuState->x86.SMMRevId & 0xFFFF) == 0) {\r
CpuState->x86.SMBASE = (UINT32)CpuHotPlugData->SmBase[CpuIndex];\r
} else {\r
\r
@param[in] CpuIndex The index of the CPU to hook. The value\r
must be between 0 and the NumberOfCpus\r
- field in the System Management System Table\r
- (SMST).\r
+ field in the System Management System\r
+ Table (SMST).\r
@param[in] CpuState Pointer to SMRAM Save State Map for the\r
currently executing CPU.\r
@param[in] NewInstructionPointer32 Instruction pointer to use if resuming to\r
)\r
{\r
UINT64 OriginalInstructionPointer;\r
- QEMU_SMRAM_SAVE_STATE_MAP *CpuSaveState = (QEMU_SMRAM_SAVE_STATE_MAP *)CpuState;\r
+ QEMU_SMRAM_SAVE_STATE_MAP *CpuSaveState;\r
\r
+ CpuSaveState = (QEMU_SMRAM_SAVE_STATE_MAP *)CpuState;\r
if ((CpuSaveState->x86.SMMRevId & 0xFFFF) == 0) {\r
OriginalInstructionPointer = (UINT64)CpuSaveState->x86._EIP;\r
CpuSaveState->x86._EIP = (UINT32)NewInstructionPointer;\r
and the default SMI handler must be used.\r
\r
@retval 0 Use the default SMI handler.\r
- @retval > 0 Use the SMI handler installed by SmmCpuFeaturesInstallSmiHandler()\r
- The caller is required to allocate enough SMRAM for each CPU to\r
- support the size of the custom SMI handler.\r
+ @retval > 0 Use the SMI handler installed by\r
+ SmmCpuFeaturesInstallSmiHandler(). The caller is required to\r
+ allocate enough SMRAM for each CPU to support the size of the\r
+ custom SMI handler.\r
**/\r
UINTN\r
EFIAPI\r
}\r
\r
/**\r
- Install a custom SMI handler for the CPU specified by CpuIndex. This function\r
- is only called if SmmCpuFeaturesGetSmiHandlerSize() returns a size is greater\r
- than zero and is called by the CPU that was elected as monarch during System\r
- Management Mode initialization.\r
+ Install a custom SMI handler for the CPU specified by CpuIndex. This\r
+ function is only called if SmmCpuFeaturesGetSmiHandlerSize() returns a size\r
+ is greater than zero and is called by the CPU that was elected as monarch\r
+ during System Management Mode initialization.\r
\r
@param[in] CpuIndex The index of the CPU to install the custom SMI handler.\r
The value must be between 0 and the NumberOfCpus field\r
}\r
\r
/**\r
- Disable SMRR register if SMRR is supported and SmmCpuFeaturesNeedConfigureMtrrs()\r
- returns TRUE.\r
+ Disable SMRR register if SMRR is supported and\r
+ SmmCpuFeaturesNeedConfigureMtrrs() returns TRUE.\r
**/\r
VOID\r
EFIAPI\r
}\r
\r
/**\r
- Enable SMRR register if SMRR is supported and SmmCpuFeaturesNeedConfigureMtrrs()\r
- returns TRUE.\r
+ Enable SMRR register if SMRR is supported and\r
+ SmmCpuFeaturesNeedConfigureMtrrs() returns TRUE.\r
**/\r
VOID\r
EFIAPI\r
/**\r
Processor specific hook point each time a CPU exits System Management Mode.\r
\r
- @param[in] CpuIndex The index of the CPU that is exiting SMM. The value must\r
- be between 0 and the NumberOfCpus field in the System\r
- Management System Table (SMST).\r
+ @param[in] CpuIndex The index of the CPU that is exiting SMM. The value\r
+ must be between 0 and the NumberOfCpus field in the\r
+ System Management System Table (SMST).\r
**/\r
VOID\r
EFIAPI\r
}\r
\r
///\r
-/// Macro used to simplify the lookup table entries of type CPU_SMM_SAVE_STATE_LOOKUP_ENTRY\r
+/// Macro used to simplify the lookup table entries of type\r
+/// CPU_SMM_SAVE_STATE_LOOKUP_ENTRY\r
///\r
#define SMM_CPU_OFFSET(Field) OFFSET_OF (QEMU_SMRAM_SAVE_STATE_MAP, Field)\r
\r
///\r
-/// Macro used to simplify the lookup table entries of type CPU_SMM_SAVE_STATE_REGISTER_RANGE\r
+/// Macro used to simplify the lookup table entries of type\r
+/// CPU_SMM_SAVE_STATE_REGISTER_RANGE\r
///\r
#define SMM_REGISTER_RANGE(Start, End) { Start, End, End - Start + 1 }\r
\r
} CPU_SMM_SAVE_STATE_LOOKUP_ENTRY;\r
\r
///\r
-/// Table used by GetRegisterIndex() to convert an EFI_SMM_SAVE_STATE_REGISTER \r
+/// Table used by GetRegisterIndex() to convert an EFI_SMM_SAVE_STATE_REGISTER\r
/// value to an index into a table of type CPU_SMM_SAVE_STATE_LOOKUP_ENTRY\r
///\r
static CONST CPU_SMM_SAVE_STATE_REGISTER_RANGE mSmmCpuRegisterRanges[] = {\r
- SMM_REGISTER_RANGE (EFI_SMM_SAVE_STATE_REGISTER_GDTBASE, EFI_SMM_SAVE_STATE_REGISTER_LDTINFO),\r
- SMM_REGISTER_RANGE (EFI_SMM_SAVE_STATE_REGISTER_ES, EFI_SMM_SAVE_STATE_REGISTER_RIP),\r
- SMM_REGISTER_RANGE (EFI_SMM_SAVE_STATE_REGISTER_RFLAGS, EFI_SMM_SAVE_STATE_REGISTER_CR4),\r
+ SMM_REGISTER_RANGE (\r
+ EFI_SMM_SAVE_STATE_REGISTER_GDTBASE,\r
+ EFI_SMM_SAVE_STATE_REGISTER_LDTINFO\r
+ ),\r
+ SMM_REGISTER_RANGE (\r
+ EFI_SMM_SAVE_STATE_REGISTER_ES,\r
+ EFI_SMM_SAVE_STATE_REGISTER_RIP\r
+ ),\r
+ SMM_REGISTER_RANGE (\r
+ EFI_SMM_SAVE_STATE_REGISTER_RFLAGS,\r
+ EFI_SMM_SAVE_STATE_REGISTER_CR4\r
+ ),\r
{ (EFI_SMM_SAVE_STATE_REGISTER)0, (EFI_SMM_SAVE_STATE_REGISTER)0, 0 }\r
};\r
\r
///\r
-/// Lookup table used to retrieve the widths and offsets associated with each \r
-/// supported EFI_SMM_SAVE_STATE_REGISTER value \r
+/// Lookup table used to retrieve the widths and offsets associated with each\r
+/// supported EFI_SMM_SAVE_STATE_REGISTER value\r
///\r
static CONST CPU_SMM_SAVE_STATE_LOOKUP_ENTRY mSmmCpuWidthOffset[] = {\r
- {0, 0, 0, 0, 0, FALSE}, // Reserved\r
+ {\r
+ 0, // Width32\r
+ 0, // Width64\r
+ 0, // Offset32\r
+ 0, // Offset64Lo\r
+ 0, // Offset64Hi\r
+ FALSE // Writeable\r
+ }, // Reserved\r
\r
//\r
// CPU Save State registers defined in PI SMM CPU Protocol.\r
//\r
- {0, 8, 0 , SMM_CPU_OFFSET (x64._GDTRBase) , SMM_CPU_OFFSET (x64._GDTRBase) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_GDTBASE = 4\r
- {0, 8, 0 , SMM_CPU_OFFSET (x64._IDTRBase) , SMM_CPU_OFFSET (x64._IDTRBase) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_IDTBASE = 5\r
- {0, 8, 0 , SMM_CPU_OFFSET (x64._LDTRBase) , SMM_CPU_OFFSET (x64._LDTRBase) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_LDTBASE = 6\r
- {0, 0, 0 , SMM_CPU_OFFSET (x64._GDTRLimit), SMM_CPU_OFFSET (x64._GDTRLimit) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_GDTLIMIT = 7\r
- {0, 0, 0 , SMM_CPU_OFFSET (x64._IDTRLimit), SMM_CPU_OFFSET (x64._IDTRLimit) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_IDTLIMIT = 8\r
- {0, 0, 0 , SMM_CPU_OFFSET (x64._LDTRLimit), SMM_CPU_OFFSET (x64._LDTRLimit) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_LDTLIMIT = 9\r
- {0, 0, 0 , 0 , 0 + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_LDTINFO = 10\r
-\r
- {4, 4, SMM_CPU_OFFSET (x86._ES) , SMM_CPU_OFFSET (x64._ES) , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_ES = 20\r
- {4, 4, SMM_CPU_OFFSET (x86._CS) , SMM_CPU_OFFSET (x64._CS) , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_CS = 21\r
- {4, 4, SMM_CPU_OFFSET (x86._SS) , SMM_CPU_OFFSET (x64._SS) , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_SS = 22\r
- {4, 4, SMM_CPU_OFFSET (x86._DS) , SMM_CPU_OFFSET (x64._DS) , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_DS = 23\r
- {4, 4, SMM_CPU_OFFSET (x86._FS) , SMM_CPU_OFFSET (x64._FS) , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_FS = 24\r
- {4, 4, SMM_CPU_OFFSET (x86._GS) , SMM_CPU_OFFSET (x64._GS) , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_GS = 25\r
- {0, 4, 0 , SMM_CPU_OFFSET (x64._LDTR) , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_LDTR_SEL = 26\r
- {4, 4, SMM_CPU_OFFSET (x86._TR) , SMM_CPU_OFFSET (x64._TR) , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_TR_SEL = 27\r
- {4, 8, SMM_CPU_OFFSET (x86._DR7) , SMM_CPU_OFFSET (x64._DR7) , SMM_CPU_OFFSET (x64._DR7) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_DR7 = 28\r
- {4, 8, SMM_CPU_OFFSET (x86._DR6) , SMM_CPU_OFFSET (x64._DR6) , SMM_CPU_OFFSET (x64._DR6) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_DR6 = 29\r
- {0, 8, 0 , SMM_CPU_OFFSET (x64._R8) , SMM_CPU_OFFSET (x64._R8) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R8 = 30\r
- {0, 8, 0 , SMM_CPU_OFFSET (x64._R9) , SMM_CPU_OFFSET (x64._R9) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R9 = 31\r
- {0, 8, 0 , SMM_CPU_OFFSET (x64._R10) , SMM_CPU_OFFSET (x64._R10) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R10 = 32\r
- {0, 8, 0 , SMM_CPU_OFFSET (x64._R11) , SMM_CPU_OFFSET (x64._R11) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R11 = 33\r
- {0, 8, 0 , SMM_CPU_OFFSET (x64._R12) , SMM_CPU_OFFSET (x64._R12) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R12 = 34\r
- {0, 8, 0 , SMM_CPU_OFFSET (x64._R13) , SMM_CPU_OFFSET (x64._R13) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R13 = 35\r
- {0, 8, 0 , SMM_CPU_OFFSET (x64._R14) , SMM_CPU_OFFSET (x64._R14) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R14 = 36\r
- {0, 8, 0 , SMM_CPU_OFFSET (x64._R15) , SMM_CPU_OFFSET (x64._R15) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R15 = 37\r
- {4, 8, SMM_CPU_OFFSET (x86._EAX) , SMM_CPU_OFFSET (x64._RAX) , SMM_CPU_OFFSET (x64._RAX) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RAX = 38\r
- {4, 8, SMM_CPU_OFFSET (x86._EBX) , SMM_CPU_OFFSET (x64._RBX) , SMM_CPU_OFFSET (x64._RBX) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RBX = 39\r
- {4, 8, SMM_CPU_OFFSET (x86._ECX) , SMM_CPU_OFFSET (x64._RCX) , SMM_CPU_OFFSET (x64._RCX) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RCX = 40\r
- {4, 8, SMM_CPU_OFFSET (x86._EDX) , SMM_CPU_OFFSET (x64._RDX) , SMM_CPU_OFFSET (x64._RDX) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RDX = 41\r
- {4, 8, SMM_CPU_OFFSET (x86._ESP) , SMM_CPU_OFFSET (x64._RSP) , SMM_CPU_OFFSET (x64._RSP) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RSP = 42\r
- {4, 8, SMM_CPU_OFFSET (x86._EBP) , SMM_CPU_OFFSET (x64._RBP) , SMM_CPU_OFFSET (x64._RBP) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RBP = 43\r
- {4, 8, SMM_CPU_OFFSET (x86._ESI) , SMM_CPU_OFFSET (x64._RSI) , SMM_CPU_OFFSET (x64._RSI) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RSI = 44\r
- {4, 8, SMM_CPU_OFFSET (x86._EDI) , SMM_CPU_OFFSET (x64._RDI) , SMM_CPU_OFFSET (x64._RDI) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RDI = 45\r
- {4, 8, SMM_CPU_OFFSET (x86._EIP) , SMM_CPU_OFFSET (x64._RIP) , SMM_CPU_OFFSET (x64._RIP) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RIP = 46\r
-\r
- {4, 8, SMM_CPU_OFFSET (x86._EFLAGS) , SMM_CPU_OFFSET (x64._RFLAGS) , SMM_CPU_OFFSET (x64._RFLAGS) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RFLAGS = 51\r
- {4, 8, SMM_CPU_OFFSET (x86._CR0) , SMM_CPU_OFFSET (x64._CR0) , SMM_CPU_OFFSET (x64._CR0) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_CR0 = 52\r
- {4, 8, SMM_CPU_OFFSET (x86._CR3) , SMM_CPU_OFFSET (x64._CR3) , SMM_CPU_OFFSET (x64._CR3) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_CR3 = 53\r
- {0, 4, 0 , SMM_CPU_OFFSET (x64._CR4) , SMM_CPU_OFFSET (x64._CR4) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_CR4 = 54\r
+ {\r
+ 0, // Width32\r
+ 8, // Width64\r
+ 0, // Offset32\r
+ SMM_CPU_OFFSET (x64._GDTRBase), // Offset64Lo\r
+ SMM_CPU_OFFSET (x64._GDTRBase) + 4, // Offset64Hi\r
+ FALSE // Writeable\r
+ }, // EFI_SMM_SAVE_STATE_REGISTER_GDTBASE = 4\r
+\r
+ {\r
+ 0, // Width32\r
+ 8, // Width64\r
+ 0, // Offset32\r
+ SMM_CPU_OFFSET (x64._IDTRBase), // Offset64Lo\r
+ SMM_CPU_OFFSET (x64._IDTRBase) + 4, // Offset64Hi\r
+ FALSE // Writeable\r
+ }, // EFI_SMM_SAVE_STATE_REGISTER_IDTBASE = 5\r
+\r
+ {\r
+ 0, // Width32\r
+ 8, // Width64\r
+ 0, // Offset32\r
+ SMM_CPU_OFFSET (x64._LDTRBase), // Offset64Lo\r
+ SMM_CPU_OFFSET (x64._LDTRBase) + 4, // Offset64Hi\r
+ FALSE // Writeable\r
+ }, // EFI_SMM_SAVE_STATE_REGISTER_LDTBASE = 6\r
+\r
+ {\r
+ 0, // Width32\r
+ 0, // Width64\r
+ 0, // Offset32\r
+ SMM_CPU_OFFSET (x64._GDTRLimit), // Offset64Lo\r
+ SMM_CPU_OFFSET (x64._GDTRLimit) + 4, // Offset64Hi\r
+ FALSE // Writeable\r
+ }, // EFI_SMM_SAVE_STATE_REGISTER_GDTLIMIT = 7\r
+\r
+ {\r
+ 0, // Width32\r
+ 0, // Width64\r
+ 0, // Offset32\r
+ SMM_CPU_OFFSET (x64._IDTRLimit), // Offset64Lo\r
+ SMM_CPU_OFFSET (x64._IDTRLimit) + 4, // Offset64Hi\r
+ FALSE // Writeable\r
+ }, // EFI_SMM_SAVE_STATE_REGISTER_IDTLIMIT = 8\r
+\r
+ {\r
+ 0, // Width32\r
+ 0, // Width64\r
+ 0, // Offset32\r
+ SMM_CPU_OFFSET (x64._LDTRLimit), // Offset64Lo\r
+ SMM_CPU_OFFSET (x64._LDTRLimit) + 4, // Offset64Hi\r
+ FALSE // Writeable\r
+ }, // EFI_SMM_SAVE_STATE_REGISTER_LDTLIMIT = 9\r
+\r
+ {\r
+ 0, // Width32\r
+ 0, // Width64\r
+ 0, // Offset32\r
+ 0, // Offset64Lo\r
+ 0 + 4, // Offset64Hi\r
+ FALSE // Writeable\r
+ }, // EFI_SMM_SAVE_STATE_REGISTER_LDTINFO = 10\r
+\r
+ {\r
+ 4, // Width32\r
+ 4, // Width64\r
+ SMM_CPU_OFFSET (x86._ES), // Offset32\r
+ SMM_CPU_OFFSET (x64._ES), // Offset64Lo\r
+ 0, // Offset64Hi\r
+ FALSE // Writeable\r
+ }, // EFI_SMM_SAVE_STATE_REGISTER_ES = 20\r
+\r
+ {\r
+ 4, // Width32\r
+ 4, // Width64\r
+ SMM_CPU_OFFSET (x86._CS), // Offset32\r
+ SMM_CPU_OFFSET (x64._CS), // Offset64Lo\r
+ 0, // Offset64Hi\r
+ FALSE // Writeable\r
+ }, // EFI_SMM_SAVE_STATE_REGISTER_CS = 21\r
+\r
+ {\r
+ 4, // Width32\r
+ 4, // Width64\r
+ SMM_CPU_OFFSET (x86._SS), // Offset32\r
+ SMM_CPU_OFFSET (x64._SS), // Offset64Lo\r
+ 0, // Offset64Hi\r
+ FALSE // Writeable\r
+ }, // EFI_SMM_SAVE_STATE_REGISTER_SS = 22\r
+\r
+ {\r
+ 4, // Width32\r
+ 4, // Width64\r
+ SMM_CPU_OFFSET (x86._DS), // Offset32\r
+ SMM_CPU_OFFSET (x64._DS), // Offset64Lo\r
+ 0, // Offset64Hi\r
+ FALSE // Writeable\r
+ }, // EFI_SMM_SAVE_STATE_REGISTER_DS = 23\r
+\r
+ {\r
+ 4, // Width32\r
+ 4, // Width64\r
+ SMM_CPU_OFFSET (x86._FS), // Offset32\r
+ SMM_CPU_OFFSET (x64._FS), // Offset64Lo\r
+ 0, // Offset64Hi\r
+ FALSE // Writeable\r
+ }, // EFI_SMM_SAVE_STATE_REGISTER_FS = 24\r
+\r
+ {\r
+ 4, // Width32\r
+ 4, // Width64\r
+ SMM_CPU_OFFSET (x86._GS), // Offset32\r
+ SMM_CPU_OFFSET (x64._GS), // Offset64Lo\r
+ 0, // Offset64Hi\r
+ FALSE // Writeable\r
+ }, // EFI_SMM_SAVE_STATE_REGISTER_GS = 25\r
+\r
+ {\r
+ 0, // Width32\r
+ 4, // Width64\r
+ 0, // Offset32\r
+ SMM_CPU_OFFSET (x64._LDTR), // Offset64Lo\r
+ 0, // Offset64Hi\r
+ FALSE // Writeable\r
+ }, // EFI_SMM_SAVE_STATE_REGISTER_LDTR_SEL = 26\r
+\r
+ {\r
+ 4, // Width32\r
+ 4, // Width64\r
+ SMM_CPU_OFFSET (x86._TR), // Offset32\r
+ SMM_CPU_OFFSET (x64._TR), // Offset64Lo\r
+ 0, // Offset64Hi\r
+ FALSE // Writeable\r
+ }, // EFI_SMM_SAVE_STATE_REGISTER_TR_SEL = 27\r
+\r
+ {\r
+ 4, // Width32\r
+ 8, // Width64\r
+ SMM_CPU_OFFSET (x86._DR7), // Offset32\r
+ SMM_CPU_OFFSET (x64._DR7), // Offset64Lo\r
+ SMM_CPU_OFFSET (x64._DR7) + 4, // Offset64Hi\r
+ FALSE // Writeable\r
+ }, // EFI_SMM_SAVE_STATE_REGISTER_DR7 = 28\r
+\r
+ {\r
+ 4, // Width32\r
+ 8, // Width64\r
+ SMM_CPU_OFFSET (x86._DR6), // Offset32\r
+ SMM_CPU_OFFSET (x64._DR6), // Offset64Lo\r
+ SMM_CPU_OFFSET (x64._DR6) + 4, // Offset64Hi\r
+ FALSE // Writeable\r
+ }, // EFI_SMM_SAVE_STATE_REGISTER_DR6 = 29\r
+\r
+ {\r
+ 0, // Width32\r
+ 8, // Width64\r
+ 0, // Offset32\r
+ SMM_CPU_OFFSET (x64._R8), // Offset64Lo\r
+ SMM_CPU_OFFSET (x64._R8) + 4, // Offset64Hi\r
+ TRUE // Writeable\r
+ }, // EFI_SMM_SAVE_STATE_REGISTER_R8 = 30\r
+\r
+ {\r
+ 0, // Width32\r
+ 8, // Width64\r
+ 0, // Offset32\r
+ SMM_CPU_OFFSET (x64._R9), // Offset64Lo\r
+ SMM_CPU_OFFSET (x64._R9) + 4, // Offset64Hi\r
+ TRUE // Writeable\r
+ }, // EFI_SMM_SAVE_STATE_REGISTER_R9 = 31\r
+\r
+ {\r
+ 0, // Width32\r
+ 8, // Width64\r
+ 0, // Offset32\r
+ SMM_CPU_OFFSET (x64._R10), // Offset64Lo\r
+ SMM_CPU_OFFSET (x64._R10) + 4, // Offset64Hi\r
+ TRUE // Writeable\r
+ }, // EFI_SMM_SAVE_STATE_REGISTER_R10 = 32\r
+\r
+ {\r
+ 0, // Width32\r
+ 8, // Width64\r
+ 0, // Offset32\r
+ SMM_CPU_OFFSET (x64._R11), // Offset64Lo\r
+ SMM_CPU_OFFSET (x64._R11) + 4, // Offset64Hi\r
+ TRUE // Writeable\r
+ }, // EFI_SMM_SAVE_STATE_REGISTER_R11 = 33\r
+\r
+ {\r
+ 0, // Width32\r
+ 8, // Width64\r
+ 0, // Offset32\r
+ SMM_CPU_OFFSET (x64._R12), // Offset64Lo\r
+ SMM_CPU_OFFSET (x64._R12) + 4, // Offset64Hi\r
+ TRUE // Writeable\r
+ }, // EFI_SMM_SAVE_STATE_REGISTER_R12 = 34\r
+\r
+ {\r
+ 0, // Width32\r
+ 8, // Width64\r
+ 0, // Offset32\r
+ SMM_CPU_OFFSET (x64._R13), // Offset64Lo\r
+ SMM_CPU_OFFSET (x64._R13) + 4, // Offset64Hi\r
+ TRUE // Writeable\r
+ }, // EFI_SMM_SAVE_STATE_REGISTER_R13 = 35\r
+\r
+ {\r
+ 0, // Width32\r
+ 8, // Width64\r
+ 0, // Offset32\r
+ SMM_CPU_OFFSET (x64._R14), // Offset64Lo\r
+ SMM_CPU_OFFSET (x64._R14) + 4, // Offset64Hi\r
+ TRUE // Writeable\r
+ }, // EFI_SMM_SAVE_STATE_REGISTER_R14 = 36\r
+\r
+ {\r
+ 0, // Width32\r
+ 8, // Width64\r
+ 0, // Offset32\r
+ SMM_CPU_OFFSET (x64._R15), // Offset64Lo\r
+ SMM_CPU_OFFSET (x64._R15) + 4, // Offset64Hi\r
+ TRUE // Writeable\r
+ }, // EFI_SMM_SAVE_STATE_REGISTER_R15 = 37\r
+\r
+ {\r
+ 4, // Width32\r
+ 8, // Width64\r
+ SMM_CPU_OFFSET (x86._EAX), // Offset32\r
+ SMM_CPU_OFFSET (x64._RAX), // Offset64Lo\r
+ SMM_CPU_OFFSET (x64._RAX) + 4, // Offset64Hi\r
+ TRUE // Writeable\r
+ }, // EFI_SMM_SAVE_STATE_REGISTER_RAX = 38\r
+\r
+ {\r
+ 4, // Width32\r
+ 8, // Width64\r
+ SMM_CPU_OFFSET (x86._EBX), // Offset32\r
+ SMM_CPU_OFFSET (x64._RBX), // Offset64Lo\r
+ SMM_CPU_OFFSET (x64._RBX) + 4, // Offset64Hi\r
+ TRUE // Writeable\r
+ }, // EFI_SMM_SAVE_STATE_REGISTER_RBX = 39\r
+\r
+ {\r
+ 4, // Width32\r
+ 8, // Width64\r
+ SMM_CPU_OFFSET (x86._ECX), // Offset32\r
+ SMM_CPU_OFFSET (x64._RCX), // Offset64Lo\r
+ SMM_CPU_OFFSET (x64._RCX) + 4, // Offset64Hi\r
+ TRUE // Writeable\r
+ }, // EFI_SMM_SAVE_STATE_REGISTER_RCX = 40\r
+\r
+ {\r
+ 4, // Width32\r
+ 8, // Width64\r
+ SMM_CPU_OFFSET (x86._EDX), // Offset32\r
+ SMM_CPU_OFFSET (x64._RDX), // Offset64Lo\r
+ SMM_CPU_OFFSET (x64._RDX) + 4, // Offset64Hi\r
+ TRUE // Writeable\r
+ }, // EFI_SMM_SAVE_STATE_REGISTER_RDX = 41\r
+\r
+ {\r
+ 4, // Width32\r
+ 8, // Width64\r
+ SMM_CPU_OFFSET (x86._ESP), // Offset32\r
+ SMM_CPU_OFFSET (x64._RSP), // Offset64Lo\r
+ SMM_CPU_OFFSET (x64._RSP) + 4, // Offset64Hi\r
+ TRUE // Writeable\r
+ }, // EFI_SMM_SAVE_STATE_REGISTER_RSP = 42\r
+\r
+ {\r
+ 4, // Width32\r
+ 8, // Width64\r
+ SMM_CPU_OFFSET (x86._EBP), // Offset32\r
+ SMM_CPU_OFFSET (x64._RBP), // Offset64Lo\r
+ SMM_CPU_OFFSET (x64._RBP) + 4, // Offset64Hi\r
+ TRUE // Writeable\r
+ }, // EFI_SMM_SAVE_STATE_REGISTER_RBP = 43\r
+\r
+ {\r
+ 4, // Width32\r
+ 8, // Width64\r
+ SMM_CPU_OFFSET (x86._ESI), // Offset32\r
+ SMM_CPU_OFFSET (x64._RSI), // Offset64Lo\r
+ SMM_CPU_OFFSET (x64._RSI) + 4, // Offset64Hi\r
+ TRUE // Writeable\r
+ }, // EFI_SMM_SAVE_STATE_REGISTER_RSI = 44\r
+\r
+ {\r
+ 4, // Width32\r
+ 8, // Width64\r
+ SMM_CPU_OFFSET (x86._EDI), // Offset32\r
+ SMM_CPU_OFFSET (x64._RDI), // Offset64Lo\r
+ SMM_CPU_OFFSET (x64._RDI) + 4, // Offset64Hi\r
+ TRUE // Writeable\r
+ }, // EFI_SMM_SAVE_STATE_REGISTER_RDI = 45\r
+\r
+ {\r
+ 4, // Width32\r
+ 8, // Width64\r
+ SMM_CPU_OFFSET (x86._EIP), // Offset32\r
+ SMM_CPU_OFFSET (x64._RIP), // Offset64Lo\r
+ SMM_CPU_OFFSET (x64._RIP) + 4, // Offset64Hi\r
+ TRUE // Writeable\r
+ }, // EFI_SMM_SAVE_STATE_REGISTER_RIP = 46\r
+\r
+ {\r
+ 4, // Width32\r
+ 8, // Width64\r
+ SMM_CPU_OFFSET (x86._EFLAGS), // Offset32\r
+ SMM_CPU_OFFSET (x64._RFLAGS), // Offset64Lo\r
+ SMM_CPU_OFFSET (x64._RFLAGS) + 4, // Offset64Hi\r
+ TRUE // Writeable\r
+ }, // EFI_SMM_SAVE_STATE_REGISTER_RFLAGS = 51\r
+\r
+ {\r
+ 4, // Width32\r
+ 8, // Width64\r
+ SMM_CPU_OFFSET (x86._CR0), // Offset32\r
+ SMM_CPU_OFFSET (x64._CR0), // Offset64Lo\r
+ SMM_CPU_OFFSET (x64._CR0) + 4, // Offset64Hi\r
+ FALSE // Writeable\r
+ }, // EFI_SMM_SAVE_STATE_REGISTER_CR0 = 52\r
+\r
+ {\r
+ 4, // Width32\r
+ 8, // Width64\r
+ SMM_CPU_OFFSET (x86._CR3), // Offset32\r
+ SMM_CPU_OFFSET (x64._CR3), // Offset64Lo\r
+ SMM_CPU_OFFSET (x64._CR3) + 4, // Offset64Hi\r
+ FALSE // Writeable\r
+ }, // EFI_SMM_SAVE_STATE_REGISTER_CR3 = 53\r
+\r
+ {\r
+ 0, // Width32\r
+ 4, // Width64\r
+ 0, // Offset32\r
+ SMM_CPU_OFFSET (x64._CR4), // Offset64Lo\r
+ SMM_CPU_OFFSET (x64._CR4) + 4, // Offset64Hi\r
+ FALSE // Writeable\r
+ }, // EFI_SMM_SAVE_STATE_REGISTER_CR4 = 54\r
};\r
\r
//\r
UINTN Index;\r
UINTN Offset;\r
\r
- for (Index = 0, Offset = SMM_SAVE_STATE_REGISTER_FIRST_INDEX; mSmmCpuRegisterRanges[Index].Length != 0; Index++) {\r
- if (Register >= mSmmCpuRegisterRanges[Index].Start && Register <= mSmmCpuRegisterRanges[Index].End) {\r
+ for (Index = 0, Offset = SMM_SAVE_STATE_REGISTER_FIRST_INDEX;\r
+ mSmmCpuRegisterRanges[Index].Length != 0;\r
+ Index++) {\r
+ if (Register >= mSmmCpuRegisterRanges[Index].Start &&\r
+ Register <= mSmmCpuRegisterRanges[Index].End) {\r
return Register - mSmmCpuRegisterRanges[Index].Start + Offset;\r
}\r
Offset += mSmmCpuRegisterRanges[Index].Length;\r
/**\r
Read a CPU Save State register on the target processor.\r
\r
- This function abstracts the differences that whether the CPU Save State register is in the \r
- IA32 CPU Save State Map or X64 CPU Save State Map.\r
+ This function abstracts the differences that whether the CPU Save State\r
+ register is in the IA32 CPU Save State Map or X64 CPU Save State Map.\r
\r
- This function supports reading a CPU Save State register in SMBase relocation handler.\r
+ This function supports reading a CPU Save State register in SMBase relocation\r
+ handler.\r
\r
- @param[in] CpuIndex Specifies the zero-based index of the CPU save state.\r
+ @param[in] CpuIndex Specifies the zero-based index of the CPU save\r
+ state.\r
@param[in] RegisterIndex Index into mSmmCpuWidthOffset[] look up table.\r
- @param[in] Width The number of bytes to read from the CPU save state.\r
- @param[out] Buffer Upon return, this holds the CPU register value read from the save state.\r
+ @param[in] Width The number of bytes to read from the CPU save\r
+ state.\r
+ @param[out] Buffer Upon return, this holds the CPU register value\r
+ read from the save state.\r
\r
@retval EFI_SUCCESS The register was read from Save State.\r
- @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor.\r
+ @retval EFI_NOT_FOUND The register is not defined for the Save State\r
+ of Processor.\r
@retval EFI_INVALID_PARAMTER This or Buffer is NULL.\r
\r
**/\r
\r
if ((CpuSaveState->x86.SMMRevId & 0xFFFF) == 0) {\r
//\r
- // If 32-bit mode width is zero, then the specified register can not be accessed\r
+ // If 32-bit mode width is zero, then the specified register can not be\r
+ // accessed\r
//\r
if (mSmmCpuWidthOffset[RegisterIndex].Width32 == 0) {\r
return EFI_NOT_FOUND;\r
}\r
\r
//\r
- // If Width is bigger than the 32-bit mode width, then the specified register can not be accessed\r
+ // If Width is bigger than the 32-bit mode width, then the specified\r
+ // register can not be accessed\r
//\r
if (Width > mSmmCpuWidthOffset[RegisterIndex].Width32) {\r
return EFI_INVALID_PARAMETER;\r
// Write return buffer\r
//\r
ASSERT(CpuSaveState != NULL);\r
- CopyMem(Buffer, (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset32, Width);\r
+ CopyMem (\r
+ Buffer,\r
+ (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset32,\r
+ Width\r
+ );\r
} else {\r
//\r
- // If 64-bit mode width is zero, then the specified register can not be accessed\r
+ // If 64-bit mode width is zero, then the specified register can not be\r
+ // accessed\r
//\r
if (mSmmCpuWidthOffset[RegisterIndex].Width64 == 0) {\r
return EFI_NOT_FOUND;\r
}\r
\r
//\r
- // If Width is bigger than the 64-bit mode width, then the specified register can not be accessed\r
+ // If Width is bigger than the 64-bit mode width, then the specified\r
+ // register can not be accessed\r
//\r
if (Width > mSmmCpuWidthOffset[RegisterIndex].Width64) {\r
return EFI_INVALID_PARAMETER;\r
//\r
// Write lower 32-bits of return buffer\r
//\r
- CopyMem(Buffer, (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Lo, MIN(4, Width));\r
+ CopyMem (\r
+ Buffer,\r
+ (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Lo,\r
+ MIN (4, Width)\r
+ );\r
if (Width >= 4) {\r
//\r
// Write upper 32-bits of return buffer\r
//\r
- CopyMem((UINT8 *)Buffer + 4, (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Hi, Width - 4);\r
+ CopyMem (\r
+ (UINT8 *)Buffer + 4,\r
+ (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Hi,\r
+ Width - 4\r
+ );\r
}\r
}\r
return EFI_SUCCESS;\r
\r
@retval EFI_SUCCESS The register was read from Save State.\r
@retval EFI_INVALID_PARAMTER Buffer is NULL.\r
- @retval EFI_UNSUPPORTED This function does not support reading Register.\r
-\r
+ @retval EFI_UNSUPPORTED This function does not support reading\r
+ Register.\r
**/\r
EFI_STATUS\r
EFIAPI\r
//\r
RegisterIndex = GetRegisterIndex (Register);\r
if (RegisterIndex == 0) {\r
- return Register < EFI_SMM_SAVE_STATE_REGISTER_IO ? EFI_NOT_FOUND : EFI_UNSUPPORTED;\r
+ return (Register < EFI_SMM_SAVE_STATE_REGISTER_IO ?\r
+ EFI_NOT_FOUND :\r
+ EFI_UNSUPPORTED);\r
}\r
\r
return ReadSaveStateRegisterByIndex (CpuIndex, RegisterIndex, Width, Buffer);\r
\r
@retval EFI_SUCCESS The register was written to Save State.\r
@retval EFI_INVALID_PARAMTER Buffer is NULL.\r
- @retval EFI_UNSUPPORTED This function does not support writing Register.\r
+ @retval EFI_UNSUPPORTED This function does not support writing\r
+ Register.\r
**/\r
EFI_STATUS\r
EFIAPI\r
//\r
RegisterIndex = GetRegisterIndex (Register);\r
if (RegisterIndex == 0) {\r
- return Register < EFI_SMM_SAVE_STATE_REGISTER_IO ? EFI_NOT_FOUND : EFI_UNSUPPORTED;\r
+ return (Register < EFI_SMM_SAVE_STATE_REGISTER_IO ?\r
+ EFI_NOT_FOUND :\r
+ EFI_UNSUPPORTED);\r
}\r
\r
CpuSaveState = (QEMU_SMRAM_SAVE_STATE_MAP *)gSmst->CpuSaveState[CpuIndex];\r
\r
//\r
// Do not write non-writable SaveState, because it will cause exception.\r
- // \r
+ //\r
if (!mSmmCpuWidthOffset[RegisterIndex].Writeable) {\r
return EFI_UNSUPPORTED;\r
}\r
//\r
if ((CpuSaveState->x86.SMMRevId & 0xFFFF) == 0) {\r
//\r
- // If 32-bit mode width is zero, then the specified register can not be accessed\r
+ // If 32-bit mode width is zero, then the specified register can not be\r
+ // accessed\r
//\r
if (mSmmCpuWidthOffset[RegisterIndex].Width32 == 0) {\r
return EFI_NOT_FOUND;\r
}\r
\r
//\r
- // If Width is bigger than the 32-bit mode width, then the specified register can not be accessed\r
+ // If Width is bigger than the 32-bit mode width, then the specified\r
+ // register can not be accessed\r
//\r
if (Width > mSmmCpuWidthOffset[RegisterIndex].Width32) {\r
return EFI_INVALID_PARAMETER;\r
// Write SMM State register\r
//\r
ASSERT (CpuSaveState != NULL);\r
- CopyMem((UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset32, Buffer, Width);\r
+ CopyMem (\r
+ (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset32,\r
+ Buffer,\r
+ Width\r
+ );\r
} else {\r
//\r
- // If 64-bit mode width is zero, then the specified register can not be accessed\r
+ // If 64-bit mode width is zero, then the specified register can not be\r
+ // accessed\r
//\r
if (mSmmCpuWidthOffset[RegisterIndex].Width64 == 0) {\r
return EFI_NOT_FOUND;\r
}\r
\r
//\r
- // If Width is bigger than the 64-bit mode width, then the specified register can not be accessed\r
+ // If Width is bigger than the 64-bit mode width, then the specified\r
+ // register can not be accessed\r
//\r
if (Width > mSmmCpuWidthOffset[RegisterIndex].Width64) {\r
return EFI_INVALID_PARAMETER;\r
//\r
// Write lower 32-bits of SMM State register\r
//\r
- CopyMem((UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Lo, Buffer, MIN (4, Width));\r
+ CopyMem (\r
+ (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Lo,\r
+ Buffer,\r
+ MIN (4, Width)\r
+ );\r
if (Width >= 4) {\r
//\r
// Write upper 32-bits of SMM State register\r
//\r
- CopyMem((UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Hi, (UINT8 *)Buffer + 4, Width - 4);\r
+ CopyMem (\r
+ (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Hi,\r
+ (UINT8 *)Buffer + 4,\r
+ Width - 4\r
+ );\r
}\r
}\r
return EFI_SUCCESS;\r
}\r
\r
/**\r
- This API provides a method for a CPU to allocate a specific region for storing page tables.\r
+ This API provides a method for a CPU to allocate a specific region for\r
+ storing page tables.\r
\r
This API can be called more once to allocate memory for page tables.\r
\r
- Allocates the number of 4KB pages of type EfiRuntimeServicesData and returns a pointer to the\r
- allocated buffer. The buffer returned is aligned on a 4KB boundary. If Pages is 0, then NULL\r
- is returned. If there is not enough memory remaining to satisfy the request, then NULL is\r
- returned.\r
+ Allocates the number of 4KB pages of type EfiRuntimeServicesData and returns\r
+ a pointer to the allocated buffer. The buffer returned is aligned on a 4KB\r
+ boundary. If Pages is 0, then NULL is returned. If there is not enough\r
+ memory remaining to satisfy the request, then NULL is returned.\r
\r
- This function can also return NULL if there is no preference on where the page tables are allocated in SMRAM.\r
+ This function can also return NULL if there is no preference on where the\r
+ page tables are allocated in SMRAM.\r
\r
@param Pages The number of 4 KB pages to allocate.\r
\r
@return A pointer to the allocated buffer for page tables.\r
@retval NULL Fail to allocate a specific region for storing page tables,\r
- Or there is no preference on where the page tables are allocated in SMRAM.\r
+ Or there is no preference on where the page tables are\r
+ allocated in SMRAM.\r
\r
**/\r
VOID *\r
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