## @file\r
# EFI/Framework Open Virtual Machine Firmware (OVMF) platform\r
#\r
-# Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.<BR>\r
+# Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>\r
#\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+# SPDX-License-Identifier: BSD-2-Clause-Patent\r
#\r
##\r
\r
\r
[Includes]\r
Include\r
+ Csm/Include\r
\r
[LibraryClasses]\r
## @libraryclass Loads and boots a Linux kernel image\r
#\r
NvVarsFileLib|Include/Library/NvVarsFileLib.h\r
\r
+ ## @libraryclass Provides services to work with PCI capabilities in PCI\r
+ # config space.\r
+ PciCapLib|Include/Library/PciCapLib.h\r
+\r
+ ## @libraryclass Layered on top of PciCapLib, allows clients to plug an\r
+ # EFI_PCI_IO_PROTOCOL backend into PciCapLib, for config\r
+ # space access.\r
+ PciCapPciIoLib|Include/Library/PciCapPciIoLib.h\r
+\r
+ ## @libraryclass Layered on top of PciCapLib, allows clients to plug a\r
+ # PciSegmentLib backend into PciCapLib, for config space\r
+ # access.\r
+ PciCapPciSegmentLib|Include/Library/PciCapPciSegmentLib.h\r
+\r
+ ## @libraryclass Register a status code handler for printing the Boot\r
+ # Manager's LoadImage() and StartImage() preparations, and\r
+ # return codes, to the UEFI console.\r
+ PlatformBmPrintScLib|Include/Library/PlatformBmPrintScLib.h\r
+\r
## @libraryclass Access QEMU's firmware configuration interface\r
#\r
QemuFwCfgLib|Include/Library/QemuFwCfgLib.h\r
\r
+ ## @libraryclass S3 support for QEMU fw_cfg\r
+ #\r
+ QemuFwCfgS3Lib|Include/Library/QemuFwCfgS3Lib.h\r
+\r
+ ## @libraryclass Rewrite the BootOrder NvVar based on QEMU's "bootorder"\r
+ # fw_cfg file.\r
+ #\r
+ QemuBootOrderLib|Include/Library/QemuBootOrderLib.h\r
+\r
## @libraryclass Serialize (and deserialize) variables\r
#\r
SerializeVariablesLib|Include/Library/SerializeVariablesLib.h\r
\r
+ ## @libraryclass Invoke Xen hypercalls\r
+ #\r
+ XenHypercallLib|Include/Library/XenHypercallLib.h\r
+\r
+ ## @libraryclass Manage XenBus device path and I/O handles\r
+ #\r
+ XenIoMmioLib|Include/Library/XenIoMmioLib.h\r
+\r
[Guids]\r
- gUefiOvmfPkgTokenSpaceGuid = {0x93bb96af, 0xb9f2, 0x4eb8, {0x94, 0x62, 0xe0, 0xba, 0x74, 0x56, 0x42, 0x36}}\r
- gEfiXenInfoGuid = {0xd3b46f3b, 0xd441, 0x1244, {0x9a, 0x12, 0x0, 0x12, 0x27, 0x3f, 0xc1, 0x4d}}\r
+ gUefiOvmfPkgTokenSpaceGuid = {0x93bb96af, 0xb9f2, 0x4eb8, {0x94, 0x62, 0xe0, 0xba, 0x74, 0x56, 0x42, 0x36}}\r
+ gEfiXenInfoGuid = {0xd3b46f3b, 0xd441, 0x1244, {0x9a, 0x12, 0x0, 0x12, 0x27, 0x3f, 0xc1, 0x4d}}\r
+ gOvmfPkKek1AppPrefixGuid = {0x4e32566d, 0x8e9e, 0x4f52, {0x81, 0xd3, 0x5b, 0xb9, 0x71, 0x5f, 0x97, 0x27}}\r
+ gOvmfPlatformConfigGuid = {0x7235c51c, 0x0c80, 0x4cab, {0x87, 0xac, 0x3b, 0x08, 0x4a, 0x63, 0x04, 0xb1}}\r
+ gVirtioMmioTransportGuid = {0x837dca9e, 0xe874, 0x4d82, {0xb2, 0x9a, 0x23, 0xfe, 0x0e, 0x23, 0xd1, 0xe2}}\r
+ gQemuRamfbGuid = {0x557423a1, 0x63ab, 0x406c, {0xbe, 0x7e, 0x91, 0xcd, 0xbc, 0x08, 0xc4, 0x57}}\r
+ gXenBusRootDeviceGuid = {0xa732241f, 0x383d, 0x4d9c, {0x8a, 0xe1, 0x8e, 0x09, 0x83, 0x75, 0x89, 0xd7}}\r
+ gRootBridgesConnectedEventGroupGuid = {0x24a2d66f, 0xeedd, 0x4086, {0x90, 0x42, 0xf2, 0x6e, 0x47, 0x97, 0xee, 0x69}}\r
+ gMicrosoftVendorGuid = {0x77fa9abd, 0x0359, 0x4d32, {0xbd, 0x60, 0x28, 0xf4, 0xe7, 0x8f, 0x78, 0x4b}}\r
+ gEfiLegacyBiosGuid = {0x2E3044AC, 0x879F, 0x490F, {0x97, 0x60, 0xBB, 0xDF, 0xAF, 0x69, 0x5F, 0x50}}\r
+ gEfiLegacyDevOrderVariableGuid = {0xa56074db, 0x65fe, 0x45f7, {0xbd, 0x21, 0x2d, 0x2b, 0xdd, 0x8e, 0x96, 0x52}}\r
\r
[Protocols]\r
- gBlockMmioProtocolGuid = {0x6b558ce3, 0x69e5, 0x4c67, {0xa6, 0x34, 0xf7, 0xfe, 0x72, 0xad, 0xbe, 0x84}}\r
+ gVirtioDeviceProtocolGuid = {0xfa920010, 0x6785, 0x4941, {0xb6, 0xec, 0x49, 0x8c, 0x57, 0x9f, 0x16, 0x0a}}\r
+ gXenBusProtocolGuid = {0x3d3ca290, 0xb9a5, 0x11e3, {0xb7, 0x5d, 0xb8, 0xac, 0x6f, 0x7d, 0x65, 0xe6}}\r
+ gXenIoProtocolGuid = {0x6efac84f, 0x0ab0, 0x4747, {0x81, 0xbe, 0x85, 0x55, 0x62, 0x59, 0x04, 0x49}}\r
+ gIoMmuAbsentProtocolGuid = {0xf8775d50, 0x8abd, 0x4adf, {0x92, 0xac, 0x85, 0x3e, 0x51, 0xf6, 0xc8, 0xdc}}\r
+ gEfiLegacy8259ProtocolGuid = {0x38321dba, 0x4fe0, 0x4e17, {0x8a, 0xec, 0x41, 0x30, 0x55, 0xea, 0xed, 0xc1}}\r
+ gEfiFirmwareVolumeProtocolGuid = {0x389F751F, 0x1838, 0x4388, {0x83, 0x90, 0xcd, 0x81, 0x54, 0xbd, 0x27, 0xf8}}\r
+ gEfiIsaAcpiProtocolGuid = {0x64a892dc, 0x5561, 0x4536, {0x92, 0xc7, 0x79, 0x9b, 0xfc, 0x18, 0x33, 0x55}}\r
+ gEfiIsaIoProtocolGuid = {0x7ee2bd44, 0x3da0, 0x11d4, {0x9a, 0x38, 0x0, 0x90, 0x27, 0x3f, 0xc1, 0x4d}}\r
+ gEfiLegacyBiosProtocolGuid = {0xdb9a1e3d, 0x45cb, 0x4abb, {0x85, 0x3b, 0xe5, 0x38, 0x7f, 0xdb, 0x2e, 0x2d}}\r
+ gEfiLegacyBiosPlatformProtocolGuid = {0x783658a3, 0x4172, 0x4421, {0xa2, 0x99, 0xe0, 0x09, 0x07, 0x9c, 0x0c, 0xb4}}\r
+ gEfiLegacyInterruptProtocolGuid = {0x31ce593d, 0x108a, 0x485d, {0xad, 0xb2, 0x78, 0xf2, 0x1f, 0x29, 0x66, 0xbe}}\r
+ gEfiVgaMiniPortProtocolGuid = {0xc7735a2f, 0x88f5, 0x4882, {0xae, 0x63, 0xfa, 0xac, 0x8c, 0x8b, 0x86, 0xb3}}\r
\r
[PcdsFixedAtBuild]\r
- gUefiOvmfPkgTokenSpaceGuid.PcdOvmfMemFvBase|0x0|UINT32|0\r
- gUefiOvmfPkgTokenSpaceGuid.PcdOvmfMemFvSize|0x0|UINT32|1\r
+ gUefiOvmfPkgTokenSpaceGuid.PcdOvmfPeiMemFvBase|0x0|UINT32|0\r
+ gUefiOvmfPkgTokenSpaceGuid.PcdOvmfPeiMemFvSize|0x0|UINT32|1\r
+ gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDxeMemFvBase|0x0|UINT32|0x15\r
+ gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDxeMemFvSize|0x0|UINT32|0x16\r
\r
## This flag is used to control the destination port for PlatformDebugLibIoPort\r
gUefiOvmfPkgTokenSpaceGuid.PcdDebugIoPort|0x402|UINT16|4\r
\r
- ## This flag determines the Power Management Base Address of choice, written\r
- # to PIIX4 function 3 offset 0x40-0x43 bits [15:6].\r
- gUefiOvmfPkgTokenSpaceGuid.PcdAcpiPmBaseAddress|0xB000|UINT16|5\r
-\r
## When VirtioScsiDxe is instantiated for a HBA, the numbers of targets and\r
# LUNs are retrieved from the host during virtio-scsi setup.\r
# MdeModulePkg/Bus/Scsi/ScsiBusDxe then scans all MaxTarget * MaxLun\r
gUefiOvmfPkgTokenSpaceGuid.PcdVirtioScsiMaxTargetLimit|31|UINT16|6\r
gUefiOvmfPkgTokenSpaceGuid.PcdVirtioScsiMaxLunLimit|7|UINT32|7\r
\r
-[PcdsFixedAtBuild]\r
gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageEventLogBase|0x0|UINT32|0x8\r
gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageEventLogSize|0x0|UINT32|0x9\r
gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFirmwareFdSize|0x0|UINT32|0xa\r
gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageFtwSpareBase|0x0|UINT32|0xd\r
gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageFtwWorkingBase|0x0|UINT32|0xe\r
gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFdBaseAddress|0x0|UINT32|0xf\r
+ gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPageTablesBase|0x0|UINT32|0x11\r
+ gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPageTablesSize|0x0|UINT32|0x12\r
+ gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamBase|0x0|UINT32|0x13\r
+ gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamSize|0x0|UINT32|0x14\r
+ gUefiOvmfPkgTokenSpaceGuid.PcdOvmfLockBoxStorageBase|0x0|UINT32|0x18\r
+ gUefiOvmfPkgTokenSpaceGuid.PcdOvmfLockBoxStorageSize|0x0|UINT32|0x19\r
+ gUefiOvmfPkgTokenSpaceGuid.PcdGuidedExtractHandlerTableSize|0x0|UINT32|0x1a\r
+ gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDecompressionScratchEnd|0x0|UINT32|0x1f\r
+\r
+ ## Pcd8259LegacyModeMask defines the default mask value for platform. This\r
+ # value is determined.\r
+ # 1) If platform only support pure UEFI, value should be set to 0xFFFF or\r
+ # 0xFFFE; Because only clock interrupt is allowed in legacy mode in pure\r
+ # UEFI platform.\r
+ # 2) If platform install CSM and use thunk module:\r
+ # a) If thunk call provided by CSM binary requires some legacy interrupt\r
+ # support, the corresponding bit should be opened as 0.\r
+ # For example, if keyboard interfaces provided CSM binary use legacy\r
+ # keyboard interrupt in 8259 bit 1, then the value should be set to\r
+ # 0xFFFC.\r
+ # b) If all thunk call provied by CSM binary do not require legacy\r
+ # interrupt support, value should be set to 0xFFFF or 0xFFFE.\r
+ #\r
+ # The default value of legacy mode mask could be changed by\r
+ # EFI_LEGACY_8259_PROTOCOL->SetMask(). But it is rarely need change it\r
+ # except some special cases such as when initializing the CSM binary, it\r
+ # should be set to 0xFFFF to mask all legacy interrupt. Please restore the\r
+ # original legacy mask value if changing is made for these special case.\r
+ gUefiOvmfPkgTokenSpaceGuid.Pcd8259LegacyModeMask|0xFFFF|UINT16|0x3\r
+\r
+ ## Pcd8259LegacyModeEdgeLevel defines the default edge level for legacy\r
+ # mode's interrrupt controller.\r
+ # For the corresponding bits, 0 = Edge triggered and 1 = Level triggered.\r
+ gUefiOvmfPkgTokenSpaceGuid.Pcd8259LegacyModeEdgeLevel|0x0000|UINT16|0x5\r
\r
[PcdsDynamic, PcdsDynamicEx]\r
gUefiOvmfPkgTokenSpaceGuid.PcdEmuVariableEvent|0|UINT64|2\r
+ gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashVariablesEnable|FALSE|BOOLEAN|0x10\r
+ gUefiOvmfPkgTokenSpaceGuid.PcdOvmfHostBridgePciDevId|0|UINT16|0x1b\r
+ gUefiOvmfPkgTokenSpaceGuid.PcdQemuSmbiosValidated|FALSE|BOOLEAN|0x21\r
+\r
+ ## The IO port aperture shared by all PCI root bridges.\r
+ #\r
+ gUefiOvmfPkgTokenSpaceGuid.PcdPciIoBase|0x0|UINT64|0x22\r
+ gUefiOvmfPkgTokenSpaceGuid.PcdPciIoSize|0x0|UINT64|0x23\r
+\r
+ ## The 32-bit MMIO aperture shared by all PCI root bridges.\r
+ #\r
+ gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio32Base|0x0|UINT64|0x24\r
+ gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio32Size|0x0|UINT64|0x25\r
+\r
+ ## The 64-bit MMIO aperture shared by all PCI root bridges.\r
+ #\r
+ gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio64Base|0x0|UINT64|0x26\r
+ gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio64Size|0x0|UINT64|0x27\r
+\r
+ ## The following setting controls how many megabytes we configure as TSEG on\r
+ # Q35, for SMRAM purposes. Permitted defaults are: 1, 2, 8. Other defaults\r
+ # cause undefined behavior. During boot, the PCD is updated by PlatformPei\r
+ # to reflect the extended TSEG size, if one is advertized by QEMU.\r
+ #\r
+ # This PCD is only accessed if PcdSmmSmramRequire is TRUE (see below).\r
+ gUefiOvmfPkgTokenSpaceGuid.PcdQ35TsegMbytes|8|UINT16|0x20\r
\r
[PcdsFeatureFlag]\r
- gUefiOvmfPkgTokenSpaceGuid.PcdSecureBootEnable|FALSE|BOOLEAN|3\r
+ gUefiOvmfPkgTokenSpaceGuid.PcdQemuBootOrderPciTranslation|TRUE|BOOLEAN|0x1c\r
+ gUefiOvmfPkgTokenSpaceGuid.PcdQemuBootOrderMmioTranslation|FALSE|BOOLEAN|0x1d\r
+\r
+ ## This feature flag enables SMM/SMRAM support. Note that it also requires\r
+ # such support from the underlying QEMU instance; if that support is not\r
+ # present, the firmware will reject continuing after a certain point.\r
+ #\r
+ # The flag also acts as a general "security switch"; when TRUE, many\r
+ # components will change behavior, with the goal of preventing a malicious\r
+ # runtime OS from tampering with firmware structures (special memory ranges\r
+ # used by OVMF, the varstore pflash chip, LockBox etc).\r
+ gUefiOvmfPkgTokenSpaceGuid.PcdSmmSmramRequire|FALSE|BOOLEAN|0x1e\r
projects / mirror_edk2.git / blobdiff