/**@file\r
Platform PEI driver\r
\r
- Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>\r
Copyright (c) 2011, Andrei Warkentin <andreiw@motorola.com>\r
\r
This program and the accompanying materials\r
#include <Library/PciLib.h>\r
#include <Library/PeimEntryPoint.h>\r
#include <Library/PeiServicesLib.h>\r
+#include <Library/QemuFwCfgLib.h>\r
#include <Library/ResourcePublicationLib.h>\r
#include <Guid/MemoryTypeInformation.h>\r
#include <Ppi/MasterBootMode.h>\r
#include <IndustryStandard/Pci22.h>\r
-#include <Guid/XenInfo.h>\r
-#include <IndustryStandard/E820.h>\r
-#include <Library/ResourcePublicationLib.h>\r
-#include <Library/MtrrLib.h>\r
\r
#include "Platform.h"\r
#include "Cmos.h"\r
};\r
\r
\r
+EFI_BOOT_MODE mBootMode = BOOT_WITH_FULL_CONFIGURATION;\r
+\r
+BOOLEAN mS3Supported = FALSE;\r
+\r
+\r
VOID\r
AddIoMemoryBaseSizeHob (\r
EFI_PHYSICAL_ADDRESS MemoryBase,\r
}\r
\r
VOID\r
-XenMemMapInitialization (\r
+MemMapInitialization (\r
VOID\r
)\r
{\r
- EFI_E820_ENTRY64 *E820Map;\r
- UINT32 E820EntriesCount;\r
- EFI_STATUS Status;\r
-\r
- DEBUG ((EFI_D_INFO, "Using memory map provided by Xen\n"));\r
-\r
//\r
// Create Memory Type Information HOB\r
//\r
//\r
AddIoMemoryRangeHob (0x0A0000, BASE_1MB);\r
\r
- //\r
- // Parse RAM in E820 map\r
- //\r
- Status = XenGetE820Map(&E820Map, &E820EntriesCount);\r
-\r
- ASSERT_EFI_ERROR (Status);\r
-\r
- if (E820EntriesCount > 0) {\r
- EFI_E820_ENTRY64 *Entry;\r
- UINT32 Loop;\r
+ if (!mXen) {\r
+ UINT32 TopOfLowRam;\r
+ TopOfLowRam = GetSystemMemorySizeBelow4gb ();\r
\r
- for (Loop = 0; Loop < E820EntriesCount; Loop++) {\r
- Entry = E820Map + Loop;\r
-\r
- //\r
- // Only care about RAM\r
- //\r
- if (Entry->Type != EfiAcpiAddressRangeMemory) {\r
- continue;\r
- }\r
-\r
- if (Entry->BaseAddr >= BASE_4GB) {\r
- AddUntestedMemoryBaseSizeHob (Entry->BaseAddr, Entry->Length);\r
- } else {\r
- AddMemoryBaseSizeHob (Entry->BaseAddr, Entry->Length);\r
- }\r
-\r
- MtrrSetMemoryAttribute (Entry->BaseAddr, Entry->Length, CacheWriteBack);\r
- }\r
+ //\r
+ // address purpose size\r
+ // ------------ -------- -------------------------\r
+ // max(top, 2g) PCI MMIO 0xFC000000 - max(top, 2g)\r
+ // 0xFC000000 gap 44 MB\r
+ // 0xFEC00000 IO-APIC 4 KB\r
+ // 0xFEC01000 gap 1020 KB\r
+ // 0xFED00000 HPET 1 KB\r
+ // 0xFED00400 gap 1023 KB\r
+ // 0xFEE00000 LAPIC 1 MB\r
+ //\r
+ AddIoMemoryRangeHob (TopOfLowRam < BASE_2GB ?\r
+ BASE_2GB : TopOfLowRam, 0xFC000000);\r
+ AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB);\r
+ AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB);\r
+ AddIoMemoryBaseSizeHob (PcdGet32(PcdCpuLocalApicBaseAddress), SIZE_1MB);\r
}\r
}\r
\r
\r
-VOID\r
-MemMapInitialization (\r
- EFI_PHYSICAL_ADDRESS TopOfMemory\r
- )\r
-{\r
- //\r
- // Create Memory Type Information HOB\r
- //\r
- BuildGuidDataHob (\r
- &gEfiMemoryTypeInformationGuid,\r
- mDefaultMemoryTypeInformation,\r
- sizeof(mDefaultMemoryTypeInformation)\r
- );\r
-\r
- //\r
- // Add PCI IO Port space available for PCI resource allocations.\r
- //\r
- BuildResourceDescriptorHob (\r
- EFI_RESOURCE_IO,\r
- EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
- EFI_RESOURCE_ATTRIBUTE_INITIALIZED,\r
- 0xC000,\r
- 0x4000\r
- );\r
-\r
- //\r
- // Video memory + Legacy BIOS region\r
- //\r
- AddIoMemoryRangeHob (0x0A0000, BASE_1MB);\r
-\r
- //\r
- // address purpose size\r
- // ------------ -------- -------------------------\r
- // max(top, 2g) PCI MMIO 0xFC000000 - max(top, 2g)\r
- // 0xFC000000 gap 44 MB\r
- // 0xFEC00000 IO-APIC 4 KB\r
- // 0xFEC01000 gap 1020 KB\r
- // 0xFED00000 HPET 1 KB\r
- // 0xFED00400 gap 1023 KB\r
- // 0xFEE00000 LAPIC 1 MB\r
- //\r
- AddIoMemoryRangeHob (TopOfMemory < BASE_2GB ? BASE_2GB : TopOfMemory, 0xFC000000);\r
- AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB);\r
- AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB);\r
- AddIoMemoryBaseSizeHob (PcdGet32(PcdCpuLocalApicBaseAddress), SIZE_1MB);\r
-}\r
-\r
-\r
VOID\r
MiscInitialization (\r
VOID\r
\r
VOID\r
BootModeInitialization (\r
+ VOID\r
)\r
{\r
- EFI_STATUS Status;\r
+ EFI_STATUS Status;\r
+\r
+ if (CmosRead8 (0xF) == 0xFE) {\r
+ mBootMode = BOOT_ON_S3_RESUME;\r
+ }\r
\r
- Status = PeiServicesSetBootMode (BOOT_WITH_FULL_CONFIGURATION);\r
+ Status = PeiServicesSetBootMode (mBootMode);\r
ASSERT_EFI_ERROR (Status);\r
\r
Status = PeiServicesInstallPpi (mPpiBootMode);\r
IN CONST EFI_PEI_SERVICES **PeiServices\r
)\r
{\r
- EFI_PHYSICAL_ADDRESS TopOfMemory;\r
- UINT32 XenLeaf;\r
-\r
- TopOfMemory = 0;\r
-\r
DEBUG ((EFI_D_ERROR, "Platform PEIM Loaded\n"));\r
\r
DebugDumpCmos ();\r
\r
- XenLeaf = XenDetect ();\r
+ XenDetect ();\r
+\r
+ if (QemuFwCfgS3Enabled ()) {\r
+ DEBUG ((EFI_D_INFO, "S3 support was detected on QEMU\n"));\r
+ mS3Supported = TRUE;\r
+ }\r
+\r
+ BootModeInitialization ();\r
\r
PublishPeiMemory ();\r
\r
- if (XenLeaf != 0) {\r
- PcdSetBool (PcdPciDisableBusEnumeration, TRUE);\r
- } else {\r
- TopOfMemory = MemDetect ();\r
- }\r
+ InitializeRamRegions ();\r
\r
- if (XenLeaf != 0) {\r
+ if (mXen) {\r
DEBUG ((EFI_D_INFO, "Xen was detected\n"));\r
- InitializeXen (XenLeaf);\r
+ InitializeXen ();\r
}\r
\r
- ReserveEmuVariableNvStore ();\r
+ if (mBootMode != BOOT_ON_S3_RESUME) {\r
+ ReserveEmuVariableNvStore ();\r
\r
- PeiFvInitialization ();\r
+ PeiFvInitialization ();\r
\r
- if (XenLeaf != 0) {\r
- XenMemMapInitialization ();\r
- } else {\r
- MemMapInitialization (TopOfMemory);\r
+ MemMapInitialization ();\r
}\r
\r
MiscInitialization ();\r
\r
- BootModeInitialization ();\r
-\r
return EFI_SUCCESS;\r
}\r
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