OvmfPkg/PlatformPei: Skip various items for S3 resume

[mirror_edk2.git] / OvmfPkg / PlatformPei / Platform.c

diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c
index d395bc191ad1db81e9db55701a1d8f1eaa92ac0d..11b4cb7a14800aa75e3f69ba6977092546dfb331 100644 (file)
--- a/OvmfPkg/PlatformPei/Platform.c
+++ b/OvmfPkg/PlatformPei/Platform.c
@@ -1,7 +1,7 @@
 /**@file\r
   Platform PEI driver\r
 \r
-  Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>\r
+  Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>\r
   Copyright (c) 2011, Andrei Warkentin <andreiw@motorola.com>\r
 \r
   This program and the accompanying materials\r
@@ -30,9 +30,11 @@
 #include <Library/PciLib.h>\r
 #include <Library/PeimEntryPoint.h>\r
 #include <Library/PeiServicesLib.h>\r
+#include <Library/QemuFwCfgLib.h>\r
 #include <Library/ResourcePublicationLib.h>\r
 #include <Guid/MemoryTypeInformation.h>\r
 #include <Ppi/MasterBootMode.h>\r
+#include <IndustryStandard/Pci22.h>\r
 \r
 #include "Platform.h"\r
 #include "Cmos.h"\r
@@ -58,6 +60,11 @@ EFI_PEI_PPI_DESCRIPTOR   mPpiBootMode[] = {
 };\r
 \r
 \r
+EFI_BOOT_MODE mBootMode = BOOT_WITH_FULL_CONFIGURATION;\r
+\r
+BOOLEAN mS3Supported = FALSE;\r
+\r
+\r
 VOID\r
 AddIoMemoryBaseSizeHob (\r
   EFI_PHYSICAL_ADDRESS        MemoryBase,\r
@@ -162,10 +169,9 @@ AddUntestedMemoryRangeHob (
   AddUntestedMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));\r
 }\r
 \r
-\r
 VOID\r
 MemMapInitialization (\r
-  EFI_PHYSICAL_ADDRESS  TopOfMemory\r
+  VOID\r
   )\r
 {\r
   //\r
@@ -188,35 +194,38 @@ MemMapInitialization (
     0x4000\r
     );\r
 \r
-  //\r
-  // Add PCI MMIO space available to PCI resource allocations\r
-  //\r
-  if (TopOfMemory < BASE_2GB) {\r
-    AddIoMemoryBaseSizeHob (BASE_2GB, 0xFC000000 - BASE_2GB);\r
-  } else {\r
-    AddIoMemoryBaseSizeHob (TopOfMemory, 0xFC000000 - TopOfMemory);\r
-  }\r
-\r
-  //\r
-  // Local APIC range\r
-  //\r
-  AddIoMemoryBaseSizeHob (0xFEC80000, SIZE_512KB);\r
-\r
-  //\r
-  // I/O APIC range\r
-  //\r
-  AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_512KB);\r
-\r
   //\r
   // Video memory + Legacy BIOS region\r
   //\r
   AddIoMemoryRangeHob (0x0A0000, BASE_1MB);\r
+\r
+  if (!mXen) {\r
+    UINT32  TopOfLowRam;\r
+    TopOfLowRam = GetSystemMemorySizeBelow4gb ();\r
+\r
+    //\r
+    // address       purpose   size\r
+    // ------------  --------  -------------------------\r
+    // max(top, 2g)  PCI MMIO  0xFC000000 - max(top, 2g)\r
+    // 0xFC000000    gap                           44 MB\r
+    // 0xFEC00000    IO-APIC                        4 KB\r
+    // 0xFEC01000    gap                         1020 KB\r
+    // 0xFED00000    HPET                           1 KB\r
+    // 0xFED00400    gap                         1023 KB\r
+    // 0xFEE00000    LAPIC                          1 MB\r
+    //\r
+    AddIoMemoryRangeHob (TopOfLowRam < BASE_2GB ?\r
+                         BASE_2GB : TopOfLowRam, 0xFC000000);\r
+    AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB);\r
+    AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB);\r
+    AddIoMemoryBaseSizeHob (PcdGet32(PcdCpuLocalApicBaseAddress), SIZE_1MB);\r
+  }\r
 }\r
 \r
 \r
 VOID\r
 MiscInitialization (\r
-  BOOLEAN Xen\r
+  VOID\r
   )\r
 {\r
   //\r
@@ -229,22 +238,50 @@ MiscInitialization (
   //\r
   BuildCpuHob (36, 16);\r
 \r
-  if (!Xen) {\r
+  //\r
+  // If PMREGMISC/PMIOSE is set, assume the ACPI PMBA has been configured (for\r
+  // example by Xen) and skip the setup here. This matches the logic in\r
+  // AcpiTimerLibConstructor ().\r
+  //\r
+  if ((PciRead8 (PCI_LIB_ADDRESS (0, 1, 3, 0x80)) & 0x01) == 0) {\r
+    //\r
+    // The PEI phase should be exited with fully accessibe PIIX4 IO space:\r
+    // 1. set PMBA\r
+    //\r
+    PciAndThenOr32 (\r
+      PCI_LIB_ADDRESS (0, 1, 3, 0x40),\r
+      (UINT32) ~0xFFC0,\r
+      PcdGet16 (PcdAcpiPmBaseAddress)\r
+      );\r
+\r
     //\r
-    // Set the PM I/O base address to 0x400\r
+    // 2. set PCICMD/IOSE\r
     //\r
-    PciAndThenOr32 (PCI_LIB_ADDRESS (0, 1, 3, 0x40), (UINT32) ~0xfc0, 0x400);\r
+    PciOr8 (\r
+      PCI_LIB_ADDRESS (0, 1, 3, PCI_COMMAND_OFFSET),\r
+      EFI_PCI_COMMAND_IO_SPACE\r
+      );\r
+\r
+    //\r
+    // 3. set PMREGMISC/PMIOSE\r
+    //\r
+    PciOr8 (PCI_LIB_ADDRESS (0, 1, 3, 0x80), 0x01);\r
   }\r
 }\r
 \r
 \r
 VOID\r
 BootModeInitialization (\r
+  VOID\r
   )\r
 {\r
-  EFI_STATUS Status;\r
+  EFI_STATUS    Status;\r
+\r
+  if (CmosRead8 (0xF) == 0xFE) {\r
+    mBootMode = BOOT_ON_S3_RESUME;\r
+  }\r
 \r
-  Status = PeiServicesSetBootMode (BOOT_WITH_FULL_CONFIGURATION);\r
+  Status = PeiServicesSetBootMode (mBootMode);\r
   ASSERT_EFI_ERROR (Status);\r
 \r
   Status = PeiServicesInstallPpi (mPpiBootMode);\r
@@ -266,8 +303,9 @@ ReserveEmuVariableNvStore (
   //\r
   VariableStore =\r
     (EFI_PHYSICAL_ADDRESS)(UINTN)\r
-      AllocateRuntimePool (\r
-        2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)\r
+      AllocateAlignedRuntimePages (\r
+        EFI_SIZE_TO_PAGES (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)),\r
+        PcdGet32 (PcdFlashNvStorageFtwSpareSize)\r
         );\r
   DEBUG ((EFI_D_INFO,\r
           "Reserved variable store memory: 0x%lX; size: %dkb\n",\r
@@ -315,28 +353,37 @@ InitializePlatform (
   IN CONST EFI_PEI_SERVICES     **PeiServices\r
   )\r
 {\r
-  EFI_STATUS            Status;\r
-  EFI_PHYSICAL_ADDRESS  TopOfMemory;\r
-  BOOLEAN               Xen;\r
-\r
   DEBUG ((EFI_D_ERROR, "Platform PEIM Loaded\n"));\r
 \r
   DebugDumpCmos ();\r
 \r
-  TopOfMemory = MemDetect ();\r
+  XenDetect ();\r
+\r
+  if (QemuFwCfgS3Enabled ()) {\r
+    DEBUG ((EFI_D_INFO, "S3 support was detected on QEMU\n"));\r
+    mS3Supported = TRUE;\r
+  }\r
+\r
+  BootModeInitialization ();\r
 \r
-  Status = InitializeXen ();\r
-  Xen = EFI_ERROR (Status) ? FALSE : TRUE;\r
+  PublishPeiMemory ();\r
 \r
-  ReserveEmuVariableNvStore ();\r
+  InitializeRamRegions ();\r
 \r
-  PeiFvInitialization ();\r
+  if (mXen) {\r
+    DEBUG ((EFI_D_INFO, "Xen was detected\n"));\r
+    InitializeXen ();\r
+  }\r
 \r
-  MemMapInitialization (TopOfMemory);\r
+  if (mBootMode != BOOT_ON_S3_RESUME) {\r
+    ReserveEmuVariableNvStore ();\r
 \r
-  MiscInitialization (Xen);\r
+    PeiFvInitialization ();\r
 \r
-  BootModeInitialization ();\r
+    MemMapInitialization ();\r
+  }\r
+\r
+  MiscInitialization ();\r
 \r
   return EFI_SUCCESS;\r
 }\r