OvmfPkg/QemuVideoDxe/VbeShim: handle PAM1 register on Q35 correctly

[mirror_edk2.git] / OvmfPkg / QemuVideoDxe / VbeShim.c

diff --git a/OvmfPkg/QemuVideoDxe/VbeShim.c b/OvmfPkg/QemuVideoDxe/VbeShim.c
index bc90e067266de5e867764a93ed4f6ab9175b6827..e45a08e8873f15cdf366b0b4a537e6b579460392 100644 (file)
--- a/OvmfPkg/QemuVideoDxe/VbeShim.c
+++ b/OvmfPkg/QemuVideoDxe/VbeShim.c
@@ -25,6 +25,7 @@
 #include <Library/DebugLib.h>\r
 #include <Library/PciLib.h>\r
 #include <Library/PrintLib.h>\r
+#include <OvmfPlatforms.h>\r
 \r
 #include "Qemu.h"\r
 #include "VbeShim.h"\r
@@ -64,6 +65,7 @@ InstallVbeShim (
   UINTN                Segment0Pages;\r
   IVT_ENTRY            *Int0x10;\r
   EFI_STATUS           Segment0AllocationStatus;\r
+  UINT16               HostBridgeDevId;\r
   UINTN                Pam1Address;\r
   UINT8                Pam1;\r
   UINTN                SegmentCPages;\r
@@ -131,7 +133,30 @@ InstallVbeShim (
   //\r
   // Put the shim in place first.\r
   //\r
-  Pam1Address = PCI_LIB_ADDRESS (0, 0, 0, 0x5A);\r
+  // Start by determining the address of the PAM1 register.\r
+  //\r
+  HostBridgeDevId = PcdGet16 (PcdOvmfHostBridgePciDevId);\r
+  switch (HostBridgeDevId) {\r
+  case INTEL_82441_DEVICE_ID:\r
+    Pam1Address = PMC_REGISTER_PIIX4 (PIIX4_PAM1);\r
+    break;\r
+  case INTEL_Q35_MCH_DEVICE_ID:\r
+    Pam1Address = DRAMC_REGISTER_Q35 (MCH_PAM1);\r
+    break;\r
+  default:\r
+    DEBUG ((\r
+      DEBUG_ERROR,\r
+      "%a: unknown host bridge device ID: 0x%04x\n",\r
+      __FUNCTION__,\r
+      HostBridgeDevId\r
+      ));\r
+    ASSERT (FALSE);\r
+\r
+    if (!EFI_ERROR (Segment0AllocationStatus)) {\r
+      gBS->FreePages (Segment0, Segment0Pages);\r
+    }\r
+    return;\r
+  }\r
   //\r
   // low nibble covers 0xC0000 to 0xC3FFF\r
   // high nibble covers 0xC4000 to 0xC7FFF\r