PcAtChipsetPkg: Clean up source files

[mirror_edk2.git] / PcAtChipsetPkg / Library / BaseIoApicLib / IoApicLib.c

diff --git a/PcAtChipsetPkg/Library/BaseIoApicLib/IoApicLib.c b/PcAtChipsetPkg/Library/BaseIoApicLib/IoApicLib.c
index 42b3f21ec107137acfa34d50ad3bb5f2572ded23..0b8f888e7ee2f510972dfc1410b7fcbdafec1918 100644 (file)
--- a/PcAtChipsetPkg/Library/BaseIoApicLib/IoApicLib.c
+++ b/PcAtChipsetPkg/Library/BaseIoApicLib/IoApicLib.c
@@ -1,10 +1,10 @@
-/** @file \r
+/** @file\r
   I/O APIC library.\r
 \r
   I/O APIC library assumes I/O APIC is enabled. It does not\r
   handles cases where I/O APIC is disabled.\r
 \r
-  Copyright (c) 2011, Intel Corporation. All rights reserved.<BR>\r
+  Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.<BR>\r
   This program and the accompanying materials\r
   are licensed and made available under the terms and conditions of the BSD License\r
   which accompanies this distribution.  The full text of the license may be found at\r
@@ -30,7 +30,7 @@
   Read a 32-bit I/O APIC register.\r
 \r
   If Index is >= 0x100, then ASSERT().\r
-  \r
+\r
   @param  Index  Specifies the I/O APIC register to read.\r
 \r
   @return  The 32-bit value read from the I/O APIC register specified by Index.\r
@@ -50,7 +50,7 @@ IoApicRead (
   Write a 32-bit I/O APIC register.\r
 \r
   If Index is >= 0x100, then ASSERT().\r
-  \r
+\r
   @param  Index  Specifies the I/O APIC register to write.\r
   @param  Value  Specifies the value to write to the I/O APIC register specified by Index.\r
 \r
@@ -71,7 +71,7 @@ IoApicWrite (
 /**\r
   Set the interrupt mask of an I/O APIC interrupt.\r
 \r
-  If Irq is larger than the maximum number I/O APIC redirection entries, then ASSERT(). \r
+  If Irq is larger than the maximum number I/O APIC redirection entries, then ASSERT().\r
 \r
   @param  Irq     Specifies the I/O APIC interrupt to enable or disable.\r
   @param  Enable  If TRUE, then enable the I/O APIC interrupt specified by Irq.\r
@@ -98,13 +98,13 @@ IoApicEnableInterrupt (
 \r
 /**\r
   Configures an I/O APIC interrupt.\r
-  \r
+\r
   Configure an I/O APIC Redirection Table Entry to deliver an interrupt in physical\r
-  mode to the Local APIC of the currntly executing CPU.  The default state of the \r
+  mode to the Local APIC of the currntly executing CPU.  The default state of the\r
   entry is for the interrupt to be disabled (masked).  IoApicEnableInterrupts() must\r
   be used to enable(unmask) the I/O APIC Interrupt.\r
- \r
-  If Irq is larger than the maximum number I/O APIC redirection entries, then ASSERT(). \r
+\r
+  If Irq is larger than the maximum number I/O APIC redirection entries, then ASSERT().\r
   If Vector >= 0x100, then ASSERT().\r
   If DeliveryMode is not supported, then ASSERT().\r
 \r
@@ -142,11 +142,11 @@ IoApicConfigureInterrupt (
   ASSERT (Irq <= Version.Bits.MaximumRedirectionEntry);\r
   ASSERT (Vector <= 0xFF);\r
   ASSERT (DeliveryMode < 8 && DeliveryMode != 6 && DeliveryMode != 3);\r
-  \r
+\r
   Entry.Uint32.Low = IoApicRead (IO_APIC_REDIRECTION_TABLE_ENTRY_INDEX + Irq * 2);\r
   Entry.Bits.Vector          = (UINT8)Vector;\r
   Entry.Bits.DeliveryMode    = (UINT32)DeliveryMode;\r
-  Entry.Bits.DestinationMode = 0; \r
+  Entry.Bits.DestinationMode = 0;\r
   Entry.Bits.Polarity        = AssertionLevel ? 0 : 1;\r
   Entry.Bits.TriggerMode     = LevelTriggered ? 1 : 0;\r
   Entry.Bits.Mask            = 1;\r