# This package is designed to public interfaces and implementation which follows\r
# PcAt defacto standard.\r
#\r
-# Copyright (c) 2009 - 2015, Intel Corporation. All rights reserved.<BR>\r
+# Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>\r
# Copyright (c) 2017, AMD Inc. All rights reserved.<BR>\r
#\r
# This program and the accompanying materials\r
## @libraryclass Provides functions to manage I/O APIC Redirection Table Entries.\r
#\r
IoApicLib|Include/Library/IoApicLib.h\r
- \r
+\r
[Guids]\r
gPcAtChipsetPkgTokenSpaceGuid = { 0x326ae723, 0xae32, 0x4589, { 0x98, 0xb8, 0xca, 0xc2, 0x3c, 0xdc, 0xc1, 0xb1 } }\r
\r
# 1) If platform only support pure UEFI, value should be set to 0xFFFF or 0xFFFE;\r
# Because only clock interrupt is allowed in legacy mode in pure UEFI platform.<BR>\r
# 2) If platform install CSM and use thunk module:<BR>\r
- # a) If thunk call provided by CSM binary requires some legacy interrupt support, the corresponding bit \r
+ # a) If thunk call provided by CSM binary requires some legacy interrupt support, the corresponding bit\r
# should be opened as 0.<BR>\r
# For example, if keyboard interfaces provided CSM binary use legacy keyboard interrupt in 8259 bit 1, then\r
# the value should be set to 0xFFFC.<BR>\r
# to 0xFFFF or 0xFFFE.<BR>\r
#\r
# The default value of legacy mode mask could be changed by EFI_LEGACY_8259_PROTOCOL->SetMask(). But it is rarely\r
- # need change it except some special cases such as when initializing the CSM binary, it should be set to 0xFFFF to \r
+ # need change it except some special cases such as when initializing the CSM binary, it should be set to 0xFFFF to\r
# mask all legacy interrupt. Please restore the original legacy mask value if changing is made for these special case.<BR>\r
# @Prompt 8259 Legacy Mode mask.\r
gPcAtChipsetPkgTokenSpaceGuid.Pcd8259LegacyModeMask|0xFFFF|UINT16|0x00000001\r
- \r
+\r
## Pcd8259LegacyModeEdgeLevel defines the default edge level for legacy mode's interrrupt controller.\r
# For the corresponding bits, 0 = Edge triggered and 1 = Level triggered.\r
# @Prompt 8259 Legacy Mode edge level.\r
# The default value of 100000 100 ns units is the same as 10 ms.\r
# @Prompt Default period of HPET timer.\r
gPcAtChipsetPkgTokenSpaceGuid.PcdHpetDefaultTimerPeriod|100000|UINT64|0x0000000B\r
- \r
+\r
## This PCD specifies the base address of the IO APIC.\r
# @Prompt IO APIC base address.\r
gPcAtChipsetPkgTokenSpaceGuid.PcdIoApicBaseAddress|0xFEC00000|UINT32|0x0000000C\r
# @Prompt Maximal valid year in RTC.\r
# @Expression 0x80000001 | gPcAtChipsetPkgTokenSpaceGuid.PcdMaximalValidYear < gPcAtChipsetPkgTokenSpaceGuid.PcdMinimalValidYear + 100\r
gPcAtChipsetPkgTokenSpaceGuid.PcdMaximalValidYear|2097|UINT16|0x0000000E\r
- \r
+\r
[PcdsFixedAtBuild, PcdsPatchableInModule]\r
## Defines the ACPI register set base address.\r
- # The invalid 0xFFFF is as its default value. It must be configured to the real value. \r
+ # The invalid 0xFFFF is as its default value. It must be configured to the real value.\r
# @Prompt ACPI Timer IO Port Address\r
gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddress |0xFFFF|UINT16|0x00000010\r
\r
gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBusNumber | 0x00| UINT8|0x00000011\r
\r
## Defines the PCI Device Number of the PCI device that contains the BAR and Enable for ACPI hardware registers.\r
- # The invalid 0xFF is as its default value. It must be configured to the real value. \r
+ # The invalid 0xFF is as its default value. It must be configured to the real value.\r
# @Prompt ACPI Hardware PCI Device Number\r
gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciDeviceNumber | 0xFF| UINT8|0x00000012\r
\r
## Defines the PCI Function Number of the PCI device that contains the BAR and Enable for ACPI hardware registers.\r
- # The invalid 0xFF is as its default value. It must be configured to the real value. \r
+ # The invalid 0xFF is as its default value. It must be configured to the real value.\r
# @Prompt ACPI Hardware PCI Function Number\r
gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciFunctionNumber | 0xFF| UINT8|0x00000013\r
- \r
+\r
## Defines the PCI Register Offset of the PCI device that contains the Enable for ACPI hardware registers.\r
- # The invalid 0xFFFF is as its default value. It must be configured to the real value. \r
+ # The invalid 0xFFFF is as its default value. It must be configured to the real value.\r
# @Prompt ACPI Hardware PCI Register Offset\r
gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciEnableRegisterOffset |0xFFFF|UINT16|0x00000014\r
- \r
+\r
## Defines the bit mask that must be set to enable the APIC hardware register BAR.\r
# @Prompt ACPI Hardware PCI Bar Enable BitMask\r
gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoBarEnableMask | 0x00| UINT8|0x00000015\r
- \r
+\r
## Defines the PCI Register Offset of the PCI device that contains the BAR for ACPI hardware registers.\r
- # The invalid 0xFFFF is as its default value. It must be configured to the real value. \r
+ # The invalid 0xFFFF is as its default value. It must be configured to the real value.\r
# @Prompt ACPI Hardware PCI Bar Register Offset\r
gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBarRegisterOffset |0xFFFF|UINT16|0x00000016\r
\r
# @Prompt Initial value for Register_D in RTC.\r
gPcAtChipsetPkgTokenSpaceGuid.PcdInitialValueRtcRegisterD|0x00|UINT8|0x0000001D\r
\r
+ ## Specifies RTC Index Register address in I/O space.\r
+ # @Prompt RTC Index Register address\r
+ gPcAtChipsetPkgTokenSpaceGuid.PcdRtcIndexRegister|0x70|UINT8|0x0000001E\r
+\r
+ ## Specifies RTC Target Register address in I/O space.\r
+ # @Prompt RTC Target Register address\r
+ gPcAtChipsetPkgTokenSpaceGuid.PcdRtcTargetRegister|0x71|UINT8|0x0000001F\r
+\r
[UserExtensions.TianoCore."ExtraFiles"]\r
PcAtChipsetPkgExtra.uni\r
projects / mirror_edk2.git / blobdiff