-#/** @file\r
+## @file\r
# Public definitions for PcAtChipset package.\r
#\r
# This package is designed to public interfaces and implementation which follows\r
# PcAt defacto standard.\r
#\r
-# Copyright (c) 2009, Intel Corporation.\r
+# Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>\r
+# Copyright (c) 2017, AMD Inc. All rights reserved.<BR>\r
#\r
-# All rights reserved. This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php\r
+# SPDX-License-Identifier: BSD-2-Clause-Patent\r
#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-#**/\r
+##\r
\r
[Defines]\r
DEC_SPECIFICATION = 0x00010005\r
PACKAGE_NAME = PcAtChipsetPkg\r
+ PACKAGE_UNI_FILE = PcAtChipsetPkg.uni\r
PACKAGE_GUID = B728689A-52D3-4b8c-AE89-2CE5514CC6DC\r
- PACKAGE_VERSION = 0.1\r
+ PACKAGE_VERSION = 0.3\r
+\r
+[Includes]\r
+ Include\r
+\r
+[LibraryClasses]\r
+ ## @libraryclass Provides functions to manage I/O APIC Redirection Table Entries.\r
+ #\r
+ IoApicLib|Include/Library/IoApicLib.h\r
+\r
+[Guids]\r
+ gPcAtChipsetPkgTokenSpaceGuid = { 0x326ae723, 0xae32, 0x4589, { 0x98, 0xb8, 0xca, 0xc2, 0x3c, 0xdc, 0xc1, 0xb1 } }\r
\r
-[PcdsFixedAtBuild.common]\r
- ## Pcd8259LegacyModeMask defines the default mask value for platform. This value is determined\r
+#\r
+# [Error.gPcAtChipsetPkgTokenSpaceGuid]\r
+# 0x80000001 | Invalid value provided.\r
+#\r
+\r
+[PcdsFeatureFlag]\r
+ ## Indicates the HPET Timer will be configured to use MSI interrupts if the HPET timer supports them, or use I/O APIC interrupts.<BR><BR>\r
+ # TRUE - Configures the HPET Timer to use MSI interrupts if the HPET Timer supports them.<BR>\r
+ # FALSE - Configures the HPET Timer to use I/O APIC interrupts.<BR>\r
+ # @Prompt Configure HPET to use MSI.\r
+ gPcAtChipsetPkgTokenSpaceGuid.PcdHpetMsiEnable|TRUE|BOOLEAN|0x00001000\r
+\r
+[PcdsFixedAtBuild, PcdsDynamic, PcdsDynamicEx, PcdsPatchableInModule]\r
+ ## Pcd8259LegacyModeMask defines the default mask value for platform. This value is determined<BR><BR>\r
# 1) If platform only support pure UEFI, value should be set to 0xFFFF or 0xFFFE;\r
- # Because only clock interrupt is allowed in legacy mode in pure UEFI platform.\r
- # 2) If platform install CSM and use thunk module:\r
- # a) If thunk call provided by CSM binary requires some legacy interrupt support, the corresponding bit \r
- # should be opened as 0.\r
- # For example, if keyboard interfaces provided CSM binary use legacy keyboard interrupt in 8259 bit 2, then\r
- # the value should be set to 0xFFFC\r
+ # Because only clock interrupt is allowed in legacy mode in pure UEFI platform.<BR>\r
+ # 2) If platform install CSM and use thunk module:<BR>\r
+ # a) If thunk call provided by CSM binary requires some legacy interrupt support, the corresponding bit\r
+ # should be opened as 0.<BR>\r
+ # For example, if keyboard interfaces provided CSM binary use legacy keyboard interrupt in 8259 bit 1, then\r
+ # the value should be set to 0xFFFC.<BR>\r
# b) If all thunk call provied by CSM binary do not require legacy interrupt support, value should be set\r
- # to 0xFFFF or 0xFFFE.\r
- #\r
- # Because the value is used as intialization value, PCD's type should be FixedAtBuild.\r
+ # to 0xFFFF or 0xFFFE.<BR>\r
#\r
# The default value of legacy mode mask could be changed by EFI_LEGACY_8259_PROTOCOL->SetMask(). But it is rarely\r
- # need change it except some special cases such as when initializing the CSM binary, it should be set to 0xFFFF to \r
- # mask all legacy interrupt. Please restore the original legacy mask value if changing is made for these special case.\r
- #\r
- gPcAtChipsetPkgTokenSpaceGuid.Pcd8259LegacyModeMask|0x00000001|UINT16|0xFFFF\r
- \r
+ # need change it except some special cases such as when initializing the CSM binary, it should be set to 0xFFFF to\r
+ # mask all legacy interrupt. Please restore the original legacy mask value if changing is made for these special case.<BR>\r
+ # @Prompt 8259 Legacy Mode mask.\r
+ gPcAtChipsetPkgTokenSpaceGuid.Pcd8259LegacyModeMask|0xFFFF|UINT16|0x00000001\r
+\r
## Pcd8259LegacyModeEdgeLevel defines the default edge level for legacy mode's interrrupt controller.\r
- gPcAtChipsetPkgTokenSpaceGuid.Pcd8259LegacyModeEdgeLevel|0x00000002|UINT16|0x0000\r
- \r
-[Guids.common]\r
- gPcAtChipsetPkgTokenSpaceGuid = { 0x326ae723, 0xae32, 0x4589, { 0x98, 0xb8, 0xca, 0xc2, 0x3c, 0xdc, 0xc1, 0xb1 } }\r
+ # For the corresponding bits, 0 = Edge triggered and 1 = Level triggered.\r
+ # @Prompt 8259 Legacy Mode edge level.\r
+ gPcAtChipsetPkgTokenSpaceGuid.Pcd8259LegacyModeEdgeLevel|0x0000|UINT16|0x00000002\r
+\r
+ ## Indicates if we need enable IsaAcpiCom1 device.<BR><BR>\r
+ # TRUE - Enables IsaAcpiCom1 device.<BR>\r
+ # FALSE - Doesn't enable IsaAcpiCom1 device.<BR>\r
+ # @Prompt Enable IsaAcpiCom1 device.\r
+ gPcAtChipsetPkgTokenSpaceGuid.PcdIsaAcpiCom1Enable|TRUE|BOOLEAN|0x00000003\r
+\r
+ ## Indicates if we need enable IsaAcpiCom2 device.<BR><BR>\r
+ # TRUE - Enables IsaAcpiCom2 device.<BR>\r
+ # FALSE - Doesn't enable IsaAcpiCom2 device.<BR>\r
+ # @Prompt Enable IsaAcpiCom12 device.\r
+ gPcAtChipsetPkgTokenSpaceGuid.PcdIsaAcpiCom2Enable|TRUE|BOOLEAN|0x00000004\r
+\r
+ ## Indicates if we need enable IsaAcpiPs2Keyboard device.<BR><BR>\r
+ # TRUE - Enables IsaAcpiPs2Keyboard device.<BR>\r
+ # FALSE - Doesn't enable IsaAcpiPs2Keyboard device.<BR>\r
+ # @Prompt Enable IsaAcpiPs2Keyboard device.\r
+ gPcAtChipsetPkgTokenSpaceGuid.PcdIsaAcpiPs2KeyboardEnable|TRUE|BOOLEAN|0x00000005\r
+\r
+ ## Indicates if we need enable IsaAcpiPs2Mouse device.<BR><BR>\r
+ # TRUE - Enables IsaAcpiPs2Mouse device.<BR>\r
+ # FALSE - Doesn't enable IsaAcpiPs2Mouse device.<BR>\r
+ # @Prompt Enable IsaAcpiPs2Mouse device.\r
+ gPcAtChipsetPkgTokenSpaceGuid.PcdIsaAcpiPs2MouseEnable|TRUE|BOOLEAN|0x00000006\r
+\r
+ ## Indicates if we need enable IsaAcpiFloppyA device.<BR><BR>\r
+ # TRUE - Enables IsaAcpiFloppyA device.<BR>\r
+ # FALSE - Doesn't enable IsaAcpiFloppyA device.<BR>\r
+ # @Prompt Enable IsaAcpiFloppyA device.\r
+ gPcAtChipsetPkgTokenSpaceGuid.PcdIsaAcpiFloppyAEnable|TRUE|BOOLEAN|0x00000007\r
+\r
+ ## Indicates if we need enable IsaAcpiFloppyB device.<BR><BR>\r
+ # TRUE - Enables IsaAcpiFloppyB device.<BR>\r
+ # FALSE - Doesn't enable IsaAcpiFloppyB device.<BR>\r
+ # @Prompt Enable IsaAcpiFloppyB device.\r
+ gPcAtChipsetPkgTokenSpaceGuid.PcdIsaAcpiFloppyBEnable|TRUE|BOOLEAN|0x00000008\r
+\r
+ ## This PCD specifies the base address of the HPET timer.\r
+ # @Prompt HPET base address.\r
+ gPcAtChipsetPkgTokenSpaceGuid.PcdHpetBaseAddress|0xFED00000|UINT32|0x00000009\r
+\r
+ ## This PCD specifies the Local APIC Interrupt Vector for the HPET Timer.\r
+ # @Prompt HPET local APIC vector.\r
+ gPcAtChipsetPkgTokenSpaceGuid.PcdHpetLocalApicVector|0x40|UINT8|0x0000000A\r
+\r
+ ## This PCD specifies the defaut period of the HPET Timer in 100 ns units.\r
+ # The default value of 100000 100 ns units is the same as 10 ms.\r
+ # @Prompt Default period of HPET timer.\r
+ gPcAtChipsetPkgTokenSpaceGuid.PcdHpetDefaultTimerPeriod|100000|UINT64|0x0000000B\r
+\r
+ ## This PCD specifies the base address of the IO APIC.\r
+ # @Prompt IO APIC base address.\r
+ gPcAtChipsetPkgTokenSpaceGuid.PcdIoApicBaseAddress|0xFEC00000|UINT32|0x0000000C\r
+\r
+ ## This PCD specifies the minimal valid year in RTC.\r
+ # @Prompt Minimal valid year in RTC.\r
+ gPcAtChipsetPkgTokenSpaceGuid.PcdMinimalValidYear|1998|UINT16|0x0000000D\r
+\r
+ ## This PCD specifies the maximal valid year in RTC.\r
+ # @Prompt Maximal valid year in RTC.\r
+ # @Expression 0x80000001 | gPcAtChipsetPkgTokenSpaceGuid.PcdMaximalValidYear < gPcAtChipsetPkgTokenSpaceGuid.PcdMinimalValidYear + 100\r
+ gPcAtChipsetPkgTokenSpaceGuid.PcdMaximalValidYear|2097|UINT16|0x0000000E\r
+\r
+[PcdsFixedAtBuild, PcdsPatchableInModule]\r
+ ## Defines the ACPI register set base address.\r
+ # The invalid 0xFFFF is as its default value. It must be configured to the real value.\r
+ # @Prompt ACPI Timer IO Port Address\r
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddress |0xFFFF|UINT16|0x00000010\r
+\r
+ ## Defines the PCI Bus Number of the PCI device that contains the BAR and Enable for ACPI hardware registers.\r
+ # @Prompt ACPI Hardware PCI Bus Number\r
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBusNumber | 0x00| UINT8|0x00000011\r
+\r
+ ## Defines the PCI Device Number of the PCI device that contains the BAR and Enable for ACPI hardware registers.\r
+ # The invalid 0xFF is as its default value. It must be configured to the real value.\r
+ # @Prompt ACPI Hardware PCI Device Number\r
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciDeviceNumber | 0xFF| UINT8|0x00000012\r
+\r
+ ## Defines the PCI Function Number of the PCI device that contains the BAR and Enable for ACPI hardware registers.\r
+ # The invalid 0xFF is as its default value. It must be configured to the real value.\r
+ # @Prompt ACPI Hardware PCI Function Number\r
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciFunctionNumber | 0xFF| UINT8|0x00000013\r
+\r
+ ## Defines the PCI Register Offset of the PCI device that contains the Enable for ACPI hardware registers.\r
+ # The invalid 0xFFFF is as its default value. It must be configured to the real value.\r
+ # @Prompt ACPI Hardware PCI Register Offset\r
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciEnableRegisterOffset |0xFFFF|UINT16|0x00000014\r
+\r
+ ## Defines the bit mask that must be set to enable the APIC hardware register BAR.\r
+ # @Prompt ACPI Hardware PCI Bar Enable BitMask\r
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoBarEnableMask | 0x00| UINT8|0x00000015\r
+\r
+ ## Defines the PCI Register Offset of the PCI device that contains the BAR for ACPI hardware registers.\r
+ # The invalid 0xFFFF is as its default value. It must be configured to the real value.\r
+ # @Prompt ACPI Hardware PCI Bar Register Offset\r
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBarRegisterOffset |0xFFFF|UINT16|0x00000016\r
+\r
+ ## Defines the offset to the 32-bit Timer Value register that resides within the ACPI BAR.\r
+ # @Prompt Offset to 32-bit Timer register in ACPI BAR\r
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiPm1TmrOffset |0x0008|UINT16|0x00000017\r
+\r
+ ## Defines the bit mask to retrieve ACPI IO Port Base Address\r
+ # @Prompt ACPI IO Port Base Address Mask\r
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddressMask |0xFFFE|UINT16|0x00000018\r
+\r
+ ## Reset Control Register address in I/O space.\r
+ # @Prompt Reset Control Register address\r
+ gPcAtChipsetPkgTokenSpaceGuid.PcdResetControlRegister|0x64|UINT64|0x00000019\r
+\r
+ ## 8bit Reset Control Register value for cold reset.\r
+ # @Prompt Reset Control Register value for cold reset\r
+ gPcAtChipsetPkgTokenSpaceGuid.PcdResetControlValueColdReset|0xFE|UINT8|0x0000001A\r
+\r
+ ## Specifies the initial value for Register_A in RTC.\r
+ # @Prompt Initial value for Register_A in RTC.\r
+ gPcAtChipsetPkgTokenSpaceGuid.PcdInitialValueRtcRegisterA|0x26|UINT8|0x0000001B\r
+\r
+ ## Specifies the initial value for Register_B in RTC.\r
+ # @Prompt Initial value for Register_B in RTC.\r
+ gPcAtChipsetPkgTokenSpaceGuid.PcdInitialValueRtcRegisterB|0x02|UINT8|0x0000001C\r
+\r
+ ## Specifies the initial value for Register_D in RTC.\r
+ # @Prompt Initial value for Register_D in RTC.\r
+ gPcAtChipsetPkgTokenSpaceGuid.PcdInitialValueRtcRegisterD|0x00|UINT8|0x0000001D\r
+\r
+ ## Specifies RTC Index Register address in I/O space.\r
+ # @Prompt RTC Index Register address\r
+ gPcAtChipsetPkgTokenSpaceGuid.PcdRtcIndexRegister|0x70|UINT8|0x0000001E\r
+\r
+ ## Specifies RTC Target Register address in I/O space.\r
+ # @Prompt RTC Target Register address\r
+ gPcAtChipsetPkgTokenSpaceGuid.PcdRtcTargetRegister|0x71|UINT8|0x0000001F\r
\r
+[UserExtensions.TianoCore."ExtraFiles"]\r
+ PcAtChipsetPkgExtra.uni\r
projects / mirror_edk2.git / blobdiff