RefRefine soma code to make code run safely.

[mirror_edk2.git] / PcAtChipsetPkg / PcatRealTimeClockRuntimeDxe / PcRtc.h

diff --git a/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.h b/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.h
index 85492f7b5972a861cebeca9c78f025dac5dd4042..d38c8e1464a4e88c644f57a19e99b87347b24c95 100644 (file)
--- a/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.h
+++ b/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.h
@@ -84,9 +84,9 @@ typedef struct {
 // Register A\r
 //\r
 typedef struct {\r
-  UINT8 RS : 4;   // Rate Selection Bits\r
-  UINT8 DV : 3;   // Divisor\r
-  UINT8 UIP : 1;  // Update in progress\r
+  UINT8 Rs : 4;   // Rate Selection Bits\r
+  UINT8 Dv : 3;   // Divisor\r
+  UINT8 Uip : 1;  // Update in progress\r
 } RTC_REGISTER_A_BITS;\r
 \r
 typedef union {\r
@@ -98,14 +98,14 @@ typedef union {
 // Register B\r
 //\r
 typedef struct {\r
-  UINT8 DSE : 1;  // 0 - Daylight saving disabled  1 - Daylight savings enabled\r
-  UINT8 MIL : 1;  // 0 - 12 hour mode              1 - 24 hour mode\r
-  UINT8 DM : 1;   // 0 - BCD Format                1 - Binary Format\r
-  UINT8 SQWE : 1; // 0 - Disable SQWE output       1 - Enable SQWE output\r
-  UINT8 UIE : 1;  // 0 - Update INT disabled       1 - Update INT enabled\r
-  UINT8 AIE : 1;  // 0 - Alarm INT disabled        1 - Alarm INT Enabled\r
-  UINT8 PIE : 1;  // 0 - Periodic INT disabled     1 - Periodic INT Enabled\r
-  UINT8 SET : 1;  // 0 - Normal operation.         1 - Updates inhibited\r
+  UINT8 Dse : 1;  // 0 - Daylight saving disabled  1 - Daylight savings enabled\r
+  UINT8 Mil : 1;  // 0 - 12 hour mode              1 - 24 hour mode\r
+  UINT8 Dm : 1;   // 0 - BCD Format                1 - Binary Format\r
+  UINT8 Sqwe : 1; // 0 - Disable SQWE output       1 - Enable SQWE output\r
+  UINT8 Uie : 1;  // 0 - Update INT disabled       1 - Update INT enabled\r
+  UINT8 Aie : 1;  // 0 - Alarm INT disabled        1 - Alarm INT Enabled\r
+  UINT8 Pie : 1;  // 0 - Periodic INT disabled     1 - Periodic INT Enabled\r
+  UINT8 Set : 1;  // 0 - Normal operation.         1 - Updates inhibited\r
 } RTC_REGISTER_B_BITS;\r
 \r
 typedef union {\r
@@ -118,10 +118,10 @@ typedef union {
 //\r
 typedef struct {\r
   UINT8 Reserved : 4; // Read as zero.  Can not be written.\r
-  UINT8 UF : 1;       // Update End Interrupt Flag\r
-  UINT8 AF : 1;       // Alarm Interrupt Flag\r
-  UINT8 PF : 1;       // Periodic Interrupt Flag\r
-  UINT8 IRQF : 1;     // Iterrupt Request Flag = PF & PIE | AF & AIE | UF & UIE\r
+  UINT8 Uf : 1;       // Update End Interrupt Flag\r
+  UINT8 Af : 1;       // Alarm Interrupt Flag\r
+  UINT8 Pf : 1;       // Periodic Interrupt Flag\r
+  UINT8 Irqf : 1;     // Iterrupt Request Flag = PF & PIE | AF & AIE | UF & UIE\r
 } RTC_REGISTER_C_BITS;\r
 \r
 typedef union {\r
@@ -134,7 +134,7 @@ typedef union {
 //\r
 typedef struct {\r
   UINT8 Reserved : 7; // Read as zero.  Can not be written.\r
-  UINT8 VRT : 1;      // Valid RAM and Time\r
+  UINT8 Vrt : 1;      // Valid RAM and Time\r
 } RTC_REGISTER_D_BITS;\r
 \r
 typedef union {\r