\r
#include "PciHostBridge.h"\r
\r
-//\r
-// Support 64 K IO space\r
-//\r
-#define RES_IO_BASE 0x1000\r
-#define RES_IO_LIMIT 0xFFFF\r
-//\r
-// Support 4G address space\r
-//\r
-#define RES_MEM_BASE_1 0xF8000000\r
-#define RES_MEM_LIMIT_1 (0xFEC00000 - 1)\r
-\r
//\r
// Hard code: Root Bridge Number within the host bridge\r
// Root Bridge's attribute\r
};\r
\r
PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[1][1] = {\r
- {0, 0, 0, 0xffffffff, 0, 1 << 16}\r
+ {0, 0xff, 0x80000000, 0xffffffff, 0, 0xffff}\r
};\r
\r
EFI_HANDLE mDriverImageHandle;\r
//\r
// Implementation\r
//\r
+\r
/**\r
Entry point of this driver\r
\r
UINTN Loop2;\r
PCI_HOST_BRIDGE_INSTANCE *HostBridge;\r
PCI_ROOT_BRIDGE_INSTANCE *PrivateData;\r
- IN EFI_PHYSICAL_ADDRESS BaseAddress;\r
- IN UINT64 Length;\r
\r
mDriverImageHandle = ImageHandle;\r
\r
}\r
} \r
\r
- Status = gDS->AddIoSpace (\r
- EfiGcdIoTypeIo, \r
- RES_IO_BASE, \r
- RES_IO_LIMIT - RES_IO_BASE + 1\r
- );\r
- \r
- // PCI memory space from 3.75Gbytes->(4GBytes - BIOSFWH local APIC etc)\r
- Status = gDS->AddMemorySpace (\r
- EfiGcdMemoryTypeMemoryMappedIo, \r
- RES_MEM_BASE_1, \r
- (RES_MEM_LIMIT_1 - RES_MEM_BASE_1 + 1),\r
- 0\r
- );\r
- \r
- BaseAddress = 0x80000000;\r
- Length = RES_MEM_BASE_1 - BaseAddress;\r
- Status = gDS->AddMemorySpace (\r
- EfiGcdMemoryTypeMemoryMappedIo, \r
- BaseAddress, \r
- Length,\r
- 0\r
- );\r
- \r
return EFI_SUCCESS;\r
}\r
\r
required here. This notification can be used to perform any chipsetspecific\r
programming.\r
\r
- @param[in] PciResAlloc The instance pointer of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r
+ @param[in] This The instance pointer of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r
@param[in] Phase The phase during enumeration\r
\r
@retval EFI_NOT_READY This phase cannot be entered at this time. For example, this error\r
//\r
// Get the number of '1' in Alignment.\r
//\r
- BitsOfAlignment = HighBitSet64 (RootBridgeInstance->ResAllocNode[Index].Alignment) + 1;\r
+ BitsOfAlignment = (UINTN) (HighBitSet64 (RootBridgeInstance->ResAllocNode[Index].Alignment) + 1);\r
\r
switch (Index) {\r
\r
For D945 implementation, there is only one root bridge in PCI host bridge.\r
\r
@param[in] This The instance pointer of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r
- @param[in][out] RootBridgeHandle Returns the device handle of the next PCI root bridge.\r
+ @param[in, out] RootBridgeHandle Returns the device handle of the next PCI root bridge.\r
\r
@retval EFI_SUCCESS If parameter RootBridgeHandle = NULL, then return the first Rootbridge handle of the\r
specific Host bridge and return EFI_SUCCESS. \r
PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance;\r
PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance;\r
UINT8 *Temp;\r
- EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *ptr;\r
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Ptr;\r
UINT64 AddrLen;\r
UINT64 Alignment;\r
\r
RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);\r
if (RootBridgeHandle == RootBridgeInstance->Handle) {\r
while ( *Temp == 0x8A) {\r
- ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp ;\r
+ Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp ;\r
\r
//\r
// Check Address Length\r
//\r
- if (ptr->AddrLen > 0xffffffff) {\r
+ if (Ptr->AddrLen > 0xffffffff) {\r
return EFI_INVALID_PARAMETER;\r
}\r
\r
//\r
// Check address range alignment\r
//\r
- if (ptr->AddrRangeMax >= 0xffffffff || ptr->AddrRangeMax != (GetPowerOfTwo64 (ptr->AddrRangeMax + 1) - 1)) {\r
+ if (Ptr->AddrRangeMax >= 0xffffffff || Ptr->AddrRangeMax != (GetPowerOfTwo64 (Ptr->AddrRangeMax + 1) - 1)) {\r
return EFI_INVALID_PARAMETER;\r
}\r
\r
- switch (ptr->ResType) {\r
+ switch (Ptr->ResType) {\r
\r
case 0:\r
\r
//\r
// Check invalid Address Sapce Granularity\r
//\r
- if (ptr->AddrSpaceGranularity != 32) {\r
+ if (Ptr->AddrSpaceGranularity != 32) {\r
return EFI_INVALID_PARAMETER;\r
}\r
\r
// check the memory resource request is supported by PCI root bridge\r
//\r
if (RootBridgeInstance->RootBridgeAttrib == EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM &&\r
- ptr->SpecificFlag == 0x06) {\r
+ Ptr->SpecificFlag == 0x06) {\r
return EFI_INVALID_PARAMETER;\r
}\r
\r
- AddrLen = ptr->AddrLen;\r
- Alignment = ptr->AddrRangeMax;\r
- if (ptr->AddrSpaceGranularity == 32) {\r
- if (ptr->SpecificFlag == 0x06) {\r
+ AddrLen = Ptr->AddrLen;\r
+ Alignment = Ptr->AddrRangeMax;\r
+ if (Ptr->AddrSpaceGranularity == 32) {\r
+ if (Ptr->SpecificFlag == 0x06) {\r
//\r
// Apply from GCD\r
//\r
}\r
}\r
\r
- if (ptr->AddrSpaceGranularity == 64) {\r
- if (ptr->SpecificFlag == 0x06) {\r
+ if (Ptr->AddrSpaceGranularity == 64) {\r
+ if (Ptr->SpecificFlag == 0x06) {\r
RootBridgeInstance->ResAllocNode[TypePMem64].Status = ResSubmitted;\r
} else {\r
RootBridgeInstance->ResAllocNode[TypeMem64].Status = ResSubmitted;\r
break;\r
\r
case 1:\r
- AddrLen = (UINTN)ptr->AddrLen;\r
- Alignment = (UINTN)ptr->AddrRangeMax;\r
+ AddrLen = (UINTN) Ptr->AddrLen;\r
+ Alignment = (UINTN) Ptr->AddrRangeMax;\r
RootBridgeInstance->ResAllocNode[TypeIo].Length = AddrLen;\r
RootBridgeInstance->ResAllocNode[TypeIo].Alignment = Alignment;\r
RootBridgeInstance->ResAllocNode[TypeIo].Status = ResRequested;\r
UINTN Number; \r
VOID *Buffer; \r
UINT8 *Temp;\r
- EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *ptr;\r
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Ptr;\r
UINT64 ResStatus;\r
\r
Buffer = NULL;\r
Temp = Buffer;\r
for (Index = 0; Index < TypeBus; Index ++) {\r
if (RootBridgeInstance->ResAllocNode[Index].Status != ResNone) {\r
- ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp ;\r
+ Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp ;\r
ResStatus = RootBridgeInstance->ResAllocNode[Index].Status;\r
\r
switch (Index) {\r
//\r
// Io\r
//\r
- ptr->Desc = 0x8A;\r
- ptr->Len = 0x2B;\r
- ptr->ResType = 1;\r
- ptr->GenFlag = 0; \r
- ptr->SpecificFlag = 0;\r
- ptr->AddrRangeMin = RootBridgeInstance->ResAllocNode[Index].Base;\r
- ptr->AddrRangeMax = 0;\r
- ptr->AddrTranslationOffset = \\r
+ Ptr->Desc = 0x8A;\r
+ Ptr->Len = 0x2B;\r
+ Ptr->ResType = 1;\r
+ Ptr->GenFlag = 0; \r
+ Ptr->SpecificFlag = 0;\r
+ Ptr->AddrRangeMin = RootBridgeInstance->ResAllocNode[Index].Base;\r
+ Ptr->AddrRangeMax = 0;\r
+ Ptr->AddrTranslationOffset = \\r
(ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS;\r
- ptr->AddrLen = RootBridgeInstance->ResAllocNode[Index].Length;\r
+ Ptr->AddrLen = RootBridgeInstance->ResAllocNode[Index].Length;\r
break;\r
\r
case TypeMem32:\r
//\r
// Memory 32\r
// \r
- ptr->Desc = 0x8A;\r
- ptr->Len = 0x2B;\r
- ptr->ResType = 0;\r
- ptr->GenFlag = 0; \r
- ptr->SpecificFlag = 0;\r
- ptr->AddrSpaceGranularity = 32;\r
- ptr->AddrRangeMin = RootBridgeInstance->ResAllocNode[Index].Base;\r
- ptr->AddrRangeMax = 0;\r
- ptr->AddrTranslationOffset = \\r
+ Ptr->Desc = 0x8A;\r
+ Ptr->Len = 0x2B;\r
+ Ptr->ResType = 0;\r
+ Ptr->GenFlag = 0; \r
+ Ptr->SpecificFlag = 0;\r
+ Ptr->AddrSpaceGranularity = 32;\r
+ Ptr->AddrRangeMin = RootBridgeInstance->ResAllocNode[Index].Base;\r
+ Ptr->AddrRangeMax = 0;\r
+ Ptr->AddrTranslationOffset = \\r
(ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS; \r
- ptr->AddrLen = RootBridgeInstance->ResAllocNode[Index].Length;\r
+ Ptr->AddrLen = RootBridgeInstance->ResAllocNode[Index].Length;\r
break;\r
\r
case TypePMem32:\r
//\r
// Prefetch memory 32\r
//\r
- ptr->Desc = 0x8A;\r
- ptr->Len = 0x2B;\r
- ptr->ResType = 0;\r
- ptr->GenFlag = 0; \r
- ptr->SpecificFlag = 6;\r
- ptr->AddrSpaceGranularity = 32;\r
- ptr->AddrRangeMin = 0;\r
- ptr->AddrRangeMax = 0;\r
- ptr->AddrTranslationOffset = EFI_RESOURCE_NONEXISTENT; \r
- ptr->AddrLen = 0;\r
+ Ptr->Desc = 0x8A;\r
+ Ptr->Len = 0x2B;\r
+ Ptr->ResType = 0;\r
+ Ptr->GenFlag = 0; \r
+ Ptr->SpecificFlag = 6;\r
+ Ptr->AddrSpaceGranularity = 32;\r
+ Ptr->AddrRangeMin = 0;\r
+ Ptr->AddrRangeMax = 0;\r
+ Ptr->AddrTranslationOffset = EFI_RESOURCE_NONEXISTENT; \r
+ Ptr->AddrLen = 0;\r
break;\r
\r
case TypeMem64:\r
//\r
// Memory 64\r
//\r
- ptr->Desc = 0x8A;\r
- ptr->Len = 0x2B;\r
- ptr->ResType = 0;\r
- ptr->GenFlag = 0; \r
- ptr->SpecificFlag = 0;\r
- ptr->AddrSpaceGranularity = 64;\r
- ptr->AddrRangeMin = 0;\r
- ptr->AddrRangeMax = 0;\r
- ptr->AddrTranslationOffset = EFI_RESOURCE_NONEXISTENT; \r
- ptr->AddrLen = 0;\r
+ Ptr->Desc = 0x8A;\r
+ Ptr->Len = 0x2B;\r
+ Ptr->ResType = 0;\r
+ Ptr->GenFlag = 0; \r
+ Ptr->SpecificFlag = 0;\r
+ Ptr->AddrSpaceGranularity = 64;\r
+ Ptr->AddrRangeMin = 0;\r
+ Ptr->AddrRangeMax = 0;\r
+ Ptr->AddrTranslationOffset = EFI_RESOURCE_NONEXISTENT; \r
+ Ptr->AddrLen = 0;\r
break;\r
\r
case TypePMem64:\r
//\r
// Prefetch memory 64\r
//\r
- ptr->Desc = 0x8A;\r
- ptr->Len = 0x2B;\r
- ptr->ResType = 0;\r
- ptr->GenFlag = 0; \r
- ptr->SpecificFlag = 6;\r
- ptr->AddrSpaceGranularity = 64;\r
- ptr->AddrRangeMin = 0;\r
- ptr->AddrRangeMax = 0;\r
- ptr->AddrTranslationOffset = EFI_RESOURCE_NONEXISTENT; \r
- ptr->AddrLen = 0;\r
+ Ptr->Desc = 0x8A;\r
+ Ptr->Len = 0x2B;\r
+ Ptr->ResType = 0;\r
+ Ptr->GenFlag = 0; \r
+ Ptr->SpecificFlag = 6;\r
+ Ptr->AddrSpaceGranularity = 64;\r
+ Ptr->AddrRangeMin = 0;\r
+ Ptr->AddrRangeMax = 0;\r
+ Ptr->AddrTranslationOffset = EFI_RESOURCE_NONEXISTENT; \r
+ Ptr->AddrLen = 0;\r
break;\r
};\r
\r
return EFI_INVALID_PARAMETER;\r
}\r
\r
-/**\r
- Update attribute for PCI root bridge for specifc device.\r
-\r
- @param RootBridge Point to PCI root bridge.\r
- @param PciAddress The specific device PCI address\r
-**/\r
-STATIC\r
-VOID\r
-UpdateRootBridgeAttributes (\r
- IN PCI_ROOT_BRIDGE_INSTANCE *RootBridge,\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress\r
- )\r
-{\r
- EFI_STATUS Status;\r
- PCI_TYPE01 PciConfigurationHeader;\r
- UINT64 Attributes;\r
-\r
- //\r
- // Read the PCI Configuration Header for the device\r
- //\r
- Status = RootBridge->Io.Pci.Read (\r
- &RootBridge->Io,\r
- EfiPciWidthUint16,\r
- EFI_PCI_ADDRESS(\r
- PciAddress.Bus,\r
- PciAddress.Device,\r
- PciAddress.Function,\r
- 0\r
- ),\r
- sizeof (PciConfigurationHeader) / sizeof (UINT16),\r
- &PciConfigurationHeader\r
- );\r
- if (EFI_ERROR (Status)) {\r
- return;\r
- }\r
-\r
- Attributes = RootBridge->Attributes;\r
-\r
- //\r
- // Look for devices with the VGA Palette Snoop enabled in the COMMAND register of the PCI Config Header\r
- //\r
- if (PciConfigurationHeader.Hdr.Command & 0x20) {\r
- Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO;\r
- }\r
-\r
- //\r
- // If the device is a PCI-PCI Bridge, then look at the Subordinate Bus Number\r
- //\r
- if (IS_PCI_BRIDGE(&PciConfigurationHeader)) {\r
- //\r
- // Look at the PPB Configuration for legacy decoding attributes\r
- //\r
- if (PciConfigurationHeader.Bridge.BridgeControl & 0x04) {\r
- Attributes |= EFI_PCI_ATTRIBUTE_ISA_IO;\r
- Attributes |= EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO;\r
- }\r
- if (PciConfigurationHeader.Bridge.BridgeControl & 0x08) {\r
- Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO;\r
- Attributes |= EFI_PCI_ATTRIBUTE_VGA_MEMORY;\r
- Attributes |= EFI_PCI_ATTRIBUTE_VGA_IO;\r
- }\r
- } else {\r
- //\r
- // See if the PCI device is an IDE controller\r
- //\r
- if (PciConfigurationHeader.Hdr.ClassCode[2] == 0x01 &&\r
- PciConfigurationHeader.Hdr.ClassCode[1] == 0x01 ) {\r
- if (PciConfigurationHeader.Hdr.ClassCode[0] & 0x80) {\r
- Attributes |= EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO;\r
- Attributes |= EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO;\r
- }\r
- if (PciConfigurationHeader.Hdr.ClassCode[0] & 0x01) {\r
- Attributes |= EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO;\r
- }\r
- if (PciConfigurationHeader.Hdr.ClassCode[0] & 0x04) {\r
- Attributes |= EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO;\r
- }\r
- }\r
-\r
- //\r
- // See if the PCI device is a legacy VGA controller\r
- //\r
- if (PciConfigurationHeader.Hdr.ClassCode[2] == 0x00 &&\r
- PciConfigurationHeader.Hdr.ClassCode[1] == 0x01 ) {\r
- Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO;\r
- Attributes |= EFI_PCI_ATTRIBUTE_VGA_MEMORY;\r
- Attributes |= EFI_PCI_ATTRIBUTE_VGA_IO;\r
- }\r
-\r
- //\r
- // See if the PCI device is a standard VGA controller\r
- //\r
- if (PciConfigurationHeader.Hdr.ClassCode[2] == 0x03 &&\r
- PciConfigurationHeader.Hdr.ClassCode[1] == 0x00 ) {\r
- Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO;\r
- Attributes |= EFI_PCI_ATTRIBUTE_VGA_MEMORY;\r
- Attributes |= EFI_PCI_ATTRIBUTE_VGA_IO;\r
- }\r
- }\r
-\r
- RootBridge->Attributes = Attributes;\r
- RootBridge->Supports = Attributes;\r
-}\r
-\r
/**\r
Provides the hooks from the PCI bus driver to every PCI controller (device/function) at various\r
stages of the PCI enumeration process that allow the host bridge driver to preinitialize individual\r
EFI_STATUS\r
EFIAPI\r
PreprocessController (\r
- IN struct _EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
IN EFI_HANDLE RootBridgeHandle,\r
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress,\r
IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase\r
while (List != &HostBridgeInstance->Head) {\r
RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);\r
if (RootBridgeHandle == RootBridgeInstance->Handle) {\r
- UpdateRootBridgeAttributes (\r
- RootBridgeInstance,\r
- PciAddress\r
- );\r
- return EFI_SUCCESS;\r
+ break;\r
}\r
List = List->ForwardLink;\r
}\r
+ if (List == &HostBridgeInstance->Head) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
\r
- return EFI_INVALID_PARAMETER;\r
+ if (Phase < EfiPciBeforeChildBusEnumeration || Phase > EfiPciBeforeResourceCollection) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ return EFI_SUCCESS;\r
}\r
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