PcAtChipsetPkg/PciHostBridgeDxe: fix typo in "aperture"

[mirror_edk2.git] / PcAtChipsetPkg / PciHostBridgeDxe / PciRootBridgeIo.c

diff --git a/PcAtChipsetPkg/PciHostBridgeDxe/PciRootBridgeIo.c b/PcAtChipsetPkg/PciHostBridgeDxe/PciRootBridgeIo.c
index 7946324d9f674525c5e098c43288ac21adcca8be..c7d9f06fb02162372a9cb47e001ad0d4b9385c9c 100644 (file)
--- a/PcAtChipsetPkg/PciHostBridgeDxe/PciRootBridgeIo.c
+++ b/PcAtChipsetPkg/PciHostBridgeDxe/PciRootBridgeIo.c
@@ -621,7 +621,7 @@ UINT8 mOutStride[] = {
   @param Protocol         Point to protocol instance\r
   @param HostBridgeHandle Handle of host bridge\r
   @param Attri            Attribute of host bridge\r
-  @param ResAppeture      ResourceAppeture for host bridge\r
+  @param ResAperture      ResourceAperture for host bridge\r
 \r
   @retval EFI_SUCCESS Success to initialize the Pci Root Bridge.\r
 \r
@@ -631,7 +631,7 @@ RootBridgeConstructor (
   IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL    *Protocol,\r
   IN EFI_HANDLE                         HostBridgeHandle,\r
   IN UINT64                             Attri,\r
-  IN PCI_ROOT_BRIDGE_RESOURCE_APPETURE  *ResAppeture\r
+  IN PCI_ROOT_BRIDGE_RESOURCE_APERTURE  *ResAperture\r
   )\r
 {\r
   EFI_STATUS                        Status;\r
@@ -644,21 +644,21 @@ RootBridgeConstructor (
   // The host to pci bridge, the host memory and io addresses are\r
   // direct mapped to pci addresses, so no need translate, set bases to 0.\r
   //\r
-  PrivateData->MemBase = ResAppeture->MemBase;\r
-  PrivateData->IoBase  = ResAppeture->IoBase;\r
+  PrivateData->MemBase = ResAperture->MemBase;\r
+  PrivateData->IoBase  = ResAperture->IoBase;\r
 \r
   //\r
   // The host bridge only supports 32bit addressing for memory\r
   // and standard IA32 16bit io\r
   //\r
-  PrivateData->MemLimit = ResAppeture->MemLimit;\r
-  PrivateData->IoLimit  = ResAppeture->IoLimit;\r
+  PrivateData->MemLimit = ResAperture->MemLimit;\r
+  PrivateData->IoLimit  = ResAperture->IoLimit;\r
 \r
   //\r
-  // Bus Appeture for this Root Bridge (Possible Range)\r
+  // Bus Aperture for this Root Bridge (Possible Range)\r
   //\r
-  PrivateData->BusBase  = ResAppeture->BusBase;\r
-  PrivateData->BusLimit = ResAppeture->BusLimit;\r
+  PrivateData->BusBase  = ResAperture->BusBase;\r
+  PrivateData->BusLimit = ResAperture->BusLimit;\r
   \r
   //\r
   // Specific for this chipset\r