--- /dev/null
+/** @file\r
+PlatformHelperLib function prototype definitions.\r
+\r
+Copyright (c) 2013 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#ifndef __PLATFORM_HELPER_LIB_H__\r
+#define __PLATFORM_HELPER_LIB_H__\r
+\r
+#include "Platform.h"\r
+\r
+//\r
+// Function prototypes for routines exported by this library.\r
+//\r
+\r
+/**\r
+ Find pointer to RAW data in Firmware volume file.\r
+\r
+ @param FvNameGuid Firmware volume to search. If == NULL search all.\r
+ @param FileNameGuid Firmware volume file to search for.\r
+ @param SectionData Pointer to RAW data section of found file.\r
+ @param SectionDataSize Pointer to UNITN to get size of RAW data.\r
+\r
+ @retval EFI_SUCCESS Raw Data found.\r
+ @retval EFI_INVALID_PARAMETER FileNameGuid == NULL.\r
+ @retval EFI_NOT_FOUND Firmware volume file not found.\r
+ @retval EFI_UNSUPPORTED Unsupported in current enviroment (PEI or DXE).\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+PlatformFindFvFileRawDataSection (\r
+ IN CONST EFI_GUID *FvNameGuid OPTIONAL,\r
+ IN CONST EFI_GUID *FileNameGuid,\r
+ OUT VOID **SectionData,\r
+ OUT UINTN *SectionDataSize\r
+ );\r
+\r
+/**\r
+ Read 8bit character from debug stream.\r
+\r
+ Block until character is read.\r
+\r
+ @return 8bit character read from debug stream.\r
+\r
+**/\r
+CHAR8\r
+EFIAPI\r
+PlatformDebugPortGetChar8 (\r
+ VOID\r
+ );\r
+\r
+/**\r
+ Find free spi protect register and write to it to protect a flash region.\r
+\r
+ @param DirectValue Value to directly write to register.\r
+ if DirectValue == 0 the use Base & Length below.\r
+ @param BaseAddress Base address of region in Flash Memory Map.\r
+ @param Length Length of region to protect.\r
+\r
+ @retval EFI_SUCCESS Free spi protect register found & written.\r
+ @retval EFI_NOT_FOUND Free Spi protect register not found.\r
+ @retval EFI_DEVICE_ERROR Unable to write to spi protect register.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+PlatformWriteFirstFreeSpiProtect (\r
+ IN CONST UINT32 DirectValue,\r
+ IN CONST UINT32 BaseAddress,\r
+ IN CONST UINT32 Length\r
+ );\r
+\r
+/**\r
+ Lock legacy SPI static configuration information.\r
+\r
+ Function will assert if unable to lock config.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+PlatformFlashLockConfig (\r
+ VOID\r
+ );\r
+\r
+/**\r
+ Lock regions and config of SPI flash given the policy for this platform.\r
+\r
+ Function will assert if unable to lock regions or config.\r
+\r
+ @param PreBootPolicy If TRUE do Pre Boot Flash Lock Policy.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+PlatformFlashLockPolicy (\r
+ IN CONST BOOLEAN PreBootPolicy\r
+ );\r
+\r
+/**\r
+ Erase and Write to platform flash.\r
+\r
+ Routine accesses one flash block at a time, each access consists\r
+ of an erase followed by a write of FLASH_BLOCK_SIZE. One or both\r
+ of DoErase & DoWrite params must be TRUE.\r
+\r
+ Limitations:-\r
+ CpuWriteAddress must be aligned to FLASH_BLOCK_SIZE.\r
+ DataSize must be a multiple of FLASH_BLOCK_SIZE.\r
+\r
+ @param Smst If != NULL then InSmm and use to locate\r
+ SpiProtocol.\r
+ @param CpuWriteAddress Address in CPU memory map of flash region.\r
+ @param Data The buffer containing the data to be written.\r
+ @param DataSize Amount of data to write.\r
+ @param DoErase Earse each block.\r
+ @param DoWrite Write to each block.\r
+\r
+ @retval EFI_SUCCESS Operation successful.\r
+ @retval EFI_NOT_READY Required resources not setup.\r
+ @retval EFI_INVALID_PARAMETER Invalid parameter.\r
+ @retval Others Unexpected error happened.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+PlatformFlashEraseWrite (\r
+ IN VOID *Smst,\r
+ IN UINTN CpuWriteAddress,\r
+ IN UINT8 *Data,\r
+ IN UINTN DataSize,\r
+ IN BOOLEAN DoErase,\r
+ IN BOOLEAN DoWrite\r
+ );\r
+\r
+/** Check if System booted with recovery Boot Stage1 image.\r
+\r
+ @retval TRUE If system booted with recovery Boot Stage1 image.\r
+ @retval FALSE If system booted with normal stage1 image.\r
+\r
+**/\r
+BOOLEAN\r
+EFIAPI\r
+PlatformIsBootWithRecoveryStage1 (\r
+ VOID\r
+ );\r
+\r
+/**\r
+ Clear SPI Protect registers.\r
+\r
+ @retval EFI_SUCESS SPI protect registers cleared.\r
+ @retval EFI_ACCESS_DENIED Unable to clear SPI protect registers.\r
+**/\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+PlatformClearSpiProtect (\r
+ VOID\r
+ );\r
+\r
+/**\r
+ Determine if an SPI address range is protected.\r
+\r
+ @param SpiBaseAddress Base of SPI range.\r
+ @param Length Length of SPI range.\r
+\r
+ @retval TRUE Range is protected.\r
+ @retval FALSE Range is not protected.\r
+**/\r
+BOOLEAN\r
+EFIAPI\r
+PlatformIsSpiRangeProtected (\r
+ IN CONST UINT32 SpiBaseAddress,\r
+ IN CONST UINT32 Length\r
+ );\r
+\r
+/**\r
+ Set Legacy GPIO Level\r
+\r
+ @param LevelRegOffset GPIO level register Offset from GPIO Base Address.\r
+ @param GpioNum GPIO bit to change.\r
+ @param HighLevel If TRUE set GPIO High else Set GPIO low.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+PlatformLegacyGpioSetLevel (\r
+ IN CONST UINT32 LevelRegOffset,\r
+ IN CONST UINT32 GpioNum,\r
+ IN CONST BOOLEAN HighLevel\r
+ );\r
+\r
+/**\r
+ Get Legacy GPIO Level\r
+\r
+ @param LevelRegOffset GPIO level register Offset from GPIO Base Address.\r
+ @param GpioNum GPIO bit to check.\r
+\r
+ @retval TRUE If bit is SET.\r
+ @retval FALSE If bit is CLEAR.\r
+\r
+**/\r
+BOOLEAN\r
+EFIAPI\r
+PlatformLegacyGpioGetLevel (\r
+ IN CONST UINT32 LevelRegOffset,\r
+ IN CONST UINT32 GpioNum\r
+ );\r
+\r
+/**\r
+ Set the direction of Pcal9555 IO Expander GPIO pin.\r
+\r
+ @param Pcal9555SlaveAddr I2c Slave address of Pcal9555 Io Expander.\r
+ @param GpioNum Gpio direction to configure - values 0-7 for Port0\r
+ and 8-15 for Port1.\r
+ @param CfgAsInput If TRUE set pin direction as input else set as output.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+PlatformPcal9555GpioSetDir (\r
+ IN CONST UINT32 Pcal9555SlaveAddr,\r
+ IN CONST UINT32 GpioNum,\r
+ IN CONST BOOLEAN CfgAsInput\r
+ );\r
+\r
+/**\r
+ Set the level of Pcal9555 IO Expander GPIO high or low.\r
+\r
+ @param Pcal9555SlaveAddr I2c Slave address of Pcal9555 Io Expander.\r
+ @param GpioNum Gpio to change values 0-7 for Port0 and 8-15\r
+ for Port1.\r
+ @param HighLevel If TRUE set pin high else set pin low.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+PlatformPcal9555GpioSetLevel (\r
+ IN CONST UINT32 Pcal9555SlaveAddr,\r
+ IN CONST UINT32 GpioNum,\r
+ IN CONST BOOLEAN HighLevel\r
+ );\r
+\r
+/**\r
+\r
+ Enable pull-up/pull-down resistors of Pcal9555 GPIOs.\r
+\r
+ @param Pcal9555SlaveAddr I2c Slave address of Pcal9555 Io Expander.\r
+ @param GpioNum Gpio to change values 0-7 for Port0 and 8-15\r
+ for Port1.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+PlatformPcal9555GpioEnablePull (\r
+ IN CONST UINT32 Pcal9555SlaveAddr,\r
+ IN CONST UINT32 GpioNum\r
+ );\r
+\r
+/**\r
+\r
+ Disable pull-up/pull-down resistors of Pcal9555 GPIOs.\r
+\r
+ @param Pcal9555SlaveAddr I2c Slave address of Pcal9555 Io Expander.\r
+ @param GpioNum Gpio to change values 0-7 for Port0 and 8-15\r
+ for Port1.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+PlatformPcal9555GpioDisablePull (\r
+ IN CONST UINT32 Pcal9555SlaveAddr,\r
+ IN CONST UINT32 GpioNum\r
+ );\r
+\r
+BOOLEAN\r
+EFIAPI\r
+PlatformPcal9555GpioGetState (\r
+ IN CONST UINT32 Pcal9555SlaveAddr,\r
+ IN CONST UINT32 GpioNum\r
+ );\r
+\r
+/**\r
+ Init platform LEDs into known state.\r
+\r
+ @param PlatformType Executing platform type.\r
+\r
+ @retval EFI_SUCCESS Operation success.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+PlatformLedInit (\r
+ IN CONST EFI_PLATFORM_TYPE Type\r
+ );\r
+\r
+/**\r
+ Turn on or off platform flash update LED.\r
+\r
+ @param PlatformType Executing platform type.\r
+ @param TurnOn If TRUE turn on else turn off.\r
+\r
+ @retval EFI_SUCCESS Operation success.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+PlatformFlashUpdateLed (\r
+ IN CONST EFI_PLATFORM_TYPE Type,\r
+ IN CONST BOOLEAN TurnOn\r
+ );\r
+\r
+#endif // #ifndef __PLATFORM_HELPER_LIB_H__\r
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