QuarkSocPkg: Add new package for Quark SoC X1000

[mirror_edk2.git] / QuarkSocPkg / QuarkNorthCluster / Include / Library / QNCAccessLib.h

diff --git a/QuarkSocPkg/QuarkNorthCluster/Include/Library/QNCAccessLib.h b/QuarkSocPkg/QuarkNorthCluster/Include/Library/QNCAccessLib.h
new file mode 100644 (file)
index 0000000..4496167
--- /dev/null
+++ b/QuarkSocPkg/QuarkNorthCluster/Include/Library/QNCAccessLib.h
@@ -0,0 +1,167 @@
+/** @file\r
+Library functions for Setting QNC internal network port\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution.  The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#ifndef __QNC_ACCESS_LIB_H__\r
+#define __QNC_ACCESS_LIB_H__\r
+\r
+#include <IntelQNCRegs.h>\r
+\r
+#define MESSAGE_READ_DW(Port, Reg)  \\r
+        (UINT32)((QUARK_OPCODE_READ << QNC_MCR_OP_OFFSET) | ((Port << QNC_MCR_PORT_OFFSET) & 0xFF0000) | ((Reg << QNC_MCR_REG_OFFSET) & 0xFF00) | 0xF0)\r
+\r
+#define MESSAGE_WRITE_DW(Port, Reg)  \\r
+        (UINT32)((QUARK_OPCODE_WRITE << QNC_MCR_OP_OFFSET) | ((Port << QNC_MCR_PORT_OFFSET) & 0xFF0000) | ((Reg << QNC_MCR_REG_OFFSET) & 0xFF00) | 0xF0)\r
+\r
+#define ALT_MESSAGE_READ_DW(Port, Reg)  \\r
+        (UINT32)((QUARK_ALT_OPCODE_READ << QNC_MCR_OP_OFFSET) | ((Port << QNC_MCR_PORT_OFFSET) & 0xFF0000) | ((Reg << QNC_MCR_REG_OFFSET) & 0xFF00) | 0xF0)\r
+\r
+#define ALT_MESSAGE_WRITE_DW(Port, Reg)  \\r
+        (UINT32)((QUARK_ALT_OPCODE_WRITE << QNC_MCR_OP_OFFSET) | ((Port << QNC_MCR_PORT_OFFSET) & 0xFF0000) | ((Reg << QNC_MCR_REG_OFFSET) & 0xFF00) | 0xF0)\r
+\r
+#define MESSAGE_IO_READ_DW(Port, Reg)  \\r
+        (UINT32)((QUARK_OPCODE_IO_READ << QNC_MCR_OP_OFFSET) | ((Port << QNC_MCR_PORT_OFFSET) & 0xFF0000) | ((Reg << QNC_MCR_REG_OFFSET) & 0xFF00) | 0xF0)\r
+\r
+#define MESSAGE_IO_WRITE_DW(Port, Reg)  \\r
+        (UINT32)((QUARK_OPCODE_IO_WRITE << QNC_MCR_OP_OFFSET) | ((Port << QNC_MCR_PORT_OFFSET) & 0xFF0000) | ((Reg << QNC_MCR_REG_OFFSET) & 0xFF00) | 0xF0)\r
+\r
+#define MESSAGE_SHADOW_DW(Port, Reg)  \\r
+        (UINT32)((QUARK_DRAM_BASE_ADDR_READY << QNC_MCR_OP_OFFSET) | ((Port << QNC_MCR_PORT_OFFSET) & 0xFF0000) | ((Reg << QNC_MCR_REG_OFFSET) & 0xFF00) | 0xF0)\r
+\r
+\r
+/**\r
+  Read required data from QNC internal message network\r
+**/\r
+UINT32\r
+EFIAPI\r
+QNCPortRead(\r
+  UINT8 Port,\r
+  UINT32 RegAddress\r
+  );\r
+\r
+/**\r
+  Write prepared data into QNC internal message network.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+QNCPortWrite (\r
+  UINT8 Port,\r
+  UINT32 RegAddress,\r
+  UINT32 WriteValue\r
+  );\r
+\r
+/**\r
+  Read required data from QNC internal message network\r
+**/\r
+UINT32\r
+EFIAPI\r
+QNCAltPortRead(\r
+  UINT8 Port,\r
+  UINT32 RegAddress\r
+  );\r
+\r
+/**\r
+  Write prepared data into QNC internal message network.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+QNCAltPortWrite (\r
+  UINT8 Port,\r
+  UINT32 RegAddress,\r
+  UINT32 WriteValue\r
+  );\r
+\r
+/**\r
+  Read required data from QNC internal message network\r
+**/\r
+UINT32\r
+EFIAPI\r
+QNCPortIORead(\r
+  UINT8 Port,\r
+  UINT32 RegAddress\r
+  );\r
+\r
+/**\r
+  Write prepared data into QNC internal message network.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+QNCPortIOWrite (\r
+  UINT8 Port,\r
+  UINT32 RegAddress,\r
+  UINT32 WriteValue\r
+  );\r
+\r
+/**\r
+  This is for the special consideration for QNC MMIO write, as required by FWG,\r
+  a reading must be performed after MMIO writing to ensure the expected write\r
+  is processed and data is flushed into chipset\r
+\r
+**/\r
+RETURN_STATUS\r
+EFIAPI\r
+QNCMmIoWrite (\r
+  UINT32             MmIoAddress,\r
+  QNC_MEM_IO_WIDTH    Width,\r
+  UINT32             DataNumber,\r
+  VOID               *pData\r
+  );\r
+\r
+UINT32\r
+EFIAPI\r
+QncHsmmcRead (\r
+  VOID\r
+  );\r
+\r
+VOID\r
+EFIAPI\r
+QncHsmmcWrite (\r
+  UINT32 WriteValue\r
+  );\r
+\r
+VOID\r
+EFIAPI\r
+QncImrWrite (\r
+  UINT32 ImrBaseOffset,\r
+  UINT32 ImrLow,\r
+  UINT32 ImrHigh,\r
+  UINT32 ImrReadMask,\r
+  UINT32 ImrWriteMask\r
+  );\r
+\r
+VOID\r
+EFIAPI\r
+QncIClkAndThenOr (\r
+  UINT32 RegAddress,\r
+  UINT32 AndValue,\r
+  UINT32 OrValue\r
+  );\r
+\r
+VOID\r
+EFIAPI\r
+QncIClkOr (\r
+  UINT32 RegAddress,\r
+  UINT32 OrValue\r
+  );\r
+\r
+UINTN\r
+EFIAPI\r
+QncGetPciExpressBaseAddress (\r
+  VOID\r
+  );\r
+\r
+#endif\r