--- /dev/null
+/** @file\r
+This file defines the EFI SPI Protocol which implements the\r
+Intel(R) ICH SPI Host Controller Compatibility Interface.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+**/\r
+#ifndef _SPI_H_\r
+#define _SPI_H_\r
+\r
+//\r
+// Define the SPI protocol GUID\r
+//\r
+// EDK and EDKII have different GUID formats\r
+//\r
+#if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000)\r
+#define EFI_SPI_PROTOCOL_GUID \\r
+ { \\r
+ 0x1156efc6, 0xea32, 0x4396, 0xb5, 0xd5, 0x26, 0x93, 0x2e, 0x83, 0xc3, 0x13 \\r
+ }\r
+#define EFI_SMM_SPI_PROTOCOL_GUID \\r
+ { \\r
+ 0xD9072C35, 0xEB8F, 0x43ad, 0xA2, 0x20, 0x34, 0xD4, 0x0E, 0x2A, 0x82, 0x85 \\r
+ }\r
+#else\r
+#define EFI_SPI_PROTOCOL_GUID \\r
+ { \\r
+ 0x1156efc6, 0xea32, 0x4396, \\r
+ { \\r
+ 0xb5, 0xd5, 0x26, 0x93, 0x2e, 0x83, 0xc3, 0x13 \\r
+ } \\r
+ }\r
+#define EFI_SMM_SPI_PROTOCOL_GUID \\r
+ { \\r
+ 0xD9072C35, 0xEB8F, 0x43ad, \\r
+ { \\r
+ 0xA2, 0x20, 0x34, 0xD4, 0x0E, 0x2A, 0x82, 0x85 \\r
+ } \\r
+ }\r
+#endif\r
+//\r
+// Extern the GUID for protocol users.\r
+//\r
+extern EFI_GUID gEfiSpiProtocolGuid;\r
+extern EFI_GUID gEfiSmmSpiProtocolGuid;\r
+\r
+//\r
+// Forward reference for ANSI C compatibility\r
+//\r
+typedef struct _EFI_SPI_PROTOCOL EFI_SPI_PROTOCOL;\r
+\r
+//\r
+// SPI protocol data structures and definitions\r
+//\r
+//\r
+// Number of Prefix Opcodes allowed on the SPI interface\r
+//\r
+#define SPI_NUM_PREFIX_OPCODE 2\r
+\r
+//\r
+// Number of Opcodes in the Opcode Menu\r
+//\r
+#define SPI_NUM_OPCODE 8\r
+\r
+#ifdef SERVER_BIOS_FLAG\r
+//\r
+// SPI default opcode slots\r
+//\r
+#define SPI_OPCODE_JEDEC_ID_INDEX 0\r
+#endif // SERVER_BIOS_FLAG\r
+\r
+//\r
+// Opcode Type\r
+// EnumSpiOpcodeCommand: Command without address\r
+// EnumSpiOpcodeRead: Read with address\r
+// EnumSpiOpcodeWrite: Write with address\r
+//\r
+typedef enum {\r
+ EnumSpiOpcodeReadNoAddr,\r
+ EnumSpiOpcodeWriteNoAddr,\r
+ EnumSpiOpcodeRead,\r
+ EnumSpiOpcodeWrite,\r
+ EnumSpiOpcodeMax\r
+} SPI_OPCODE_TYPE;\r
+\r
+typedef enum {\r
+ EnumSpiCycle20MHz,\r
+ EnumSpiCycle33MHz,\r
+ EnumSpiCycle66MHz, // not supported by PCH\r
+ EnumSpiCycle50MHz,\r
+ EnumSpiCycleMax\r
+} SPI_CYCLE_FREQUENCY;\r
+\r
+typedef enum {\r
+ EnumSpiRegionAll,\r
+ EnumSpiRegionBios,\r
+ EnumSpiRegionMe,\r
+ EnumSpiRegionGbE,\r
+ EnumSpiRegionDescriptor,\r
+ EnumSpiRegionPlatformData,\r
+ EnumSpiRegionMax\r
+} SPI_REGION_TYPE;\r
+\r
+//\r
+// Hardware Sequencing required operations (as listed in CougarPoint EDS Table 5-55: "Hardware\r
+// Sequencing Commands and Opcode Requirements"\r
+//\r
+typedef enum {\r
+ EnumSpiOperationWriteStatus,\r
+ EnumSpiOperationProgramData_1_Byte,\r
+ EnumSpiOperationProgramData_64_Byte,\r
+ EnumSpiOperationReadData,\r
+ EnumSpiOperationWriteDisable,\r
+ EnumSpiOperationReadStatus,\r
+ EnumSpiOperationWriteEnable,\r
+ EnumSpiOperationFastRead,\r
+ EnumSpiOperationEnableWriteStatus,\r
+ EnumSpiOperationErase_256_Byte,\r
+ EnumSpiOperationErase_4K_Byte,\r
+ EnumSpiOperationErase_8K_Byte,\r
+ EnumSpiOperationErase_64K_Byte,\r
+ EnumSpiOperationFullChipErase,\r
+ EnumSpiOperationJedecId,\r
+ EnumSpiOperationDualOutputFastRead,\r
+ EnumSpiOperationDiscoveryParameters,\r
+ EnumSpiOperationOther,\r
+ EnumSpiOperationMax\r
+} SPI_OPERATION;\r
+\r
+//\r
+// Opcode menu entries\r
+// Type Operation Type (value to be programmed to the OPTYPE register)\r
+// Code The opcode (value to be programmed to the OPMENU register)\r
+// Frequency The expected frequency to be used (value to be programmed to the SSFC\r
+// Register)\r
+// Operation Which Hardware Sequencing required operation this opcode respoinds to.\r
+// The required operations are listed in EDS Table 5-55: "Hardware\r
+// Sequencing Commands and Opcode Requirements"\r
+// If the opcode does not corresponds to any operation listed, use\r
+// EnumSpiOperationOther\r
+//\r
+typedef struct _SPI_OPCODE_MENU_ENTRY {\r
+ SPI_OPCODE_TYPE Type;\r
+ UINT8 Code;\r
+ SPI_CYCLE_FREQUENCY Frequency;\r
+ SPI_OPERATION Operation;\r
+} SPI_OPCODE_MENU_ENTRY;\r
+\r
+//\r
+// Initialization data table loaded to the SPI host controller\r
+// VendorId Vendor ID of the SPI device\r
+// DeviceId0 Device ID0 of the SPI device\r
+// DeviceId1 Device ID1 of the SPI device\r
+// PrefixOpcode Prefix opcodes which are loaded into the SPI host controller\r
+// OpcodeMenu Opcodes which are loaded into the SPI host controller Opcode Menu\r
+// BiosStartOffset The offset of the start of the BIOS image relative to the flash device.\r
+// Please note this is a Flash Linear Address, NOT a memory space address.\r
+// This value is platform specific and depends on the system flash map.\r
+// This value is only used on non Descriptor mode.\r
+// BiosSize The the BIOS Image size in flash. This value is platform specific\r
+// and depends on the system flash map. Please note BIOS Image size may\r
+// be smaller than BIOS Region size (in Descriptor Mode) or the flash size\r
+// (in Non Descriptor Mode), and in this case, BIOS Image is supposed to be\r
+// placed at the top end of the BIOS Region (in Descriptor Mode) or the flash\r
+// (in Non Descriptor Mode)\r
+//\r
+typedef struct _SPI_INIT_TABLE {\r
+ UINT8 VendorId;\r
+ UINT8 DeviceId0;\r
+ UINT8 DeviceId1;\r
+ UINT8 PrefixOpcode[SPI_NUM_PREFIX_OPCODE];\r
+ SPI_OPCODE_MENU_ENTRY OpcodeMenu[SPI_NUM_OPCODE];\r
+ UINTN BiosStartOffset;\r
+ UINTN BiosSize;\r
+} SPI_INIT_TABLE;\r
+\r
+//\r
+// Public Info struct to show current initialized state of the spi interface.\r
+// OpcodeIndex must be less then SPI_NUM_OPCODE for operation to be supported.\r
+//\r
+typedef struct _SPI_INIT_INFO {\r
+ SPI_INIT_TABLE *InitTable;\r
+ UINT8 JedecIdOpcodeIndex;\r
+ UINT8 OtherOpcodeIndex;\r
+ UINT8 WriteStatusOpcodeIndex;\r
+ UINT8 ProgramOpcodeIndex;\r
+ UINT8 ReadOpcodeIndex;\r
+ UINT8 EraseOpcodeIndex;\r
+ UINT8 ReadStatusOpcodeIndex;\r
+ UINT8 FullChipEraseOpcodeIndex;\r
+} SPI_INIT_INFO;\r
+\r
+//\r
+// Protocol member functions\r
+//\r
+\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_SPI_INIT) (\r
+ IN EFI_SPI_PROTOCOL * This,\r
+ IN SPI_INIT_TABLE * InitTable\r
+ );\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ Initializes the host controller to execute SPI commands.\r
+\r
+Arguments:\r
+\r
+ This Pointer to the EFI_SPI_PROTOCOL instance.\r
+ InitTable Pointer to caller-allocated buffer containing the SPI\r
+ interface initialization table.\r
+\r
+Returns:\r
+\r
+ EFI_SUCCESS Opcode initialization on the SPI host controller completed.\r
+ EFI_ACCESS_DENIED The SPI configuration interface is locked.\r
+ EFI_OUT_OF_RESOURCES Not enough resource available to initialize the device.\r
+ EFI_DEVICE_ERROR Device error, operation failed.\r
+\r
+--*/\r
+\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_SPI_LOCK) (\r
+ IN EFI_SPI_PROTOCOL * This\r
+ );\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ Lock the SPI Static Configuration Interface.\r
+ Once locked, the interface is no longer open for configuration changes.\r
+ The lock state automatically clears on next system reset.\r
+\r
+Arguments:\r
+\r
+ This Pointer to the EFI_SPI_PROTOCOL instance.\r
+\r
+Returns:\r
+\r
+ EFI_SUCCESS Lock operation succeed.\r
+ EFI_DEVICE_ERROR Device error, operation failed.\r
+ EFI_ACCESS_DENIED The interface has already been locked.\r
+\r
+--*/\r
+\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_SPI_EXECUTE) (\r
+ IN EFI_SPI_PROTOCOL * This,\r
+ IN UINT8 OpcodeIndex,\r
+ IN UINT8 PrefixOpcodeIndex,\r
+ IN BOOLEAN DataCycle,\r
+ IN BOOLEAN Atomic,\r
+ IN BOOLEAN ShiftOut,\r
+ IN UINTN Address,\r
+ IN UINT32 DataByteCount,\r
+ IN OUT UINT8 *Buffer,\r
+ IN SPI_REGION_TYPE SpiRegionType\r
+ );\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ Execute SPI commands from the host controller.\r
+\r
+Arguments:\r
+\r
+ This Pointer to the EFI_SPI_PROTOCOL instance.\r
+ OpcodeIndex Index of the command in the OpCode Menu.\r
+ PrefixOpcodeIndex Index of the first command to run when in an atomic cycle sequence.\r
+ DataCycle TRUE if the SPI cycle contains data\r
+ Atomic TRUE if the SPI cycle is atomic and interleave cycles are not allowed.\r
+ ShiftOut If DataByteCount is not zero, TRUE to shift data out and FALSE to shift data in.\r
+ Address In Descriptor Mode, for Descriptor Region, GbE Region, ME Region and Platform\r
+ Region, this value specifies the offset from the Region Base; for BIOS Region,\r
+ this value specifies the offset from the start of the BIOS Image. In Non\r
+ Descriptor Mode, this value specifies the offset from the start of the BIOS Image.\r
+ Please note BIOS Image size may be smaller than BIOS Region size (in Descriptor\r
+ Mode) or the flash size (in Non Descriptor Mode), and in this case, BIOS Image is\r
+ supposed to be placed at the top end of the BIOS Region (in Descriptor Mode) or\r
+ the flash (in Non Descriptor Mode)\r
+ DataByteCount Number of bytes in the data portion of the SPI cycle.\r
+ Buffer Pointer to caller-allocated buffer containing the dada received or sent during the SPI cycle.\r
+ SpiRegionType SPI Region type. Values EnumSpiRegionBios, EnumSpiRegionGbE, EnumSpiRegionMe,\r
+ EnumSpiRegionDescriptor, and EnumSpiRegionPlatformData are only applicable in\r
+ Descriptor mode. Value EnumSpiRegionAll is applicable to both Descriptor Mode\r
+ and Non Descriptor Mode, which indicates "SpiRegionOffset" is actually relative\r
+ to base of the 1st flash device (i.e., it is a Flash Linear Address).\r
+\r
+Returns:\r
+\r
+ EFI_SUCCESS Command succeed.\r
+ EFI_INVALID_PARAMETER The parameters specified are not valid.\r
+ EFI_UNSUPPORTED Command not supported.\r
+ EFI_DEVICE_ERROR Device error, command aborts abnormally.\r
+\r
+--*/\r
+\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_SPI_INFO) (\r
+ IN EFI_SPI_PROTOCOL *This,\r
+ OUT SPI_INIT_INFO **InitInfoPtr\r
+ );\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ Return info about SPI host controller, to help callers usage of Execute\r
+ service.\r
+\r
+ If 0xff is returned as an opcode index in init info struct\r
+ then device does not support the operation.\r
+\r
+Arguments:\r
+\r
+ This Pointer to the EFI_SPI_PROTOCOL instance.\r
+ InitInfoPtr Pointer to init info written to this memory location.\r
+\r
+Returns:\r
+\r
+ EFI_SUCCESS Information returned.\r
+ EFI_INVALID_PARAMETER Invalid parameter.\r
+ EFI_NOT_READY Required resources not setup.\r
+ Others Unexpected error happened.\r
+\r
+--*/\r
+\r
+//\r
+// Protocol definition\r
+//\r
+struct _EFI_SPI_PROTOCOL {\r
+ EFI_SPI_INIT Init;\r
+ EFI_SPI_LOCK Lock;\r
+ EFI_SPI_EXECUTE Execute;\r
+ EFI_SPI_INFO Info;\r
+};\r
+\r
+#endif\r
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