+++ /dev/null
-/** @file\r
-Lib function for Pei QNC.\r
-\r
-Copyright (c) 2013-2015 Intel Corporation.\r
-\r
-SPDX-License-Identifier: BSD-2-Clause-Patent\r
-\r
-**/\r
-#include "CommonHeader.h"\r
-\r
-/**\r
- This function provides the necessary SOC initialization\r
- before MRC running. It sets RCBA, GPIO, PMBASE\r
- and some parts of SOC through SOC message method.\r
- If the function cannot complete it'll ASSERT().\r
-**/\r
-VOID\r
-EFIAPI\r
-PeiQNCPreMemInit (\r
- VOID\r
- )\r
-{\r
- UINT32 RegValue;\r
-\r
- // QNCPortWrite(Port#, Offset, Value)\r
-\r
- //\r
- // Set the fixed PRI Status encodings config.\r
- //\r
- QNCPortWrite (\r
- QUARK_NC_MEMORY_ARBITER_SB_PORT_ID,\r
- QUARK_NC_MEMORY_ARBITER_REG_ASTATUS,\r
- QNC_FIXED_CONFIG_ASTATUS\r
- );\r
-\r
- // Sideband register write to Remote Management Unit\r
- QNCPortWrite (QUARK_NC_RMU_SB_PORT_ID, QNC_MSG_TMPM_REG_PMBA, (BIT31 | PcdGet16 (PcdPmbaIoBaseAddress)));\r
-\r
- // Configurable I/O address in iLB (legacy block)\r
-\r
- LpcPciCfg32 (R_QNC_LPC_SMBUS_BASE) = BIT31 | PcdGet16 (PcdSmbaIoBaseAddress);\r
- LpcPciCfg32 (R_QNC_LPC_GBA_BASE) = BIT31 | PcdGet16 (PcdGbaIoBaseAddress);\r
- LpcPciCfg32 (R_QNC_LPC_PM1BLK) = BIT31 | PcdGet16 (PcdPm1blkIoBaseAddress);\r
- LpcPciCfg32 (R_QNC_LPC_GPE0BLK) = BIT31 | PcdGet16 (PcdGpe0blkIoBaseAddress);\r
- LpcPciCfg32 (R_QNC_LPC_WDTBA) = BIT31 | PcdGet16 (PcdWdtbaIoBaseAddress);\r
-\r
- //\r
- // Program RCBA Base Address\r
- //\r
- LpcPciCfg32AndThenOr (R_QNC_LPC_RCBA, (~B_QNC_LPC_RCBA_MASK), (((UINT32)(PcdGet64 (PcdRcbaMmioBaseAddress))) | B_QNC_LPC_RCBA_EN));\r
-\r
- //\r
- // Program Memory Manager fixed config values.\r
- //\r
-\r
- RegValue = QNCPortRead (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_BTHCTRL);\r
- RegValue &= ~(DRAM_NON_HOST_RQ_LIMIT_MASK);\r
- RegValue |= (V_DRAM_NON_HOST_RQ_LIMIT << DRAM_NON_HOST_RQ_LIMIT_BP);\r
- QNCPortWrite (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_BTHCTRL, RegValue);\r
-\r
- //\r
- // Program iCLK fixed config values.\r
- //\r
- QncIClkAndThenOr (\r
- QUARK_ICLK_MUXTOP,\r
- (UINT32) ~(B_MUXTOP_FLEX2_MASK | B_MUXTOP_FLEX1_MASK),\r
- (V_MUXTOP_FLEX2 << B_MUXTOP_FLEX2_BP) | (V_MUXTOP_FLEX1 << B_MUXTOP_FLEX1_BP)\r
- );\r
- QncIClkAndThenOr (\r
- QUARK_ICLK_REF2_DBUFF0,\r
- (UINT32) ~(BIT0), // bit[0] cleared\r
- 0\r
- );\r
- QncIClkOr (\r
- QUARK_ICLK_SSC1,\r
- BIT0 // bit[0] set\r
- );\r
- QncIClkOr (\r
- QUARK_ICLK_SSC2,\r
- BIT0 // bit[0] set\r
- );\r
- QncIClkOr (\r
- QUARK_ICLK_SSC3,\r
- BIT0 // bit[0] set\r
- );\r
-\r
- //\r
- // Set RMU DMA disable bit post boot.\r
- //\r
- RegValue = QNCPortRead (QUARK_NC_RMU_SB_PORT_ID, QUARK_NC_RMU_REG_OPTIONS_1);\r
- RegValue |= OPTIONS_1_DMA_DISABLE;\r
- QNCPortWrite (QUARK_NC_RMU_SB_PORT_ID, QUARK_NC_RMU_REG_OPTIONS_1, RegValue);\r
-}\r
-\r
-/**\r
- Do north cluster init which needs to be done AFTER MRC init.\r
-\r
- @param VOID\r
-\r
- @retval VOID\r
-**/\r
-\r
-VOID\r
-EFIAPI\r
-PeiQNCPostMemInit (\r
- VOID\r
- )\r
-{\r
- //\r
- // Program SVID/SID the same as VID/DID for all devices except root ports.\r
- //\r
- QNCMmPci32(0, MC_BUS, MC_DEV, MC_FUN, R_EFI_PCI_SVID) = QNCMmPci32(0, MC_BUS, MC_DEV, MC_FUN, PCI_VENDOR_ID_OFFSET);\r
- QNCMmPci32(0, PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, PCI_FUNCTION_NUMBER_QNC_LPC, R_EFI_PCI_SVID) = QNCMmPci32(0, PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, PCI_FUNCTION_NUMBER_QNC_LPC, PCI_VENDOR_ID_OFFSET);\r
- QNCMmPci32(0, PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_IOSF2AHB_0, PCI_FUNCTION_NUMBER_QNC_IOSF2AHB, R_EFI_PCI_SVID) = QNCMmPci32(0, PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_IOSF2AHB_0, PCI_FUNCTION_NUMBER_QNC_IOSF2AHB, PCI_VENDOR_ID_OFFSET);\r
- QNCMmPci32(0, PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_IOSF2AHB_1, PCI_FUNCTION_NUMBER_QNC_IOSF2AHB, R_EFI_PCI_SVID) = QNCMmPci32(0, PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_IOSF2AHB_1, PCI_FUNCTION_NUMBER_QNC_IOSF2AHB, PCI_VENDOR_ID_OFFSET);\r
- return;\r
-}\r
-\r
-/**\r
- Used to check QNC if it's S3 state. Clear the register state after query.\r
-\r
- @retval TRUE if it's S3 state.\r
- @retval FALSE if it's not S3 state.\r
-\r
-**/\r
-BOOLEAN\r
-EFIAPI\r
-QNCCheckS3AndClearState (\r
- VOID\r
- )\r
-{\r
- BOOLEAN S3WakeEventFound;\r
- UINT16 Pm1Sts;\r
- UINT16 Pm1En;\r
- UINT16 Pm1Cnt;\r
- UINT32 Gpe0Sts;\r
- UINT32 Gpe0En;\r
- UINT32 NewValue;\r
- CHAR8 *EventDescStr;\r
-\r
- S3WakeEventFound = FALSE;\r
- EventDescStr = NULL;\r
-\r
- //\r
- // Read the ACPI registers,\r
- //\r
- Pm1Sts = IoRead16 (PcdGet16 (PcdPm1blkIoBaseAddress) + R_QNC_PM1BLK_PM1S);\r
- Pm1En = IoRead16 (PcdGet16 (PcdPm1blkIoBaseAddress) + R_QNC_PM1BLK_PM1E);\r
- Pm1Cnt = IoRead16 (PcdGet16 (PcdPm1blkIoBaseAddress) + R_QNC_PM1BLK_PM1C);\r
- Gpe0Sts = IoRead32 ((UINT16)(LpcPciCfg32 (R_QNC_LPC_GPE0BLK) & 0xFFFF) + R_QNC_GPE0BLK_GPE0S);\r
- Gpe0En = IoRead32 ((UINT16)(LpcPciCfg32 (R_QNC_LPC_GPE0BLK) & 0xFFFF) + R_QNC_GPE0BLK_GPE0E);\r
-\r
- //\r
- // Clear Power Management 1 Enable Register and\r
- // General Purpost Event 0 Enables Register\r
- //\r
- IoWrite16 (PcdGet16 (PcdPm1blkIoBaseAddress) + R_QNC_PM1BLK_PM1E, 0);\r
- IoWrite32 ((UINT16)(LpcPciCfg32 (R_QNC_LPC_GPE0BLK) & 0xFFFF) + R_QNC_GPE0BLK_GPE0E, 0);\r
-\r
- if ((Pm1Sts & B_QNC_PM1BLK_PM1S_WAKE) != 0 && (Pm1Cnt & B_QNC_PM1BLK_PM1C_SLPTP) == V_S3) {\r
-\r
- //\r
- // Detect the actual WAKE event\r
- //\r
- if ((Pm1Sts & B_QNC_PM1BLK_PM1S_RTC) && (Pm1En & B_QNC_PM1BLK_PM1E_RTC)) {\r
- EventDescStr = "RTC Alarm";\r
- S3WakeEventFound = TRUE;\r
- }\r
- if ((Pm1Sts & B_QNC_PM1BLK_PM1S_PCIEWSTS) && !(Pm1En & B_QNC_PM1BLK_PM1E_PWAKED)) {\r
- EventDescStr = "PCIe WAKE";\r
- S3WakeEventFound = TRUE;\r
- }\r
- if ((Gpe0Sts & B_QNC_GPE0BLK_GPE0S_PCIE) && (Gpe0En & B_QNC_GPE0BLK_GPE0E_PCIE)) {\r
- EventDescStr = "PCIe";\r
- S3WakeEventFound = TRUE;\r
- }\r
- if ((Gpe0Sts & B_QNC_GPE0BLK_GPE0S_GPIO) && (Gpe0En & B_QNC_GPE0BLK_GPE0E_GPIO)) {\r
- EventDescStr = "GPIO";\r
- S3WakeEventFound = TRUE;\r
- }\r
- if ((Gpe0Sts & B_QNC_GPE0BLK_GPE0S_EGPE) && (Gpe0En & B_QNC_GPE0BLK_GPE0E_EGPE)) {\r
- EventDescStr = "Ext. GPE";\r
- S3WakeEventFound = TRUE;\r
- }\r
- if (S3WakeEventFound == FALSE) {\r
- EventDescStr = "Unknown";\r
- }\r
- DEBUG ((EFI_D_INFO, "S3 Wake Event - %a\n", EventDescStr));\r
-\r
- //\r
- // If no Power Button Override event occurs and one enabled wake event occurs,\r
- // just do S3 resume and clear the state.\r
- //\r
- IoWrite16 (PcdGet16 (PcdPm1blkIoBaseAddress) + R_QNC_PM1BLK_PM1C, (Pm1Cnt & (~B_QNC_PM1BLK_PM1C_SLPTP)));\r
-\r
- //\r
- // Set EOS to de Assert SMI\r
- //\r
- IoWrite32 ((UINT16)(LpcPciCfg32 (R_QNC_LPC_GPE0BLK) & 0xFFFF) + R_QNC_GPE0BLK_SMIS, B_QNC_GPE0BLK_SMIS_EOS);\r
-\r
- //\r
- // Enable SMI globally\r
- //\r
- NewValue = QNCPortRead (QUARK_NC_HOST_BRIDGE_SB_PORT_ID, QNC_MSG_FSBIC_REG_HMISC);\r
- NewValue |= SMI_EN;\r
- QNCPortWrite (QUARK_NC_HOST_BRIDGE_SB_PORT_ID, QNC_MSG_FSBIC_REG_HMISC, NewValue);\r
-\r
- return TRUE;\r
- }\r
-\r
- return FALSE;\r
-}\r
-\r
-/**\r
- Used to check QNC if system wakes up from power on reset. Clear the register state after query.\r
-\r
- @retval TRUE if system wakes up from power on reset\r
- @retval FALSE if system does not wake up from power on reset\r
-\r
-**/\r
-BOOLEAN\r
-EFIAPI\r
-QNCCheckPowerOnResetAndClearState (\r
- VOID\r
- )\r
-{\r
- UINT16 Pm1Sts;\r
- UINT16 Pm1Cnt;\r
-\r
- //\r
- // Read the ACPI registers,\r
- // PM1_STS information cannot be lost after power down, unless CMOS is cleared.\r
- //\r
- Pm1Sts = IoRead16 (PcdGet16 (PcdPm1blkIoBaseAddress) + R_QNC_PM1BLK_PM1S);\r
- Pm1Cnt = IoRead16 (PcdGet16 (PcdPm1blkIoBaseAddress) + R_QNC_PM1BLK_PM1C);\r
-\r
- //\r
- // If B_SLP_TYP is S5\r
- //\r
- if ((Pm1Sts & B_QNC_PM1BLK_PM1S_WAKE) != 0 && (Pm1Cnt & B_QNC_PM1BLK_PM1C_SLPTP) == V_S5) {\r
- IoWrite16 (PcdGet16 (PcdPm1blkIoBaseAddress) + R_QNC_PM1BLK_PM1C, (Pm1Cnt & (~B_QNC_PM1BLK_PM1C_SLPTP)));\r
- return TRUE;\r
- }\r
-\r
- return FALSE;\r
-}\r
-\r
-/**\r
- This function is used to clear SMI and wake status.\r
-\r
-**/\r
-VOID\r
-EFIAPI\r
-QNCClearSmiAndWake (\r
- VOID\r
- )\r
-{\r
- UINT32 Gpe0Sts;\r
- UINT32 SmiSts;\r
-\r
- //\r
- // Read the ACPI registers\r
- //\r
- Gpe0Sts = IoRead32 ((UINT16)(LpcPciCfg32 (R_QNC_LPC_GPE0BLK) & 0xFFFF) + R_QNC_GPE0BLK_GPE0S);\r
- SmiSts = IoRead32 ((UINT16)(LpcPciCfg32 (R_QNC_LPC_GPE0BLK) & 0xFFFF) + R_QNC_GPE0BLK_SMIS);\r
-\r
- //\r
- // Clear any SMI or wake state from the boot\r
- //\r
- Gpe0Sts |= B_QNC_GPE0BLK_GPE0S_ALL;\r
- SmiSts |= B_QNC_GPE0BLK_SMIS_ALL;\r
-\r
- //\r
- // Write them back\r
- //\r
- IoWrite32 ((UINT16)(LpcPciCfg32 (R_QNC_LPC_GPE0BLK) & 0xFFFF) + R_QNC_GPE0BLK_GPE0S, Gpe0Sts);\r
- IoWrite32 ((UINT16)(LpcPciCfg32 (R_QNC_LPC_GPE0BLK) & 0xFFFF) + R_QNC_GPE0BLK_SMIS, SmiSts);\r
-}\r
-\r
-/** Send DRAM Ready opcode.\r
-\r
- @param[in] OpcodeParam Parameter to DRAM ready opcode.\r
-\r
- @retval VOID\r
-**/\r
-VOID\r
-EFIAPI\r
-QNCSendOpcodeDramReady (\r
- IN UINT32 OpcodeParam\r
- )\r
-{\r
-\r
- //\r
- // Before sending DRAM ready place invalid value in Scrub Config.\r
- //\r
- QNCPortWrite (\r
- QUARK_NC_RMU_SB_PORT_ID,\r
- QUARK_NC_ECC_SCRUB_CONFIG_REG,\r
- SCRUB_CFG_INVALID\r
- );\r
-\r
- //\r
- // Send opcode and use param to notify HW of new RMU firmware location.\r
- //\r
- McD0PciCfg32 (QNC_ACCESS_PORT_MDR) = OpcodeParam;\r
- McD0PciCfg32 (QNC_ACCESS_PORT_MCR) = MESSAGE_SHADOW_DW (QUARK_NC_RMU_SB_PORT_ID, 0);\r
-\r
- //\r
- // HW completed tasks on DRAM ready when scrub config read back as zero.\r
- //\r
- while (QNCPortRead (QUARK_NC_RMU_SB_PORT_ID, QUARK_NC_ECC_SCRUB_CONFIG_REG) != 0) {\r
- MicroSecondDelay (10);\r
- }\r
-}\r
-\r
-/**\r
-\r
- Relocate RMU Main binary to memory after MRC to improve performance.\r
-\r
- @param[in] DestBaseAddress - Specify the new memory address for the RMU Main binary.\r
- @param[in] SrcBaseAddress - Specify the current memory address for the RMU Main binary.\r
- @param[in] Size - Specify size of the RMU Main binary.\r
-\r
- @retval VOID\r
-\r
-**/\r
-VOID\r
-EFIAPI\r
-RmuMainRelocation (\r
- IN CONST UINT32 DestBaseAddress,\r
- IN CONST UINT32 SrcBaseAddress,\r
- IN CONST UINTN Size\r
- )\r
-{\r
- //\r
- // Shadow RMU Main binary into main memory.\r
- //\r
- CopyMem ((VOID *)(UINTN)DestBaseAddress,(VOID *)(UINTN) SrcBaseAddress, Size);\r
-}\r
-\r
-\r
-/**\r
- Get the total memory size\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-QNCGetTotalMemorysize (\r
- VOID\r
- )\r
-{\r
- return QNCPortRead(QUARK_NC_HOST_BRIDGE_SB_PORT_ID, QUARK_NC_HOST_BRIDGE_HMBOUND_REG) & HMBOUND_MASK;\r
-}\r
-\r
-\r
-/**\r
- Get the memory range of TSEG.\r
- The TSEG's memory is below TOLM.\r
-\r
- @param[out] BaseAddress The base address of TSEG's memory range\r
- @param[out] MemorySize The size of TSEG's memory range\r
-\r
-**/\r
-VOID\r
-EFIAPI\r
-QNCGetTSEGMemoryRange (\r
- OUT UINT64 *BaseAddress,\r
- OUT UINT64 *MemorySize\r
- )\r
-{\r
- UINT64 Register = 0;\r
- UINT64 SMMAddress = 0;\r
-\r
- Register = QncHsmmcRead ();\r
-\r
- //\r
- // Get the SMRAM Base address\r
- //\r
- SMMAddress = Register & SMM_START_MASK;\r
- *BaseAddress = LShift16 (SMMAddress);\r
-\r
- //\r
- // Get the SMRAM size\r
- //\r
- SMMAddress = ((Register & SMM_END_MASK) | (~SMM_END_MASK)) + 1;\r
- *MemorySize = SMMAddress - (*BaseAddress);\r
-\r
- DEBUG ((\r
- EFI_D_INFO,\r
- "TSEG's memory range: BaseAddress = 0x%x, Size = 0x%x\n",\r
- (UINT32)*BaseAddress,\r
- (UINT32)*MemorySize\r
- ));\r
-}\r
-\r
-/**\r
- Updates the PAM registers in the MCH for the requested range and mode.\r
-\r
- @param Start The start address of the memory region\r
- @param Length The length, in bytes, of the memory region\r
- @param ReadEnable Pointer to the boolean variable on whether to enable read for legacy memory section.\r
- If NULL, then read attribute will not be touched by this call.\r
- @param ReadEnable Pointer to the boolean variable on whether to enable write for legacy memory section.\r
- If NULL, then write attribute will not be touched by this call.\r
- @param Granularity A pointer to granularity, in bytes, that the PAM registers support\r
-\r
- @retval RETURN_SUCCESS The PAM registers in the MCH were updated\r
- @retval RETURN_INVALID_PARAMETER The memory range is not valid in legacy region.\r
-\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-QNCLegacyRegionManipulation (\r
- IN UINT32 Start,\r
- IN UINT32 Length,\r
- IN BOOLEAN *ReadEnable,\r
- IN BOOLEAN *WriteEnable,\r
- OUT UINT32 *Granularity\r
- )\r
-{\r
- //\r
- // Do nothing cos no such support on QNC\r
- //\r
- return RETURN_SUCCESS;\r
-}\r
-\r
-/**\r
- Determine if QNC is supported.\r
-\r
- @retval FALSE QNC is not supported.\r
- @retval TRUE QNC is supported.\r
-**/\r
-BOOLEAN\r
-EFIAPI\r
-IsQncSupported (\r
- VOID\r
- )\r
-{\r
- UINT16 SocVendorId;\r
- UINT16 SocDeviceId;\r
-\r
- SocVendorId = MmioRead16 (\r
- PciDeviceMmBase (MC_BUS,\r
- MC_DEV,\r
- MC_FUN) + PCI_VENDOR_ID_OFFSET\r
- );\r
-\r
- SocDeviceId = QncGetSocDeviceId();\r
-\r
- //\r
- // Verify that this is a supported chipset\r
- //\r
- if ((SocVendorId != QUARK_MC_VENDOR_ID) || ((SocDeviceId != QUARK_MC_DEVICE_ID) && (SocDeviceId != QUARK2_MC_DEVICE_ID))) {\r
- DEBUG ((DEBUG_ERROR, "QNC code doesn't support the Soc VendorId:0x%04x Soc DeviceId:0x%04x!\n", SocVendorId, SocDeviceId));\r
- return FALSE;\r
- }\r
- return TRUE;\r
-}\r
-\r
-/**\r
- Get the DeviceId of the SoC\r
-\r
- @retval PCI DeviceId of the SoC\r
-**/\r
-UINT16\r
-EFIAPI\r
-QncGetSocDeviceId (\r
- VOID\r
- )\r
-{\r
- UINT16 SocDeviceId;\r
-\r
- SocDeviceId = MmioRead16 (\r
- PciDeviceMmBase (\r
- MC_BUS,\r
- MC_DEV,\r
- MC_FUN\r
- ) + PCI_DEVICE_ID_OFFSET\r
- );\r
-\r
- return SocDeviceId;\r
-}\r
-\r
-/**\r
- Enable SMI detection of legacy flash access violations.\r
-**/\r
-VOID\r
-EFIAPI\r
-QncEnableLegacyFlashAccessViolationSmi (\r
- VOID\r
- )\r
-{\r
- UINT32 BcValue;\r
-\r
- BcValue = LpcPciCfg32 (R_QNC_LPC_BIOS_CNTL);\r
-\r
- //\r
- // Clear BIOSWE & set BLE.\r
- //\r
- BcValue &= (~B_QNC_LPC_BIOS_CNTL_BIOSWE);\r
- BcValue |= (B_QNC_LPC_BIOS_CNTL_BLE);\r
-\r
- LpcPciCfg32 (R_QNC_LPC_BIOS_CNTL) = BcValue;\r
-\r
- DEBUG ((EFI_D_INFO, "BIOS Control Lock Enabled!\n"));\r
-}\r
-\r
-/**\r
- Setup RMU Thermal sensor registers for Vref mode.\r
-**/\r
-VOID\r
-EFIAPI\r
-QNCThermalSensorSetVRefMode (\r
- VOID\r
- )\r
-{\r
- UINT32 Tscgf1Config;\r
- UINT32 Tscgf2Config;\r
- UINT32 Tscgf2Config2;\r
-\r
- Tscgf1Config = QNCAltPortRead (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_TSCGF1_CONFIG);\r
- Tscgf2Config = QNCAltPortRead (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_TSCGF2_CONFIG);\r
- Tscgf2Config2 = QNCAltPortRead (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_TSCGF2_CONFIG2);\r
-\r
- Tscgf1Config &= ~(B_TSCGF1_CONFIG_ISNSCURRENTSEL_MASK);\r
- Tscgf1Config |= (V_TSCGF1_CONFIG_ISNSCURRENTSEL_VREF_MODE << B_TSCGF1_CONFIG_ISNSCURRENTSEL_BP);\r
-\r
- Tscgf1Config &= ~(B_TSCGF1_CONFIG_IBGEN);\r
- Tscgf1Config |= (V_TSCGF1_CONFIG_IBGEN_VREF_MODE << B_TSCGF1_CONFIG_IBGEN_BP);\r
-\r
- Tscgf2Config2 &= ~(B_TSCGF2_CONFIG2_ISPARECTRL_MASK);\r
- Tscgf2Config2 |= (V_TSCGF2_CONFIG2_ISPARECTRL_VREF_MODE << B_TSCGF2_CONFIG2_ISPARECTRL_BP);\r
-\r
- Tscgf2Config2 &= ~(B_TSCGF2_CONFIG2_ICALCOARSETUNE_MASK);\r
- Tscgf2Config2 |= (V_TSCGF2_CONFIG2_ICALCOARSETUNE_VREF_MODE << B_TSCGF2_CONFIG2_ICALCOARSETUNE_BP);\r
-\r
- Tscgf2Config &= ~(B_TSCGF2_CONFIG_IDSCONTROL_MASK);\r
- Tscgf2Config |= (V_TSCGF2_CONFIG_IDSCONTROL_VREF_MODE << B_TSCGF2_CONFIG_IDSCONTROL_BP);\r
-\r
- QNCAltPortWrite (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_TSCGF1_CONFIG, Tscgf1Config);\r
- QNCAltPortWrite (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_TSCGF2_CONFIG, Tscgf2Config);\r
- QNCAltPortWrite (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_TSCGF2_CONFIG2, Tscgf2Config2);\r
-}\r
-\r
-/**\r
- Setup RMU Thermal sensor registers for Ratiometric mode.\r
-**/\r
-VOID\r
-EFIAPI\r
-QNCThermalSensorSetRatiometricMode (\r
- VOID\r
- )\r
-{\r
- UINT32 Tscgf1Config;\r
- UINT32 Tscgf2Config;\r
- UINT32 Tscgf2Config2;\r
- UINT32 Tscgf3Config;\r
-\r
- Tscgf1Config = QNCAltPortRead (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_TSCGF1_CONFIG);\r
- Tscgf2Config = QNCAltPortRead (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_TSCGF2_CONFIG);\r
- Tscgf2Config2 = QNCAltPortRead (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_TSCGF2_CONFIG2);\r
- Tscgf3Config = QNCAltPortRead (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_TSCGF3_CONFIG);\r
-\r
- Tscgf1Config &= ~(B_TSCGF1_CONFIG_ISNSCURRENTSEL_MASK);\r
- Tscgf1Config |= (V_TSCGF1_CONFIG_ISNSCURRENTSEL_RATIO_MODE << B_TSCGF1_CONFIG_ISNSCURRENTSEL_BP);\r
-\r
- Tscgf1Config &= ~(B_TSCGF1_CONFIG_ISNSCHOPSEL_MASK);\r
- Tscgf1Config |= (V_TSCGF1_CONFIG_ISNSCHOPSEL_RATIO_MODE << B_TSCGF1_CONFIG_ISNSCHOPSEL_BP);\r
-\r
- Tscgf1Config &= ~(B_TSCGF1_CONFIG_ISNSINTERNALVREFEN);\r
- Tscgf1Config |= (V_TSCGF1_CONFIG_ISNSINTERNALVREFEN_RATIO_MODE << B_TSCGF1_CONFIG_ISNSINTERNALVREFEN_BP);\r
-\r
- Tscgf1Config &= ~(B_TSCGF1_CONFIG_IBGEN);\r
- Tscgf1Config |= (V_TSCGF1_CONFIG_IBGEN_RATIO_MODE << B_TSCGF1_CONFIG_IBGEN_BP);\r
-\r
- Tscgf1Config &= ~(B_TSCGF1_CONFIG_IBGCHOPEN);\r
- Tscgf1Config |= (V_TSCGF1_CONFIG_IBGCHOPEN_RATIO_MODE << B_TSCGF1_CONFIG_IBGCHOPEN_BP);\r
-\r
- Tscgf2Config2 &= ~(B_TSCGF2_CONFIG2_ICALCONFIGSEL_MASK);\r
- Tscgf2Config2 |= (V_TSCGF2_CONFIG2_ICALCONFIGSEL_RATIO_MODE << B_TSCGF2_CONFIG2_ICALCONFIGSEL_BP);\r
-\r
- Tscgf2Config2 &= ~(B_TSCGF2_CONFIG2_ISPARECTRL_MASK);\r
- Tscgf2Config2 |= (V_TSCGF2_CONFIG2_ISPARECTRL_RATIO_MODE << B_TSCGF2_CONFIG2_ISPARECTRL_BP);\r
-\r
- Tscgf2Config2 &= ~(B_TSCGF2_CONFIG2_ICALCOARSETUNE_MASK);\r
- Tscgf2Config2 |= (V_TSCGF2_CONFIG2_ICALCOARSETUNE_RATIO_MODE << B_TSCGF2_CONFIG2_ICALCOARSETUNE_BP);\r
-\r
- Tscgf2Config &= ~(B_TSCGF2_CONFIG_IDSCONTROL_MASK);\r
- Tscgf2Config |= (V_TSCGF2_CONFIG_IDSCONTROL_RATIO_MODE << B_TSCGF2_CONFIG_IDSCONTROL_BP);\r
-\r
- Tscgf2Config &= ~(B_TSCGF2_CONFIG_IDSTIMING_MASK);\r
- Tscgf2Config |= (V_TSCGF2_CONFIG_IDSTIMING_RATIO_MODE << B_TSCGF2_CONFIG_IDSTIMING_BP);\r
-\r
- Tscgf3Config &= ~(B_TSCGF3_CONFIG_ITSGAMMACOEFF_MASK);\r
- Tscgf3Config |= (V_TSCGF3_CONFIG_ITSGAMMACOEFF_RATIO_MODE << B_TSCGF3_CONFIG_ITSGAMMACOEFF_BP);\r
-\r
- QNCAltPortWrite (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_TSCGF1_CONFIG, Tscgf1Config);\r
- QNCAltPortWrite (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_TSCGF2_CONFIG, Tscgf2Config);\r
- QNCAltPortWrite (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_TSCGF2_CONFIG2, Tscgf2Config2);\r
- QNCAltPortWrite (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_TSCGF3_CONFIG, Tscgf3Config);\r
-}\r
-\r
-/**\r
- Setup RMU Thermal sensor trip point values.\r
-\r
- @param[in] CatastrophicTripOnDegreesCelsius - Catastrophic set trip point threshold.\r
- @param[in] HotTripOnDegreesCelsius - Hot set trip point threshold.\r
- @param[in] HotTripOffDegreesCelsius - Hot clear trip point threshold.\r
-\r
- @retval EFI_SUCCESS Trip points setup.\r
- @retval EFI_INVALID_PARAMETER Invalid trip point value.\r
-\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-QNCThermalSensorSetTripValues (\r
- IN CONST UINTN CatastrophicTripOnDegreesCelsius,\r
- IN CONST UINTN HotTripOnDegreesCelsius,\r
- IN CONST UINTN HotTripOffDegreesCelsius\r
- )\r
-{\r
- UINT32 RegisterValue;\r
-\r
- //\r
- // Register fields are 8-bit temperature values of granularity 1 degree C\r
- // where 0x00 corresponds to -50 degrees C\r
- // and 0xFF corresponds to 205 degrees C.\r
- //\r
- // User passes unsigned values in degrees Celsius so trips < 0 not supported.\r
- //\r
- // Add 50 to user values to get values for register fields.\r
- //\r
-\r
- if ((CatastrophicTripOnDegreesCelsius > 205) || (HotTripOnDegreesCelsius > 205) || (HotTripOffDegreesCelsius > 205)) {\r
- return EFI_INVALID_PARAMETER;\r
- }\r
-\r
- //\r
- // Set new values.\r
- //\r
- RegisterValue =\r
- ((0 + 50) << TS_CAT_TRIP_CLEAR_THOLD_BP) | // Cat Trip Clear value must be less than Cat Trip Set Value.\r
- ((CatastrophicTripOnDegreesCelsius + 50) << TS_CAT_TRIP_SET_THOLD_BP) |\r
- ((HotTripOnDegreesCelsius + 50) << TS_HOT_TRIP_SET_THOLD_BP) |\r
- ((HotTripOffDegreesCelsius + 50) << TS_HOT_TRIP_CLEAR_THOLD_BP)\r
- ;\r
-\r
- QNCPortWrite (QUARK_NC_RMU_SB_PORT_ID, QUARK_NC_RMU_REG_TS_TRIP, RegisterValue);\r
-\r
- return EFI_SUCCESS;\r
-}\r
-\r
-/**\r
- Enable RMU Thermal sensor with a Catastrophic Trip point.\r
-\r
- @retval EFI_SUCCESS Trip points setup.\r
- @retval EFI_INVALID_PARAMETER Invalid trip point value.\r
-\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-QNCThermalSensorEnableWithCatastrophicTrip (\r
- IN CONST UINTN CatastrophicTripOnDegreesCelsius\r
- )\r
-{\r
- UINT32 Tscgf3Config;\r
- UINT32 TsModeReg;\r
- UINT32 TsTripReg;\r
-\r
- //\r
- // Trip Register fields are 8-bit temperature values of granularity 1 degree C\r
- // where 0x00 corresponds to -50 degrees C\r
- // and 0xFF corresponds to 205 degrees C.\r
- //\r
- // User passes unsigned values in degrees Celsius so trips < 0 not supported.\r
- //\r
- // Add 50 to user values to get values for register fields.\r
- //\r
-\r
- if (CatastrophicTripOnDegreesCelsius > 205) {\r
- return EFI_INVALID_PARAMETER;\r
- }\r
-\r
- Tscgf3Config = QNCAltPortRead (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_TSCGF3_CONFIG);\r
- TsModeReg = QNCPortRead (QUARK_NC_RMU_SB_PORT_ID, QUARK_NC_RMU_REG_TS_MODE);\r
- TsTripReg = QNCPortRead (QUARK_NC_RMU_SB_PORT_ID, QUARK_NC_RMU_REG_TS_TRIP);\r
-\r
- //\r
- // Setup Catastrophic Trip point.\r
- //\r
- TsTripReg &= ~(TS_CAT_TRIP_SET_THOLD_MASK);\r
- TsTripReg |= ((CatastrophicTripOnDegreesCelsius + 50) << TS_CAT_TRIP_SET_THOLD_BP);\r
- TsTripReg &= ~(TS_CAT_TRIP_CLEAR_THOLD_MASK);\r
- TsTripReg |= ((0 + 50) << TS_CAT_TRIP_CLEAR_THOLD_BP); // Cat Trip Clear value must be less than Cat Trip Set Value.\r
- QNCPortWrite (QUARK_NC_RMU_SB_PORT_ID, QUARK_NC_RMU_REG_TS_TRIP, TsTripReg);\r
-\r
- //\r
- // To enable the TS do the following:\r
- // 1) Take the TS out of reset by setting itsrst to 0x0.\r
- // 2) Enable the TS using RMU Thermal sensor mode register.\r
- //\r
-\r
- Tscgf3Config &= ~(B_TSCGF3_CONFIG_ITSRST);\r
- TsModeReg |= TS_ENABLE;\r
-\r
- QNCAltPortWrite (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_TSCGF3_CONFIG, Tscgf3Config);\r
- QNCPortWrite (QUARK_NC_RMU_SB_PORT_ID, QUARK_NC_RMU_REG_TS_MODE, TsModeReg);\r
-\r
- return EFI_SUCCESS;\r
-}\r
-\r
-/**\r
- Lock all RMU Thermal sensor control & trip point registers.\r
-\r
-**/\r
-VOID\r
-EFIAPI\r
-QNCThermalSensorLockAllRegisters (\r
- VOID\r
- )\r
-{\r
- UINT32 RegValue;\r
- UINT32 LockMask;\r
-\r
- LockMask = TS_LOCK_THRM_CTRL_REGS_ENABLE | TS_LOCK_AUX_TRIP_PT_REGS_ENABLE;\r
-\r
- RegValue = QNCPortRead (QUARK_NC_RMU_SB_PORT_ID, QUARK_NC_RMU_REG_CONFIG);\r
- RegValue |= LockMask;\r
- QNCPortWrite (QUARK_NC_RMU_SB_PORT_ID, QUARK_NC_RMU_REG_CONFIG, RegValue);\r
-\r
- ASSERT ((LockMask == (QNCPortRead (QUARK_NC_RMU_SB_PORT_ID, QUARK_NC_RMU_REG_CONFIG) & LockMask)));\r
-}\r
-\r
-/**\r
- Set chipset policy for double bit ECC error.\r
-\r
- @param[in] PolicyValue Policy to config on double bit ECC error.\r
-\r
-**/\r
-VOID\r
-EFIAPI\r
-QNCPolicyDblEccBitErr (\r
- IN CONST UINT32 PolicyValue\r
- )\r
-{\r
- UINT32 Register;\r
- Register = QNCPortRead (QUARK_NC_RMU_SB_PORT_ID, QUARK_NC_RMU_REG_WDT_CONTROL);\r
- Register &= ~(B_WDT_CONTROL_DBL_ECC_BIT_ERR_MASK);\r
- Register |= PolicyValue;\r
- QNCPortWrite (\r
- QUARK_NC_RMU_SB_PORT_ID,\r
- QUARK_NC_RMU_REG_WDT_CONTROL,\r
- Register\r
- );\r
-}\r
-\r
-/**\r
- Determine if running on secure Quark hardware Sku.\r
-\r
- @retval FALSE Base Quark Sku or unprovisioned Secure Sku running.\r
- @retval TRUE Provisioned SecureSku hardware running.\r
-**/\r
-BOOLEAN\r
-EFIAPI\r
-QncIsSecureProvisionedSku (\r
- VOID\r
- )\r
-{\r
- // Read QUARK Secure SKU Fuse\r
- return ((QNCAltPortRead (QUARK_SCSS_FUSE_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_SPI_ROM_FUSE) & BIT6) == BIT6);\r
-}\r
projects / mirror_edk2.git / blobdiff