--- /dev/null
+/************************************************************************\r
+ *\r
+ * Copyright (c) 2013-2015 Intel Corporation.\r
+ *\r
+* This program and the accompanying materials\r
+* are licensed and made available under the terms and conditions of the BSD License\r
+* which accompanies this distribution. The full text of the license may be found at\r
+* http://opensource.org/licenses/bsd-license.php\r
+*\r
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+ *\r
+ * MCU register definition\r
+ *\r
+ ************************************************************************/\r
+#ifndef __IOSF_DEFINITIONS_H\r
+#define __IOSF_DEFINITIONS_H\r
+\r
+// Define each of the IOSF-SB register offsets used by MRC.\r
+\r
+\r
+// MCU registers (DUNIT):\r
+// ====\r
+#define DRP 0x0000\r
+#define DTR0 0x0001\r
+#define DTR1 0x0002\r
+#define DTR2 0x0003\r
+#define DTR3 0x0004\r
+#define DTR4 0x0005\r
+#define DPMC0 0x0006\r
+#define DPMC1 0x0007\r
+#define DRFC 0x0008\r
+#define DSCH 0x0009\r
+#define DCAL 0x000A\r
+#define DRMC 0x000B\r
+#define PMSTS 0x000C\r
+#define DCO 0x000F\r
+#define DSTAT 0x0020\r
+#define DECCCTRL 0x0060\r
+#define DFUSESTAT 0x0070\r
+#define SCRMSEED 0x0080\r
+#define SCRMLO 0x0081\r
+#define SCRMHI 0x0082\r
+\r
+#define MCU_CH_OFFSET 0x0040\r
+#define MCU_RK_OFFSET 0x0020\r
+\r
+////\r
+//\r
+// BEGIN DUnit register definition\r
+//\r
+#pragma pack(1)\r
+typedef union {\r
+ uint32_t raw;\r
+ struct {\r
+ uint32_t rank0Enabled :1; /**< BIT [0] Rank 0 Enable */\r
+ uint32_t rank1Enabled :1; /**< BIT [1] Rank 1 Enable */\r
+ uint32_t reserved0 :2;\r
+ uint32_t dimm0DevWidth :2; /**< BIT [5:4] DIMM 0 Device Width (Rank0&1) */\r
+ uint32_t dimm0DevDensity :2; /**< BIT [7:6] DIMM 0 Device Density */\r
+ uint32_t reserved1 :1;\r
+ uint32_t dimm1DevWidth :2; /**< BIT [10:9] DIMM 1 Device Width (Rank2&3) */\r
+ uint32_t dimm1DevDensity :2; /**< BIT [12:11] DIMM 1 Device Density */\r
+ uint32_t split64 :1; /**< BIT [13] split 64B transactions */\r
+ uint32_t addressMap :2; /**< BIT [15:14] Address Map select */\r
+ uint32_t reserved3 :14;\r
+ uint32_t mode32 :1; /**< BIT [30] Select 32bit data interface*/\r
+ uint32_t reserved4 :1;\r
+ } field;\r
+} RegDRP; /**< DRAM Rank Population and Interface Register */\r
+#pragma pack()\r
+\r
+\r
+#pragma pack(1)\r
+typedef union {\r
+ uint32_t raw;\r
+ struct {\r
+ uint32_t dramFrequency :2; /**< DRAM Frequency (000=800,001=1033,010=1333) */\r
+ uint32_t reserved1 :2;\r
+ uint32_t tRP :4; /**< bit [7:4] Precharge to Activate Delay */\r
+ uint32_t tRCD :4; /**< bit [11:8] Activate to CAS Delay */\r
+ uint32_t tCL :3; /**< bit [14:12] CAS Latency */\r
+ uint32_t reserved4 :1;\r
+ uint32_t tXS :1; /**< SRX Delay */\r
+ uint32_t reserved5 :1;\r
+ uint32_t tXSDLL :1; /**< SRX To DLL Delay */\r
+ uint32_t reserved6 :1;\r
+ uint32_t tZQCS :1; /**< bit [20] ZQTS recovery Latncy */\r
+ uint32_t reserved7 :1;\r
+ uint32_t tZQCL :1; /**< bit [22] ZQCL recovery Latncy */\r
+ uint32_t reserved8 :1;\r
+ uint32_t pmeDelay :2; /**< bit [25:24] Power mode entry delay */\r
+ uint32_t reserved9 :2;\r
+ uint32_t CKEDLY :4; /**< bit [31:28] */\r
+ } field;\r
+} RegDTR0; /**< DRAM Timing Register 0 */\r
+#pragma pack()\r
+\r
+#pragma pack(1)\r
+typedef union {\r
+ uint32_t raw;\r
+ struct {\r
+ uint32_t tWCL :3; /**< bit [2:0] CAS Write Latency */\r
+ uint32_t reserved1 :1;\r
+ uint32_t tCMD :2; /**< bit [5:4] Command transport duration */\r
+ uint32_t reserved2 :2;\r
+ uint32_t tWTP :4; /**< Write to Precharge */\r
+ uint32_t tCCD :2; /**< CAS to CAS delay */\r
+ uint32_t reserved4 :2;\r
+ uint32_t tFAW :4; /**< Four bank Activation Window*/\r
+ uint32_t tRAS :4; /**< Row Activation Period: */\r
+ uint32_t tRRD :2; /**<Row activation to Row activation Delay */\r
+ uint32_t reserved5 :2;\r
+ uint32_t tRTP :3; /**<Read to Precharge Delay */\r
+ uint32_t reserved6 :1;\r
+ } field;\r
+} RegDTR1; /**< DRAM Timing Register 1 */\r
+#pragma pack()\r
+\r
+#pragma pack(1)\r
+typedef union {\r
+ uint32_t raw;\r
+ struct {\r
+ uint32_t tRRDR :3; /**< RD to RD from different ranks, same DIMM */\r
+ uint32_t reserved1 :5;\r
+ uint32_t tWWDR :3; /**< WR to WR from different ranks, same DIMM. */\r
+ uint32_t reserved3 :5;\r
+ uint32_t tRWDR :4; /**< bit [19:16] RD to WR from different ranks, same DIMM. */\r
+ uint32_t reserved5 :12;\r
+ } field;\r
+} RegDTR2; /**< DRAM Timing Register 2 */\r
+#pragma pack()\r
+\r
+#pragma pack(1)\r
+typedef union {\r
+ uint32_t raw;\r
+ struct {\r
+ uint32_t tWRDR :3; /**< WR to RD from different ranks, same DIMM. */\r
+ uint32_t reserved1 :1;\r
+ uint32_t tWRDD :3; /**< WR to RD from different DIMM. */\r
+ uint32_t reserved2 :1;\r
+ uint32_t tRWSR :4; /**< RD to WR Same Rank. */\r
+ uint32_t reserved3 :1;\r
+ uint32_t tWRSR :4; /**< WR to RD Same Rank. */\r
+ uint32_t reserved4 :5;\r
+ uint32_t tXP :2; /**< Time from CKE set on to any command. */\r
+ uint32_t PWD_DLY :4; /**< Extended Power-Down Delay. */\r
+ uint32_t EnDeRate :1;\r
+ uint32_t DeRateOvr :1;\r
+ uint32_t DeRateStat :1;\r
+ uint32_t reserved5 :1;\r
+ } field;\r
+} RegDTR3; /**< DRAM Timing Register 3 */\r
+#pragma pack()\r
+\r
+\r
+#pragma pack(1)\r
+typedef union {\r
+ uint32_t raw;\r
+ struct {\r
+ uint32_t WRODTSTRT :2; /**< WR command to ODT assert delay */\r
+ uint32_t reserved1 :2;\r
+ uint32_t WRODTSTOP :3; /**< Write command to ODT de-assert delay. */\r
+ uint32_t reserved2 :1;\r
+ uint32_t RDODTSTRT :3; /**< Read command to ODT assert delay */\r
+ uint32_t reserved3 :1;\r
+ uint32_t RDODTSTOP :3; /**< Read command to ODT de-assert delay */\r
+ uint32_t ODTDIS :1; /**< ODT disable */\r
+ uint32_t TRGSTRDIS :1; /**< Write target rank is not stretched */\r
+ uint32_t RDODTDIS :1; /**< Disable Read ODT */\r
+ uint32_t WRBODTDIS :1; /**< Disable Write ODT */\r
+ uint32_t reserved5 :13;\r
+ } field;\r
+} RegDTR4; /**< DRAM Timing Register 3 */\r
+#pragma pack()\r
+\r
+#pragma pack(1)\r
+typedef union {\r
+ uint32_t raw;\r
+ struct {\r
+ uint32_t SREntryDelay :8; /**< Self-Refresh Entry Delay: */\r
+ uint32_t powerModeOpCode :5; /**< SPID Power Mode Opcode */\r
+ uint32_t reserved1 :3;\r
+ uint32_t PCLSTO :3; /**< Page Close Timeout Period */\r
+ uint32_t reserved2 :1;\r
+ uint32_t PCLSWKOK :1; /**< Wake Allowed For Page Close Timeout */\r
+ uint32_t PREAPWDEN :1; /**< Send Precharge All to rank before entering Power-Down mode. */\r
+ uint32_t reserved3 :1;\r
+ uint32_t DYNSREN :1; /**< Dynamic Self-Refresh */\r
+ uint32_t CLKGTDIS :1; /**< Clock Gating Disabled*/\r
+ uint32_t DISPWRDN :1; /**< Disable Power Down*/\r
+ uint32_t reserved4 :2;\r
+ uint32_t REUTCLKGTDIS :1;\r
+ uint32_t ENPHYCLKGATE :1;\r
+ uint32_t reserved5 :2;\r
+ } field;\r
+} RegDPMC0; /**< DRAM Power Management Control Register 0 */\r
+#pragma pack()\r
+\r
+#pragma pack(1)\r
+typedef union {\r
+ uint32_t raw;\r
+ struct {\r
+ uint32_t REFWMLO :4; /**< Refresh Opportunistic Watermark */\r
+ uint32_t REFWMHI :4; /**< Refresh High Watermark*/\r
+ uint32_t REFWMPNC :4; /**< Refresh Panic Watermark */\r
+ uint32_t tREFI :3; /**< bit [14:12] Refresh Period */\r
+ uint32_t reserved1 :1;\r
+ uint32_t REFCNTMAX :2; /**< Refresh Max tREFI Interval */\r
+ uint32_t reserved2 :2;\r
+ uint32_t REFSKEWDIS :1; /**< tREFI counters */\r
+ uint32_t REFDBTCLR :1;\r
+ uint32_t reserved3 :2;\r
+ uint32_t CuRefRate :3;\r
+ uint32_t DisRefBW :1;\r
+ uint32_t reserved4 :4;\r
+ } field;\r
+} RegDRCF; /**< DRAM Refresh Control Register*/\r
+#pragma pack()\r
+\r
+#pragma pack(1)\r
+typedef union {\r
+ uint32_t raw;\r
+ struct {\r
+ uint32_t reserved1 :8;\r
+ uint32_t ZQCINT :3; /**< ZQ Calibration Short Interval: */\r
+ uint32_t reserved2 :1;\r
+ uint32_t SRXZQCL :2; /** < ZQ Calibration Length */\r
+ uint32_t ZQCalType :1;\r
+ uint32_t ZQCalStart :1;\r
+ uint32_t TQPollStart :1;\r
+ uint32_t TQPollRS :2;\r
+ uint32_t reserved3 :5;\r
+ uint32_t MRRData :8; /**< bit[31:24] */\r
+ } field;\r
+} RegDCAL; /**< DRAM Calibration Control*/\r
+#pragma pack()\r
+\r
+#pragma pack(1)\r
+typedef union {\r
+ uint32_t raw;\r
+ struct {\r
+ uint32_t OOOAGETRH :5; /**< Out-of-Order Aging Threshold */\r
+ uint32_t reserved1 :3;\r
+ uint32_t OOODIS :1; /**< Out-of-Order Disable */\r
+ uint32_t OOOST3DIS :1; /**< Out-of-Order Disabled when RequestBD_Status is 3. */\r
+ uint32_t reserved2 :2;\r
+ uint32_t NEWBYPDIS :1;\r
+ uint32_t reserved3 :3;\r
+ uint32_t IPREQMAX :3; /** < Max In-Progress Requests stored in MC */\r
+ uint32_t reserved4 :13;\r
+ } field;\r
+} RegDSCH; /**< DRAM Scheduler Control Register */\r
+#pragma pack()\r
+\r
+#pragma pack(1)\r
+typedef union {\r
+ uint32_t raw;\r
+ struct {\r
+ uint32_t DRPLOCK :1; /**< DRP lock bit */\r
+ uint32_t reserved1 :7;\r
+ uint32_t REUTLOCK :1; /**< REUT lock bit */\r
+ uint32_t reserved2 :19;\r
+ uint32_t PMICTL :1; /**< PRI Control Select: 0-memory_manager, 1-hte */\r
+ uint32_t PMIDIS :1; /**< PMIDIS Should be set is using IOSF-SB RW */\r
+ uint32_t DIOIC :1; /**< DDRIO initialization is complete */\r
+ uint32_t IC :1; /**< D-unit Initialization Complete */\r
+ } field;\r
+} RegDCO; /**< DRAM Controller Operation Register*/\r
+#pragma pack()\r
+\r
+#pragma pack(1)\r
+typedef union {\r
+ uint32_t raw;\r
+ struct {\r
+ uint32_t SBEEN :1; /**< Enable Single Bit Error Detection and Correction */\r
+ uint32_t DBEEN :1; /**< Enable Double Bit Error Detection */\r
+ uint32_t CBOEN :3; /**< Enable ECC Check Bits Override */\r
+ uint32_t SYNSEL :2; /**< ECC Syndrome Bits Select for Observation */\r
+ uint32_t CLRSBECNT :1; /**< Clear ECC Single Bit Error Count */\r
+ uint32_t CBOV :8; /**< ECC Check Bits Override Value */\r
+ uint32_t reserved1 :1; /**< */\r
+ uint32_t ENCBGEN :1; /**< Enable Generation of ECC Check Bits */\r
+ uint32_t ENCBGESWIZ :1; /**< Enable Same Chip ECC Byte Lane Swizzle */\r
+\r
+ } field;\r
+} RegDECCCTRL; /**< DRAM ECC Control Register */\r
+#pragma pack()\r
+\r
+\r
+#pragma pack(1)\r
+typedef union {\r
+ uint32_t raw;\r
+ struct {\r
+ uint32_t FUS_DUN_ECC_DIS :1;\r
+ uint32_t FUS_DUN_MAX_SUPPORTED_MEMORY :3;\r
+ uint32_t FUS_DUN_MAX_DEVDEN :2;\r
+ uint32_t RESERVED1 :1;\r
+ uint32_t FUS_DUN_RANK2_DIS :1;\r
+ uint32_t FUS_DUN_OOO_DIS :1;\r
+ uint32_t FUS_DUN_MEMX8_DIS :1;\r
+ uint32_t FUS_DUN_MEMX16_DIS :1;\r
+ uint32_t RESERVED2 :1;\r
+ uint32_t FUS_DUN_1N_DIS :1;\r
+ uint32_t FUS_DUN_DQ_SCRAMBLER_DIS :1;\r
+ uint32_t RESERVED3 :1;\r
+ uint32_t FUS_DUN_32BIT_DRAM_IFC :1;\r
+ } field;\r
+} RegDFUSESTAT;\r
+#pragma pack()\r
+\r
+//\r
+// END DUnit register definition\r
+//\r
+////\r
+\r
+\r
+\r
+////\r
+//\r
+// DRAM Initialization Structures used in JEDEC Message Bus Commands\r
+//\r
+\r
+#pragma pack(1)\r
+typedef union {\r
+ uint32_t raw;\r
+ struct {\r
+ unsigned command :3; /**< Command: 000-MRS,001-Refresh,010-Pre-charge,011-Activate,110-ZQ,111-NOP */\r
+ unsigned bankAddress :3; /**< Bank Address (BA[2:0]) */\r
+ unsigned BL :2; /**< Burst Length, CDV:1*/\r
+ unsigned CL :1; /**< CL Reserved CDV:0 */\r
+ unsigned RBT :1; /**< Read Burst Type */\r
+ unsigned casLatency :3; /**< cas Latency */\r
+ unsigned TM :1; /**< Test mode */\r
+ unsigned dllReset :1; /**< DLL Reset */\r
+ unsigned writeRecovery :3; /**< Write Recovery for Auto Pre-Charge: 001=2,010=3,011=4,100=5,101=6 */\r
+ unsigned PPD :1; /**< DLL Control for Precharge Power-Down CDV:1 */\r
+ unsigned reserved1 :3;\r
+ unsigned rankSelect :4; /**< Rank Select */\r
+ unsigned reserved2 :6;\r
+ } field;\r
+} DramInitDDR3MRS0; /**< DDR3 Mode Register Set (MRS) Command */\r
+#pragma pack()\r
+\r
+#pragma pack(1)\r
+typedef union {\r
+ uint32_t raw;\r
+ struct {\r
+ unsigned command :3; /**< Command: 000-MRS,001-Refresh,010-Pre-charge,011-Activate,110-ZQ,111-NOP */\r
+ unsigned bankAddress :3; /**< Bank Address (BA[2:0]) */\r
+ unsigned dllEnabled :1; /**< CDV=0 */\r
+ unsigned DIC0 :1; /**< Output Driver Impedance Control */\r
+ unsigned rttNom0 :1; /**< RTT_nom[0] */\r
+ unsigned MRC_AL :2; /**< Additive Latency = 0 */\r
+ unsigned DIC1 :1; /**< Reserved */\r
+ unsigned rttNom1 :1; /**< RTT_nom[1] */\r
+ unsigned wlEnabled :1; /**< Write Leveling Enable */\r
+ unsigned reserved1 :1;\r
+ unsigned rttNom2 :1; /** < RTT_nom[2] */\r
+ unsigned reserved2 :1;\r
+ unsigned TDQS :1; /**< TDQS Enable */\r
+ unsigned Qoff :1; /**< Output Buffers Disabled */\r
+ unsigned reserved3 :3;\r
+ unsigned rankSelect :4; /**< Rank Select */\r
+ unsigned reserved4 :6;\r
+ } field;\r
+} DramInitDDR3EMR1; /**< DDR3 Extended Mode Register 1 Set (EMRS1) Command */\r
+#pragma pack()\r
+\r
+#pragma pack(1)\r
+typedef union {\r
+ uint32_t raw;\r
+ struct {\r
+ uint32_t command :3; /**< Command: 000-MRS,001-Refresh,010-Pre-charge,011-Activate,110-ZQ,111-NOP */\r
+ uint32_t bankAddress :3; /**< Bank Address (BA[2:0]) */\r
+ uint32_t PASR :3; /**< Partial Array Self-Refresh */\r
+ uint32_t CWL :3; /**< CAS Write Latency */\r
+ uint32_t ASR :1; /**< Auto Self-Refresh */\r
+ uint32_t SRT :1; /**< SR Temperature Range = 0*/\r
+ uint32_t reserved1 :1;\r
+ uint32_t rtt_WR :2; /**< Rtt_WR */\r
+ uint32_t reserved2 :5;\r
+ uint32_t rankSelect :4; /**< Rank Select */\r
+ uint32_t reserved3 :6;\r
+ } field;\r
+} DramInitDDR3EMR2; /**< DDR3 Extended Mode Register 2 Set (EMRS2) Command */\r
+#pragma pack()\r
+\r
+#pragma pack(1)\r
+typedef union {\r
+ uint32_t raw;\r
+ struct {\r
+ uint32_t command :3; /**< Command: 000-MRS,001-Refresh,010-Pre-charge,011-Activate,110-ZQ,111-NOP */\r
+ uint32_t bankAddress :3; /**< Bank Address (BA[2:0]) */\r
+ uint32_t MPR_Location :2; /**< MPR Location */\r
+ uint32_t MPR :1; /**< MPR: Multi Purpose Register */\r
+ uint32_t reserved1 :13;\r
+ uint32_t rankSelect :4; /**< Rank Select */\r
+ uint32_t reserved2 :6;\r
+ } field;\r
+} DramInitDDR3EMR3; /**< DDR3 Extended Mode Register 2 Set (EMRS2) Command */\r
+#pragma pack()\r
+\r
+#pragma pack(1)\r
+typedef union {\r
+ uint32_t raw;\r
+ struct {\r
+ uint32_t command :3; /**< Command: 000-MRS,001-Refresh,010-Pre-charge,011-Activate,110 - ZQ Calibration,111-NOP */\r
+ uint32_t bankAddress :3; /**< Bank Address (BA[2:0]) */\r
+ uint32_t multAddress :16; /**< Multiplexed Address (MA[14:0]) */\r
+ uint32_t rankSelect :2; /**< Rank Select */\r
+ uint32_t reserved3 :8;\r
+ } field;\r
+} DramInitMisc; /**< Miscellaneous DDRx Initialization Command */\r
+#pragma pack()\r
+\r
+//\r
+// Construct DRAM init command using DramInitXxxx pattern\r
+//\r
+#define DCMD_MRS1(rnk,dat) (0 | ((rnk)<<22) | (1<<3) | ((dat)<<6))\r
+#define DCMD_REF(rnk) (1 | ((rnk)<<22))\r
+#define DCMD_PRE(rnk) (2 | ((rnk)<<22))\r
+#define DCMD_PREA(rnk) (2 | ((rnk)<<22) | (BIT10<<6))\r
+#define DCMD_ACT(rnk,row) (3 | ((rnk)<<22) | ((row)<<6))\r
+#define DCMD_WR(rnk,col) (4 | ((rnk)<<22) | ((col)<<6))\r
+#define DCMD_RD(rnk,col) (5 | ((rnk)<<22) | ((col)<<6))\r
+#define DCMD_ZQCS(rnk) (6 | ((rnk)<<22))\r
+#define DCMD_ZQCL(rnk) (6 | ((rnk)<<22) | (BIT10<<6))\r
+#define DCMD_NOP(rnk) (7 | ((rnk)<<22))\r
+\r
+\r
+\r
+\r
+#define DDR3_EMRS1_DIC_40 (0)\r
+#define DDR3_EMRS1_DIC_34 (1)\r
+\r
+#define DDR3_EMRS2_RTTWR_60 (BIT9)\r
+#define DDR3_EMRS2_RTTWR_120 (BIT10)\r
+\r
+#define DDR3_EMRS1_RTTNOM_0 (0)\r
+#define DDR3_EMRS1_RTTNOM_60 (BIT2)\r
+#define DDR3_EMRS1_RTTNOM_120 (BIT6)\r
+#define DDR3_EMRS1_RTTNOM_40 (BIT6|BIT2)\r
+#define DDR3_EMRS1_RTTNOM_20 (BIT9)\r
+#define DDR3_EMRS1_RTTNOM_30 (BIT9|BIT2)\r
+\r
+\r
+//\r
+// END DRAM Init...\r
+//\r
+////\r
+\r
+\r
+// HOST_BRIDGE registers:\r
+#define HMBOUND 0x0020 //ok\r
+\r
+// MEMORY_MANAGER registers:\r
+#define BCTRL 0x0004\r
+#define BWFLUSH 0x0008\r
+#define BDEBUG1 0x00C4\r
+\r
+////\r
+//\r
+// BEGIN DDRIO registers\r
+//\r
+\r
+// DDR IOs & COMPs:\r
+#define DDRIODQ_BL_OFFSET 0x0800\r
+#define DDRIODQ_CH_OFFSET ((NUM_BYTE_LANES/2) * DDRIODQ_BL_OFFSET)\r
+#define DDRIOCCC_CH_OFFSET 0x0800\r
+#define DDRCOMP_CH_OFFSET 0x0100\r
+\r
+// CH0-BL01-DQ\r
+#define DQOBSCKEBBCTL 0x0000\r
+#define DQDLLTXCTL 0x0004\r
+#define DQDLLRXCTL 0x0008\r
+#define DQMDLLCTL 0x000C\r
+#define B0RXIOBUFCTL 0x0010\r
+#define B0VREFCTL 0x0014\r
+#define B0RXOFFSET1 0x0018\r
+#define B0RXOFFSET0 0x001C\r
+#define B1RXIOBUFCTL 0x0020\r
+#define B1VREFCTL 0x0024\r
+#define B1RXOFFSET1 0x0028\r
+#define B1RXOFFSET0 0x002C\r
+#define DQDFTCTL 0x0030\r
+#define DQTRAINSTS 0x0034\r
+#define B1DLLPICODER0 0x0038\r
+#define B0DLLPICODER0 0x003C\r
+#define B1DLLPICODER1 0x0040\r
+#define B0DLLPICODER1 0x0044\r
+#define B1DLLPICODER2 0x0048\r
+#define B0DLLPICODER2 0x004C\r
+#define B1DLLPICODER3 0x0050\r
+#define B0DLLPICODER3 0x0054\r
+#define B1RXDQSPICODE 0x0058\r
+#define B0RXDQSPICODE 0x005C\r
+#define B1RXDQPICODER32 0x0060\r
+#define B1RXDQPICODER10 0x0064\r
+#define B0RXDQPICODER32 0x0068\r
+#define B0RXDQPICODER10 0x006C\r
+#define B01PTRCTL0 0x0070\r
+#define B01PTRCTL1 0x0074\r
+#define B01DBCTL0 0x0078\r
+#define B01DBCTL1 0x007C\r
+#define B0LATCTL0 0x0080\r
+#define B1LATCTL0 0x0084\r
+#define B01LATCTL1 0x0088\r
+#define B0ONDURCTL 0x008C\r
+#define B1ONDURCTL 0x0090\r
+#define B0OVRCTL 0x0094\r
+#define B1OVRCTL 0x0098\r
+#define DQCTL 0x009C\r
+#define B0RK2RKCHGPTRCTRL 0x00A0\r
+#define B1RK2RKCHGPTRCTRL 0x00A4\r
+#define DQRK2RKCTL 0x00A8\r
+#define DQRK2RKPTRCTL 0x00AC\r
+#define B0RK2RKLAT 0x00B0\r
+#define B1RK2RKLAT 0x00B4\r
+#define DQCLKALIGNREG0 0x00B8\r
+#define DQCLKALIGNREG1 0x00BC\r
+#define DQCLKALIGNREG2 0x00C0\r
+#define DQCLKALIGNSTS0 0x00C4\r
+#define DQCLKALIGNSTS1 0x00C8\r
+#define DQCLKGATE 0x00CC\r
+#define B0COMPSLV1 0x00D0\r
+#define B1COMPSLV1 0x00D4\r
+#define B0COMPSLV2 0x00D8\r
+#define B1COMPSLV2 0x00DC\r
+#define B0COMPSLV3 0x00E0\r
+#define B1COMPSLV3 0x00E4\r
+#define DQVISALANECR0TOP 0x00E8\r
+#define DQVISALANECR1TOP 0x00EC\r
+#define DQVISACONTROLCRTOP 0x00F0\r
+#define DQVISALANECR0BL 0x00F4\r
+#define DQVISALANECR1BL 0x00F8\r
+#define DQVISACONTROLCRBL 0x00FC\r
+#define DQTIMINGCTRL 0x010C\r
+// CH0-ECC\r
+#define ECCDLLTXCTL 0x2004\r
+#define ECCDLLRXCTL 0x2008\r
+#define ECCMDLLCTL 0x200C\r
+#define ECCB1DLLPICODER0 0x2038\r
+#define ECCB1DLLPICODER1 0x2040\r
+#define ECCB1DLLPICODER2 0x2048\r
+#define ECCB1DLLPICODER3 0x2050\r
+#define ECCB01DBCTL0 0x2078\r
+#define ECCB01DBCTL1 0x207C\r
+#define ECCCLKALIGNREG0 0x20B8\r
+#define ECCCLKALIGNREG1 0x20BC\r
+#define ECCCLKALIGNREG2 0x20C0\r
+// CH0-CMD\r
+#define CMDOBSCKEBBCTL 0x4800\r
+#define CMDDLLTXCTL 0x4808\r
+#define CMDDLLRXCTL 0x480C\r
+#define CMDMDLLCTL 0x4810\r
+#define CMDRCOMPODT 0x4814\r
+#define CMDDLLPICODER0 0x4820\r
+#define CMDDLLPICODER1 0x4824\r
+#define CMDCFGREG0 0x4840\r
+#define CMDPTRREG 0x4844\r
+#define CMDCLKALIGNREG0 0x4850\r
+#define CMDCLKALIGNREG1 0x4854\r
+#define CMDCLKALIGNREG2 0x4858\r
+#define CMDPMCONFIG0 0x485C\r
+#define CMDPMDLYREG0 0x4860\r
+#define CMDPMDLYREG1 0x4864\r
+#define CMDPMDLYREG2 0x4868\r
+#define CMDPMDLYREG3 0x486C\r
+#define CMDPMDLYREG4 0x4870\r
+#define CMDCLKALIGNSTS0 0x4874\r
+#define CMDCLKALIGNSTS1 0x4878\r
+#define CMDPMSTS0 0x487C\r
+#define CMDPMSTS1 0x4880\r
+#define CMDCOMPSLV 0x4884\r
+#define CMDBONUS0 0x488C\r
+#define CMDBONUS1 0x4890\r
+#define CMDVISALANECR0 0x4894\r
+#define CMDVISALANECR1 0x4898\r
+#define CMDVISACONTROLCR 0x489C\r
+#define CMDCLKGATE 0x48A0\r
+#define CMDTIMINGCTRL 0x48A4\r
+// CH0-CLK-CTL\r
+#define CCOBSCKEBBCTL 0x5800\r
+#define CCRCOMPIO 0x5804\r
+#define CCDLLTXCTL 0x5808\r
+#define CCDLLRXCTL 0x580C\r
+#define CCMDLLCTL 0x5810\r
+#define CCRCOMPODT 0x5814\r
+#define CCDLLPICODER0 0x5820\r
+#define CCDLLPICODER1 0x5824\r
+#define CCDDR3RESETCTL 0x5830\r
+#define CCCFGREG0 0x5838\r
+#define CCCFGREG1 0x5840\r
+#define CCPTRREG 0x5844\r
+#define CCCLKALIGNREG0 0x5850\r
+#define CCCLKALIGNREG1 0x5854\r
+#define CCCLKALIGNREG2 0x5858\r
+#define CCPMCONFIG0 0x585C\r
+#define CCPMDLYREG0 0x5860\r
+#define CCPMDLYREG1 0x5864\r
+#define CCPMDLYREG2 0x5868\r
+#define CCPMDLYREG3 0x586C\r
+#define CCPMDLYREG4 0x5870\r
+#define CCCLKALIGNSTS0 0x5874\r
+#define CCCLKALIGNSTS1 0x5878\r
+#define CCPMSTS0 0x587C\r
+#define CCPMSTS1 0x5880\r
+#define CCCOMPSLV1 0x5884\r
+#define CCCOMPSLV2 0x5888\r
+#define CCCOMPSLV3 0x588C\r
+#define CCBONUS0 0x5894\r
+#define CCBONUS1 0x5898\r
+#define CCVISALANECR0 0x589C\r
+#define CCVISALANECR1 0x58A0\r
+#define CCVISACONTROLCR 0x58A4\r
+#define CCCLKGATE 0x58A8\r
+#define CCTIMINGCTL 0x58AC\r
+// COMP\r
+#define CMPCTRL 0x6800\r
+#define SOFTRSTCNTL 0x6804\r
+#define MSCNTR 0x6808\r
+#define NMSCNTRL 0x680C\r
+#define LATCH1CTL 0x6814\r
+#define COMPVISALANECR0 0x681C\r
+#define COMPVISALANECR1 0x6820\r
+#define COMPVISACONTROLCR 0x6824\r
+#define COMPBONUS0 0x6830\r
+#define TCOCNTCTRL 0x683C\r
+#define DQANAODTPUCTL 0x6840\r
+#define DQANAODTPDCTL 0x6844\r
+#define DQANADRVPUCTL 0x6848\r
+#define DQANADRVPDCTL 0x684C\r
+#define DQANADLYPUCTL 0x6850\r
+#define DQANADLYPDCTL 0x6854\r
+#define DQANATCOPUCTL 0x6858\r
+#define DQANATCOPDCTL 0x685C\r
+#define CMDANADRVPUCTL 0x6868\r
+#define CMDANADRVPDCTL 0x686C\r
+#define CMDANADLYPUCTL 0x6870\r
+#define CMDANADLYPDCTL 0x6874\r
+#define CLKANAODTPUCTL 0x6880\r
+#define CLKANAODTPDCTL 0x6884\r
+#define CLKANADRVPUCTL 0x6888\r
+#define CLKANADRVPDCTL 0x688C\r
+#define CLKANADLYPUCTL 0x6890\r
+#define CLKANADLYPDCTL 0x6894\r
+#define CLKANATCOPUCTL 0x6898\r
+#define CLKANATCOPDCTL 0x689C\r
+#define DQSANAODTPUCTL 0x68A0\r
+#define DQSANAODTPDCTL 0x68A4\r
+#define DQSANADRVPUCTL 0x68A8\r
+#define DQSANADRVPDCTL 0x68AC\r
+#define DQSANADLYPUCTL 0x68B0\r
+#define DQSANADLYPDCTL 0x68B4\r
+#define DQSANATCOPUCTL 0x68B8\r
+#define DQSANATCOPDCTL 0x68BC\r
+#define CTLANADRVPUCTL 0x68C8\r
+#define CTLANADRVPDCTL 0x68CC\r
+#define CTLANADLYPUCTL 0x68D0\r
+#define CTLANADLYPDCTL 0x68D4\r
+#define CHNLBUFSTATIC 0x68F0\r
+#define COMPOBSCNTRL 0x68F4\r
+#define COMPBUFFDBG0 0x68F8\r
+#define COMPBUFFDBG1 0x68FC\r
+#define CFGMISCCH0 0x6900\r
+#define COMPEN0CH0 0x6904\r
+#define COMPEN1CH0 0x6908\r
+#define COMPEN2CH0 0x690C\r
+#define STATLEGEN0CH0 0x6910\r
+#define STATLEGEN1CH0 0x6914\r
+#define DQVREFCH0 0x6918\r
+#define CMDVREFCH0 0x691C\r
+#define CLKVREFCH0 0x6920\r
+#define DQSVREFCH0 0x6924\r
+#define CTLVREFCH0 0x6928\r
+#define TCOVREFCH0 0x692C\r
+#define DLYSELCH0 0x6930\r
+#define TCODRAMBUFODTCH0 0x6934\r
+#define CCBUFODTCH0 0x6938\r
+#define RXOFFSETCH0 0x693C\r
+#define DQODTPUCTLCH0 0x6940\r
+#define DQODTPDCTLCH0 0x6944\r
+#define DQDRVPUCTLCH0 0x6948\r
+#define DQDRVPDCTLCH0 0x694C\r
+#define DQDLYPUCTLCH0 0x6950\r
+#define DQDLYPDCTLCH0 0x6954\r
+#define DQTCOPUCTLCH0 0x6958\r
+#define DQTCOPDCTLCH0 0x695C\r
+#define CMDDRVPUCTLCH0 0x6968\r
+#define CMDDRVPDCTLCH0 0x696C\r
+#define CMDDLYPUCTLCH0 0x6970\r
+#define CMDDLYPDCTLCH0 0x6974\r
+#define CLKODTPUCTLCH0 0x6980\r
+#define CLKODTPDCTLCH0 0x6984\r
+#define CLKDRVPUCTLCH0 0x6988\r
+#define CLKDRVPDCTLCH0 0x698C\r
+#define CLKDLYPUCTLCH0 0x6990\r
+#define CLKDLYPDCTLCH0 0x6994\r
+#define CLKTCOPUCTLCH0 0x6998\r
+#define CLKTCOPDCTLCH0 0x699C\r
+#define DQSODTPUCTLCH0 0x69A0\r
+#define DQSODTPDCTLCH0 0x69A4\r
+#define DQSDRVPUCTLCH0 0x69A8\r
+#define DQSDRVPDCTLCH0 0x69AC\r
+#define DQSDLYPUCTLCH0 0x69B0\r
+#define DQSDLYPDCTLCH0 0x69B4\r
+#define DQSTCOPUCTLCH0 0x69B8\r
+#define DQSTCOPDCTLCH0 0x69BC\r
+#define CTLDRVPUCTLCH0 0x69C8\r
+#define CTLDRVPDCTLCH0 0x69CC\r
+#define CTLDLYPUCTLCH0 0x69D0\r
+#define CTLDLYPDCTLCH0 0x69D4\r
+#define FNLUPDTCTLCH0 0x69F0\r
+// PLL\r
+#define MPLLCTRL0 0x7800\r
+#define MPLLCTRL1 0x7808\r
+#define MPLLCSR0 0x7810\r
+#define MPLLCSR1 0x7814\r
+#define MPLLCSR2 0x7820\r
+#define MPLLDFT 0x7828\r
+#define MPLLMON0CTL 0x7830\r
+#define MPLLMON1CTL 0x7838\r
+#define MPLLMON2CTL 0x783C\r
+#define SFRTRIM 0x7850\r
+#define MPLLDFTOUT0 0x7858\r
+#define MPLLDFTOUT1 0x785C\r
+#define MASTERRSTN 0x7880\r
+#define PLLLOCKDEL 0x7884\r
+#define SFRDEL 0x7888\r
+#define CRUVISALANECR0 0x78F0\r
+#define CRUVISALANECR1 0x78F4\r
+#define CRUVISACONTROLCR 0x78F8\r
+#define IOSFVISALANECR0 0x78FC\r
+#define IOSFVISALANECR1 0x7900\r
+#define IOSFVISACONTROLCR 0x7904\r
+\r
+//\r
+// END DDRIO registers\r
+//\r
+////\r
+\r
+\r
+#endif\r
projects / mirror_edk2.git / blobdiff