QuarkSocPkg: Add new package for Quark SoC X1000

[mirror_edk2.git] / QuarkSocPkg / QuarkNorthCluster / MemoryInit / Pei / hte.h

diff --git a/QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei/hte.h b/QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei/hte.h
new file mode 100644 (file)
index 0000000..eeb6192
--- /dev/null
+++ b/QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei/hte.h
@@ -0,0 +1,72 @@
+/** @file\r
+HTE handling routines for MRC use.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution.  The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+#ifndef __HTE_H\r
+#define __HTE_H\r
+\r
+#define STATIC   static\r
+#define VOID     void\r
+\r
+#if !defined(__GNUC__) && (__STDC_VERSION__ < 199901L)\r
+typedef uint32_t UINT32;\r
+typedef uint16_t UINT16;\r
+typedef uint8_t UINT8;\r
+#endif\r
+\r
+typedef enum\r
+{\r
+  MrcNoHaltSystemOnError,\r
+  MrcHaltSystemOnError,\r
+  MrcHaltHteEngineOnError,\r
+  MrcNoHaltHteEngineOnError\r
+} HALT_TYPE;\r
+\r
+typedef enum\r
+{\r
+  MrcMemInit, MrcMemTest\r
+} MEM_INIT_OR_TEST;\r
+\r
+#define READ_TRAIN      1\r
+#define WRITE_TRAIN     2\r
+\r
+#define HTE_MEMTEST_NUM                 2\r
+#define HTE_LOOP_CNT                    5  // EXP_LOOP_CNT field of HTE_CMD_CTL. This CANNOT be less than 4\r
+#define HTE_LFSR_VICTIM_SEED   0xF294BA21  // Random seed for victim.\r
+#define HTE_LFSR_AGRESSOR_SEED 0xEBA7492D  // Random seed for aggressor.\r
+UINT32\r
+HteMemInit(\r
+    MRC_PARAMS *CurrentMrcData,\r
+    UINT8 MemInitFlag,\r
+    UINT8 HaltHteEngineOnError);\r
+\r
+UINT16\r
+BasicWriteReadHTE(\r
+    MRC_PARAMS *CurrentMrcData,\r
+    UINT32 Address,\r
+    UINT8 FirstRun,\r
+    UINT8 Mode);\r
+\r
+UINT16\r
+WriteStressBitLanesHTE(\r
+    MRC_PARAMS *CurrentMrcData,\r
+    UINT32 Address,\r
+    UINT8 FirstRun);\r
+\r
+VOID\r
+HteMemOp(\r
+    UINT32 Address,\r
+    UINT8 FirstRun,\r
+    UINT8 IsWrite);\r
+\r
+#endif\r