QuarkSocPkg: Add new package for Quark SoC X1000

[mirror_edk2.git] / QuarkSocPkg / QuarkNorthCluster / Smm / DxeSmm / QncSmmDispatcher / QNC / QNCSmmQncn.c

diff --git a/QuarkSocPkg/QuarkNorthCluster/Smm/DxeSmm/QncSmmDispatcher/QNC/QNCSmmQncn.c b/QuarkSocPkg/QuarkNorthCluster/Smm/DxeSmm/QncSmmDispatcher/QNC/QNCSmmQncn.c
new file mode 100644 (file)
index 0000000..53ee3ea
--- /dev/null
+++ b/QuarkSocPkg/QuarkNorthCluster/Smm/DxeSmm/QncSmmDispatcher/QNC/QNCSmmQncn.c
@@ -0,0 +1,217 @@
+/** @file\r
+File to contain all the hardware specific stuff for the Smm QNCn dispatch protocol.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution.  The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+**/\r
+\r
+//\r
+// Include common header file for this module.\r
+//\r
+#include "CommonHeader.h"\r
+\r
+#include "QNCSmmHelpers.h"\r
+\r
+QNC_SMM_SOURCE_DESC QNCN_SOURCE_DESCS[NUM_ICHN_TYPES] = {\r
+\r
+  // QNCnMch (0)\r
+  NULL_SOURCE_DESC_INITIALIZER,\r
+\r
+  // QNCnPme (1)\r
+  NULL_SOURCE_DESC_INITIALIZER,\r
+\r
+  // QNCnRtcAlarm (2)\r
+  {\r
+    QNC_SMM_NO_FLAGS,\r
+    {\r
+      {{ACPI_ADDR_TYPE, {R_QNC_PM1BLK_PM1E}}, S_QNC_PM1BLK_PM1E, N_QNC_PM1BLK_PM1E_RTC},\r
+      NULL_BIT_DESC_INITIALIZER\r
+    },\r
+    {\r
+      {{ACPI_ADDR_TYPE, {R_QNC_PM1BLK_PM1S}}, S_QNC_PM1BLK_PM1S, N_QNC_PM1BLK_PM1S_RTC}\r
+    }\r
+  },\r
+\r
+  // QNCnRingIndicate (3)\r
+  NULL_SOURCE_DESC_INITIALIZER,\r
+\r
+  // QNCnAc97Wake (4)\r
+  NULL_SOURCE_DESC_INITIALIZER,\r
+\r
+  // QNCnSerialIrq (5)\r
+  NULL_SOURCE_DESC_INITIALIZER,\r
+\r
+  // QNCnY2KRollover (6)\r
+  NULL_SOURCE_DESC_INITIALIZER,\r
+\r
+  // QNCnTcoTimeout (7)\r
+  NULL_SOURCE_DESC_INITIALIZER,\r
+\r
+  // QNCnOsTco (8)\r
+  NULL_SOURCE_DESC_INITIALIZER,\r
+\r
+  // QNCnNmi (9)\r
+  NULL_SOURCE_DESC_INITIALIZER,\r
+\r
+  // QNCnIntruderDetect (10)\r
+  NULL_SOURCE_DESC_INITIALIZER,\r
+\r
+  // QNCnBiosWp (11)\r
+  {\r
+    QNC_SMM_CLEAR_WITH_ZERO,\r
+    {\r
+      {\r
+        {\r
+          PCI_ADDR_TYPE,\r
+          {\r
+            (\r
+              (PCI_BUS_NUMBER_QNC << 24) |\r
+              (PCI_DEVICE_NUMBER_QNC_LPC << 16) |\r
+              (PCI_FUNCTION_NUMBER_QNC_LPC << 8) |\r
+              R_QNC_LPC_BIOS_CNTL\r
+            )\r
+          }\r
+        },\r
+        S_QNC_LPC_BIOS_CNTL,\r
+        N_QNC_LPC_BIOS_CNTL_BLE\r
+      },\r
+      NULL_BIT_DESC_INITIALIZER\r
+    },\r
+    {\r
+      {\r
+        {\r
+          PCI_ADDR_TYPE,\r
+          {\r
+            (\r
+              (PCI_BUS_NUMBER_QNC << 24) |\r
+              (PCI_DEVICE_NUMBER_QNC_LPC << 16) |\r
+              (PCI_FUNCTION_NUMBER_QNC_LPC << 8) |\r
+              R_QNC_LPC_BIOS_CNTL\r
+            )\r
+          }\r
+        },\r
+        S_QNC_LPC_BIOS_CNTL,\r
+        N_QNC_LPC_BIOS_CNTL_BIOSWE\r
+      }\r
+    }\r
+  },\r
+\r
+  // QNCnMcSmi (12)\r
+  NULL_SOURCE_DESC_INITIALIZER,\r
+\r
+  // QNCnPmeB0 (13)\r
+  NULL_SOURCE_DESC_INITIALIZER,\r
+\r
+  // QNCnThrmSts (14)\r
+  {\r
+    QNC_SMM_SCI_EN_DEPENDENT,\r
+    {\r
+      {{GPE_ADDR_TYPE, {R_QNC_GPE0BLK_GPE0E}}, S_QNC_GPE0BLK_GPE0E, N_QNC_GPE0BLK_GPE0E_THRM},\r
+      NULL_BIT_DESC_INITIALIZER\r
+    },\r
+    {\r
+      {{GPE_ADDR_TYPE, {R_QNC_GPE0BLK_GPE0S}}, S_QNC_GPE0BLK_GPE0S, N_QNC_GPE0BLK_GPE0S_THRM}\r
+    }\r
+  },\r
+\r
+  // QNCnSmBus (15)\r
+  NULL_SOURCE_DESC_INITIALIZER,\r
+\r
+  // QNCnIntelUsb2 (16)\r
+  NULL_SOURCE_DESC_INITIALIZER,\r
+\r
+  // QNCnMonSmi7 (17)\r
+  NULL_SOURCE_DESC_INITIALIZER,\r
+\r
+  // QNCnMonSmi6 (18)\r
+  NULL_SOURCE_DESC_INITIALIZER,\r
+\r
+  // QNCnMonSmi5 (19)\r
+  NULL_SOURCE_DESC_INITIALIZER,\r
+\r
+  // QNCnMonSmi4 (20)\r
+  NULL_SOURCE_DESC_INITIALIZER,\r
+\r
+  // QNCnDevTrap13 (21)\r
+  NULL_SOURCE_DESC_INITIALIZER,\r
+\r
+  // QNCnDevTrap12 (22)\r
+  NULL_SOURCE_DESC_INITIALIZER,\r
+\r
+  // QNCnDevTrap11 (23)\r
+  NULL_SOURCE_DESC_INITIALIZER,\r
+\r
+  // QNCnDevTrap10 (24)\r
+  NULL_SOURCE_DESC_INITIALIZER,\r
+\r
+  // QNCnDevTrap9 (25)\r
+  NULL_SOURCE_DESC_INITIALIZER,\r
+\r
+  // QNCnDevTrap8 (26)\r
+  NULL_SOURCE_DESC_INITIALIZER,\r
+\r
+  // QNCnDevTrap7 (27)\r
+  NULL_SOURCE_DESC_INITIALIZER,\r
+\r
+  // QNCnDevTrap6 (28)\r
+  NULL_SOURCE_DESC_INITIALIZER,\r
+\r
+  // QNCnDevTrap5 (29)\r
+  NULL_SOURCE_DESC_INITIALIZER,\r
+\r
+  // QNCnDevTrap3 (30)\r
+  NULL_SOURCE_DESC_INITIALIZER,\r
+\r
+  // QNCnDevTrap2 (31)\r
+  NULL_SOURCE_DESC_INITIALIZER,\r
+\r
+  // QNCnDevTrap1 (32)\r
+  NULL_SOURCE_DESC_INITIALIZER,\r
+\r
+  // QNCnDevTrap0 (33)\r
+  NULL_SOURCE_DESC_INITIALIZER,\r
+\r
+  // QNCnIoTrap3 (34)\r
+  NULL_SOURCE_DESC_INITIALIZER,\r
+\r
+  // QNCnIoTrap2 (35)\r
+  NULL_SOURCE_DESC_INITIALIZER,\r
+\r
+  // QNCnIoTrap1 (36)\r
+  NULL_SOURCE_DESC_INITIALIZER,\r
+\r
+  // QNCnIoTrap0 (37)\r
+  NULL_SOURCE_DESC_INITIALIZER,\r
+\r
+  // QNCnPciExpress (38)\r
+  NULL_SOURCE_DESC_INITIALIZER,\r
+\r
+  // QNCnMonitor (39)\r
+  NULL_SOURCE_DESC_INITIALIZER,\r
+\r
+  // QNCnSpi (40)\r
+  NULL_SOURCE_DESC_INITIALIZER,\r
+\r
+  // QNCnQRT (41)\r
+  NULL_SOURCE_DESC_INITIALIZER,\r
+\r
+  // QNCnGpioUnlock (42)\r
+  NULL_SOURCE_DESC_INITIALIZER\r
+};\r
+\r
+VOID\r
+QNCSmmQNCnClearSource(\r
+  QNC_SMM_SOURCE_DESC   *SrcDesc\r
+  )\r
+{\r
+    QNCSmmClearSource (SrcDesc);\r
+}\r