/** @file\r
TIS (TPM Interface Specification) functions used by dTPM2.0 library.\r
\r
-Copyright (c) 2013 - 2015, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2013 - 2016, Intel Corporation. All rights reserved.<BR>\r
(C) Copyright 2015 Hewlett Packard Enterprise Development LP<BR>\r
This program and the accompanying materials \r
are licensed and made available under the terms and conditions of the BSD License \r
#include <Library/Tpm2DeviceLib.h>\r
#include <Library/PcdLib.h>\r
\r
-//\r
-// Set structure alignment to 1-byte\r
-//\r
-#pragma pack (1)\r
-\r
-//\r
-// Register set map as specified in TIS specification Chapter 10\r
-//\r
-typedef struct {\r
- ///\r
- /// Used to gain ownership for this particular port.\r
- ///\r
- UINT8 Access; // 0\r
- UINT8 Reserved1[7]; // 1\r
- ///\r
- /// Controls interrupts.\r
- ///\r
- UINT32 IntEnable; // 8\r
- ///\r
- /// SIRQ vector to be used by the TPM.\r
- ///\r
- UINT8 IntVector; // 0ch\r
- UINT8 Reserved2[3]; // 0dh\r
- ///\r
- /// What caused interrupt.\r
- ///\r
- UINT32 IntSts; // 10h\r
- ///\r
- /// Shows which interrupts are supported by that particular TPM.\r
- ///\r
- UINT32 IntfCapability; // 14h\r
- ///\r
- /// Status Register. Provides status of the TPM.\r
- ///\r
- UINT8 Status; // 18h\r
- ///\r
- /// Number of consecutive writes that can be done to the TPM.\r
- ///\r
- UINT16 BurstCount; // 19h\r
- ///\r
- /// TPM2 support CANCEL at BIT[24] of STATUS register (WO)\r
- ///\r
- UINT8 StatusEx; // 1Bh\r
- UINT8 Reserved3[8];\r
- ///\r
- /// Read or write FIFO, depending on transaction.\r
- ///\r
- UINT32 DataFifo; // 24h\r
- UINT8 Reserved4[0xed8]; // 28h\r
- ///\r
- /// Vendor ID\r
- ///\r
- UINT16 Vid; // 0f00h\r
- ///\r
- /// Device ID\r
- ///\r
- UINT16 Did; // 0f02h\r
- ///\r
- /// Revision ID\r
- ///\r
- UINT8 Rid; // 0f04h\r
- ///\r
- /// TCG defined configuration registers.\r
- ///\r
- UINT8 TcgDefined[0x7b]; // 0f05h\r
- ///\r
- /// Alias to I/O legacy space.\r
- ///\r
- UINT32 LegacyAddress1; // 0f80h\r
- ///\r
- /// Additional 8 bits for I/O legacy space extension.\r
- ///\r
- UINT32 LegacyAddress1Ex; // 0f84h\r
- ///\r
- /// Alias to second I/O legacy space.\r
- ///\r
- UINT32 LegacyAddress2; // 0f88h\r
- ///\r
- /// Additional 8 bits for second I/O legacy space extension.\r
- ///\r
- UINT32 LegacyAddress2Ex; // 0f8ch\r
- ///\r
- /// Vendor-defined configuration registers.\r
- ///\r
- UINT8 VendorDefined[0x70];// 0f90h\r
-} TIS_PC_REGISTERS;\r
-\r
-//\r
-// Restore original structure alignment\r
-//\r
-#pragma pack ()\r
-\r
-//\r
-// Define pointer types used to access TIS registers on PC\r
-//\r
-typedef TIS_PC_REGISTERS *TIS_PC_REGISTERS_PTR;\r
-\r
-//\r
-// Define bits of ACCESS and STATUS registers\r
-//\r
-\r
-///\r
-/// This bit is a 1 to indicate that the other bits in this register are valid.\r
-///\r
-#define TIS_PC_VALID BIT7\r
-///\r
-/// Indicate that this locality is active.\r
-///\r
-#define TIS_PC_ACC_ACTIVE BIT5\r
-///\r
-/// Set to 1 to indicate that this locality had the TPM taken away while\r
-/// this locality had the TIS_PC_ACC_ACTIVE bit set.\r
-///\r
-#define TIS_PC_ACC_SEIZED BIT4\r
-///\r
-/// Set to 1 to indicate that TPM MUST reset the\r
-/// TIS_PC_ACC_ACTIVE bit and remove ownership for localities less than the\r
-/// locality that is writing this bit.\r
-///\r
-#define TIS_PC_ACC_SEIZE BIT3\r
-///\r
-/// When this bit is 1, another locality is requesting usage of the TPM.\r
-///\r
-#define TIS_PC_ACC_PENDIND BIT2\r
-///\r
-/// Set to 1 to indicate that this locality is requesting to use TPM.\r
-///\r
-#define TIS_PC_ACC_RQUUSE BIT1\r
-///\r
-/// A value of 1 indicates that a T/OS has not been established on the platform\r
-///\r
-#define TIS_PC_ACC_ESTABLISH BIT0\r
-\r
-///\r
-/// When this bit is 1, TPM is in the Ready state, \r
-/// indicating it is ready to receive a new command.\r
-///\r
-#define TIS_PC_STS_READY BIT6\r
-///\r
-/// Write a 1 to this bit to cause the TPM to execute that command.\r
-///\r
-#define TIS_PC_STS_GO BIT5\r
-///\r
-/// This bit indicates that the TPM has data available as a response.\r
-///\r
-#define TIS_PC_STS_DATA BIT4\r
-///\r
-/// The TPM sets this bit to a value of 1 when it expects another byte of data for a command.\r
-///\r
-#define TIS_PC_STS_EXPECT BIT3\r
-///\r
-/// Writes a 1 to this bit to force the TPM to re-send the response.\r
-///\r
-#define TIS_PC_STS_RETRY BIT1\r
-\r
-//\r
-// Default TimeOut value\r
-//\r
-#define TIS_TIMEOUT_A (1000 * 1000) // 1s\r
-#define TIS_TIMEOUT_B (2000 * 1000) // 2s\r
-#define TIS_TIMEOUT_C (1000 * 1000) // 1s\r
-#define TIS_TIMEOUT_D (1000 * 1000) // 1s\r
+#include <IndustryStandard/TpmTis.h>\r
\r
#define TIS_TIMEOUT_MAX (90000 * 1000) // 90s\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
-DTpm2SubmitCommand (\r
+DTpm2TisSubmitCommand (\r
IN UINT32 InputParameterBlockSize,\r
IN UINT8 *InputParameterBlock,\r
IN OUT UINT32 *OutputParameterBlockSize,\r
**/\r
EFI_STATUS\r
EFIAPI\r
-DTpm2RequestUseTpm (\r
+DTpm2TisRequestUseTpm (\r
VOID\r
)\r
{\r
projects / mirror_edk2.git / blobdiff