--- /dev/null
+/** @file\r
+ The TPM2 definition block in ACPI table for TCG2 physical presence\r
+ and MemoryClear.\r
+\r
+Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>\r
+(c)Copyright 2016 HP Development Company, L.P.<BR>\r
+Copyright (c) Microsoft Corporation.<BR>\r
+SPDX-License-Identifier: BSD-2-Clause-Patent\r
+\r
+**/\r
+\r
+DefinitionBlock (\r
+ "Tpm.aml",\r
+ "SSDT",\r
+ 2,\r
+ "INTEL ",\r
+ "Tpm2Tabl",\r
+ 0x1000\r
+ )\r
+{\r
+ Scope (\_SB)\r
+ {\r
+ Device (TPM)\r
+ {\r
+ //\r
+ // TCG2\r
+ //\r
+\r
+ //\r
+ // TAG for patching TPM2.0 _HID\r
+ //\r
+ Name (_HID, "NNNN0000")\r
+\r
+ Name (_CID, "MSFT0101")\r
+\r
+ //\r
+ // Readable name of this device, don't know if this way is correct yet\r
+ //\r
+ Name (_STR, Unicode ("TPM 2.0 Device"))\r
+\r
+ //\r
+ // Operational region for Smi port access\r
+ //\r
+ OperationRegion (SMIP, SystemIO, FixedPcdGet16 (PcdSmiCommandIoPort), 1)\r
+ Field (SMIP, ByteAcc, NoLock, Preserve)\r
+ {\r
+ IOPN, 8\r
+ }\r
+\r
+ //\r
+ // Operational region for TPM access\r
+ //\r
+ OperationRegion (TPMR, SystemMemory, 0xfed40000, 0x5000)\r
+ Field (TPMR, AnyAcc, NoLock, Preserve)\r
+ {\r
+ ACC0, 8, // TPM_ACCESS_0\r
+ Offset(0x8),\r
+ INTE, 32, // TPM_INT_ENABLE_0\r
+ INTV, 8, // TPM_INT_VECTOR_0\r
+ Offset(0x10),\r
+ INTS, 32, // TPM_INT_STATUS_0\r
+ INTF, 32, // TPM_INTF_CAPABILITY_0\r
+ STS0, 32, // TPM_STS_0\r
+ Offset(0x24),\r
+ FIFO, 32, // TPM_DATA_FIFO_0\r
+ Offset(0x30),\r
+ TID0, 32, // TPM_INTERFACE_ID_0\r
+ // ignore the rest\r
+ }\r
+\r
+ //\r
+ // Operational region for TPM support, TPM Physical Presence and TPM Memory Clear\r
+ // Region Offset 0xFFFF0000 and Length 0xF0 will be fixed in C code.\r
+ //\r
+ OperationRegion (TNVS, SystemMemory, 0xFFFF0000, 0xF0)\r
+ Field (TNVS, AnyAcc, NoLock, Preserve)\r
+ {\r
+ PPIN, 8, // Software SMI for Physical Presence Interface\r
+ PPIP, 32, // Used for save physical presence parameter\r
+ PPRP, 32, // Physical Presence request operation response\r
+ PPRQ, 32, // Physical Presence request operation\r
+ PPRM, 32, // Physical Presence request operation parameter\r
+ LPPR, 32, // Last Physical Presence request operation\r
+ FRET, 32, // Physical Presence function return code\r
+ MCIN, 8, // Software SMI for Memory Clear Interface\r
+ MCIP, 32, // Used for save the Mor parameter\r
+ MORD, 32, // Memory Overwrite Request Data\r
+ MRET, 32, // Memory Overwrite function return code\r
+ UCRQ, 32, // Physical Presence request operation to Get User Confirmation Status\r
+ IRQN, 32, // IRQ Number for _CRS\r
+ SFRB, 8 // Is shortformed Pkglength for resource buffer\r
+ }\r
+\r
+ //\r
+ // Possible resource settings returned by _PRS method\r
+ // RESS : ResourceTemplate with PkgLength <=63\r
+ // RESL : ResourceTemplate with PkgLength > 63\r
+ //\r
+ // The format of the data has to follow the same format as\r
+ // _CRS (according to ACPI spec).\r
+ //\r
+ Name (RESS, ResourceTemplate() {\r
+ Memory32Fixed (ReadWrite, 0xfed40000, 0x5000)\r
+ Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , , ) {1,2,3,4,5,6,7,8,9,10}\r
+ })\r
+\r
+ Name (RESL, ResourceTemplate() {\r
+ Memory32Fixed (ReadWrite, 0xfed40000, 0x5000)\r
+ Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , , ) {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15}\r
+ })\r
+\r
+ //\r
+ // Current resource settings for _CRS method\r
+ //\r
+ Name(RES0, ResourceTemplate () {\r
+ Memory32Fixed (ReadWrite, 0xfed40000, 0x5000, REG0)\r
+ Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , , INTR) {12}\r
+ })\r
+\r
+ Name(RES1, ResourceTemplate () {\r
+ Memory32Fixed (ReadWrite, 0xfed40000, 0x5000, REG1)\r
+ })\r
+\r
+\r
+ //\r
+ // Return the resource consumed by TPM device.\r
+ //\r
+ Method(_CRS,0,Serialized)\r
+ {\r
+ //\r
+ // IRQNum = 0 means disable IRQ support\r
+ //\r
+ If (LEqual(IRQN, 0)) {\r
+ Return (RES1)\r
+ }\r
+ Else\r
+ {\r
+ CreateDWordField(RES0, ^INTR._INT, LIRQ)\r
+ Store(IRQN, LIRQ)\r
+ Return (RES0)\r
+ }\r
+ }\r
+\r
+ //\r
+ // Set resources consumed by the TPM device. This is used to\r
+ // assign an interrupt number to the device. The input byte stream\r
+ // has to be the same as returned by _CRS (according to ACPI spec).\r
+ //\r
+ // Platform may choose to override this function with specific interrupt\r
+ // programing logic to replace FIFO/TIS SIRQ registers programing\r
+ //\r
+ Method(_SRS,1,Serialized)\r
+ {\r
+ //\r
+ // Do not configure Interrupt if IRQ Num is configured 0 by default\r
+ //\r
+ If (LNotEqual(IRQN, 0)) {\r
+ //\r
+ // Update resource descriptor\r
+ // Use the field name to identify the offsets in the argument\r
+ // buffer and RES0 buffer.\r
+ //\r
+ CreateDWordField(Arg0, ^INTR._INT, IRQ0)\r
+ CreateDWordField(RES0, ^INTR._INT, LIRQ)\r
+ Store(IRQ0, LIRQ)\r
+ Store(IRQ0, IRQN)\r
+\r
+ CreateBitField(Arg0, ^INTR._HE, ITRG)\r
+ CreateBitField(RES0, ^INTR._HE, LTRG)\r
+ Store(ITRG, LTRG)\r
+\r
+ CreateBitField(Arg0, ^INTR._LL, ILVL)\r
+ CreateBitField(RES0, ^INTR._LL, LLVL)\r
+ Store(ILVL, LLVL)\r
+\r
+ //\r
+ // Update TPM FIFO PTP/TIS interface only, identified by TPM_INTERFACE_ID_x lowest\r
+ // nibble.\r
+ // 0000 - FIFO interface as defined in PTP for TPM 2.0 is active\r
+ // 1111 - FIFO interface as defined in TIS1.3 is active\r
+ //\r
+ If (LOr(LEqual (And (TID0, 0x0F), 0x00), LEqual (And (TID0, 0x0F), 0x0F))) {\r
+ //\r
+ // If FIFO interface, interrupt vector register is\r
+ // available. TCG PTP specification allows only\r
+ // values 1..15 in this field. For other interrupts\r
+ // the field should stay 0.\r
+ //\r
+ If (LLess (IRQ0, 16)) {\r
+ Store (And(IRQ0, 0xF), INTV)\r
+ }\r
+ //\r
+ // Interrupt enable register (TPM_INT_ENABLE_x) bits 3:4\r
+ // contains settings for interrupt polarity.\r
+ // The other bits of the byte enable individual interrupts.\r
+ // They should be all be zero, but to avoid changing the\r
+ // configuration, the other bits are be preserved.\r
+ // 00 - high level\r
+ // 01 - low level\r
+ // 10 - rising edge\r
+ // 11 - falling edge\r
+ //\r
+ // ACPI spec definitions:\r
+ // _HE: '1' is Edge, '0' is Level\r
+ // _LL: '1' is ActiveHigh, '0' is ActiveLow (inverted from TCG spec)\r
+ //\r
+ If (LEqual (ITRG, 1)) {\r
+ Or(INTE, 0x00000010, INTE)\r
+ } Else {\r
+ And(INTE, 0xFFFFFFEF, INTE)\r
+ }\r
+ if (LEqual (ILVL, 0)) {\r
+ Or(INTE, 0x00000008, INTE)\r
+ } Else {\r
+ And(INTE, 0xFFFFFFF7, INTE)\r
+ }\r
+ }\r
+ }\r
+ }\r
+\r
+ Method(_PRS,0,Serialized)\r
+ {\r
+ //\r
+ // IRQNum = 0 means disable IRQ support\r
+ //\r
+ If (LEqual(IRQN, 0)) {\r
+ Return (RES1)\r
+ } ElseIf(LEqual(SFRB, 0)) {\r
+ //\r
+ // Long format. Possible resources PkgLength > 63\r
+ //\r
+ Return (RESL)\r
+ } Else {\r
+ //\r
+ // Short format. Possible resources PkgLength <=63\r
+ //\r
+ Return (RESS)\r
+ }\r
+ }\r
+\r
+ Method (PTS, 1, Serialized)\r
+ {\r
+ //\r
+ // Detect Sx state for MOR, only S4, S5 need to handle\r
+ //\r
+ If (LAnd (LLess (Arg0, 6), LGreater (Arg0, 3)))\r
+ {\r
+ //\r
+ // Bit4 -- DisableAutoDetect. 0 -- Firmware MAY autodetect.\r
+ //\r
+ If (LNot (And (MORD, 0x10)))\r
+ {\r
+ //\r
+ // Trigger the SMI through ACPI _PTS method.\r
+ //\r
+ Store (0x02, MCIP)\r
+\r
+ //\r
+ // Trigger the SMI interrupt\r
+ //\r
+ Store (MCIN, IOPN)\r
+ }\r
+ }\r
+ Return (0)\r
+ }\r
+\r
+ Method (_STA, 0)\r
+ {\r
+ if (LEqual (ACC0, 0xff))\r
+ {\r
+ Return (0)\r
+ }\r
+ Return (0x0f)\r
+ }\r
+\r
+ //\r
+ // TCG Hardware Information\r
+ //\r
+ Method (HINF, 1, Serialized, 0, {BuffObj, PkgObj}, {UnknownObj}) // IntObj\r
+ {\r
+ //\r
+ // Switch by function index\r
+ //\r
+ Switch (ToInteger(Arg0))\r
+ {\r
+ Case (0)\r
+ {\r
+ //\r
+ // Standard query\r
+ //\r
+ Return (Buffer () {0x03})\r
+ }\r
+ Case (1)\r
+ {\r
+ //\r
+ // Return failure if no TPM present\r
+ //\r
+ Name(TPMV, Package () {0x01, Package () {0x2, 0x0}})\r
+ if (LEqual (_STA (), 0x00))\r
+ {\r
+ Return (Package () {0x00})\r
+ }\r
+\r
+ //\r
+ // Return TPM version\r
+ //\r
+ Return (TPMV)\r
+ }\r
+ Default {BreakPoint}\r
+ }\r
+ Return (Buffer () {0})\r
+ }\r
+\r
+ Name(TPM2, Package (0x02){\r
+ Zero,\r
+ Zero\r
+ })\r
+\r
+ Name(TPM3, Package (0x03){\r
+ Zero,\r
+ Zero,\r
+ Zero\r
+ })\r
+\r
+ //\r
+ // TCG Physical Presence Interface\r
+ //\r
+ Method (TPPI, 2, Serialized, 0, {BuffObj, PkgObj, IntObj, StrObj}, {UnknownObj, UnknownObj}) // IntObj, PkgObj\r
+ {\r
+ //\r
+ // Switch by function index\r
+ //\r
+ Switch (ToInteger(Arg0))\r
+ {\r
+ Case (0)\r
+ {\r
+ //\r
+ // Standard query, supports function 1-8\r
+ //\r
+ Return (Buffer () {0xFF, 0x01})\r
+ }\r
+ Case (1)\r
+ {\r
+ //\r
+ // a) Get Physical Presence Interface Version\r
+ //\r
+ Return ("$PV")\r
+ }\r
+ Case (2)\r
+ {\r
+ //\r
+ // b) Submit TPM Operation Request to Pre-OS Environment\r
+ //\r
+\r
+ Store (DerefOf (Index (Arg1, 0x00)), PPRQ)\r
+ Store (0, PPRM)\r
+ Store (0x02, PPIP)\r
+\r
+ //\r
+ // Trigger the SMI interrupt\r
+ //\r
+ Store (PPIN, IOPN)\r
+ Return (FRET)\r
+\r
+\r
+ }\r
+ Case (3)\r
+ {\r
+ //\r
+ // c) Get Pending TPM Operation Requested By the OS\r
+ //\r
+\r
+ Store (PPRQ, Index (TPM2, 0x01))\r
+ Return (TPM2)\r
+ }\r
+ Case (4)\r
+ {\r
+ //\r
+ // d) Get Platform-Specific Action to Transition to Pre-OS Environment\r
+ //\r
+ Return (2)\r
+ }\r
+ Case (5)\r
+ {\r
+ //\r
+ // e) Return TPM Operation Response to OS Environment\r
+ //\r
+ Store (0x05, PPIP)\r
+\r
+ //\r
+ // Trigger the SMI interrupt\r
+ //\r
+ Store (PPIN, IOPN)\r
+\r
+ Store (LPPR, Index (TPM3, 0x01))\r
+ Store (PPRP, Index (TPM3, 0x02))\r
+\r
+ Return (TPM3)\r
+ }\r
+ Case (6)\r
+ {\r
+\r
+ //\r
+ // f) Submit preferred user language (Not implemented)\r
+ //\r
+\r
+ Return (3)\r
+\r
+ }\r
+ Case (7)\r
+ {\r
+ //\r
+ // g) Submit TPM Operation Request to Pre-OS Environment 2\r
+ //\r
+ Store (7, PPIP)\r
+ Store (DerefOf (Index (Arg1, 0x00)), PPRQ)\r
+ Store (0, PPRM)\r
+ If (LEqual (PPRQ, 23)) {\r
+ Store (DerefOf (Index (Arg1, 0x01)), PPRM)\r
+ }\r
+\r
+ //\r
+ // Trigger the SMI interrupt\r
+ //\r
+ Store (PPIN, IOPN)\r
+ Return (FRET)\r
+ }\r
+ Case (8)\r
+ {\r
+ //\r
+ // e) Get User Confirmation Status for Operation\r
+ //\r
+ Store (8, PPIP)\r
+ Store (DerefOf (Index (Arg1, 0x00)), UCRQ)\r
+\r
+ //\r
+ // Trigger the SMI interrupt\r
+ //\r
+ Store (PPIN, IOPN)\r
+\r
+ Return (FRET)\r
+ }\r
+\r
+ Default {BreakPoint}\r
+ }\r
+ Return (1)\r
+ }\r
+\r
+ Method (TMCI, 2, Serialized, 0, IntObj, {UnknownObj, UnknownObj}) // IntObj, PkgObj\r
+ {\r
+ //\r
+ // Switch by function index\r
+ //\r
+ Switch (ToInteger (Arg0))\r
+ {\r
+ Case (0)\r
+ {\r
+ //\r
+ // Standard query, supports function 1-1\r
+ //\r
+ Return (Buffer () {0x03})\r
+ }\r
+ Case (1)\r
+ {\r
+ //\r
+ // Save the Operation Value of the Request to MORD (reserved memory)\r
+ //\r
+ Store (DerefOf (Index (Arg1, 0x00)), MORD)\r
+\r
+ //\r
+ // Trigger the SMI through ACPI _DSM method.\r
+ //\r
+ Store (0x01, MCIP)\r
+\r
+ //\r
+ // Trigger the SMI interrupt\r
+ //\r
+ Store (MCIN, IOPN)\r
+ Return (MRET)\r
+ }\r
+ Default {BreakPoint}\r
+ }\r
+ Return (1)\r
+ }\r
+\r
+ Method (_DSM, 4, Serialized, 0, UnknownObj, {BuffObj, IntObj, IntObj, PkgObj})\r
+ {\r
+\r
+ //\r
+ // TCG Hardware Information\r
+ //\r
+ If(LEqual(Arg0, ToUUID ("cf8e16a5-c1e8-4e25-b712-4f54a96702c8")))\r
+ {\r
+ Return (HINF (Arg2))\r
+ }\r
+\r
+ //\r
+ // TCG Physical Presence Interface\r
+ //\r
+ If(LEqual(Arg0, ToUUID ("3dddfaa6-361b-4eb4-a424-8d10089d1653")))\r
+ {\r
+ Return (TPPI (Arg2, Arg3))\r
+ }\r
+\r
+ //\r
+ // TCG Memory Clear Interface\r
+ //\r
+ If(LEqual(Arg0, ToUUID ("376054ed-cc13-4675-901c-4756d7f2d45d")))\r
+ {\r
+ Return (TMCI (Arg2, Arg3))\r
+ }\r
+\r
+ Return (Buffer () {0})\r
+ }\r
+ }\r
+ }\r
+}\r
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