Update the comments in function headers to follow Doxygen special documentation block...

[mirror_edk2.git] / ShellPkg / Library / UefiShellDebug1CommandsLib / Pci.c

diff --git a/ShellPkg/Library/UefiShellDebug1CommandsLib/Pci.c b/ShellPkg/Library/UefiShellDebug1CommandsLib/Pci.c
index 6c333ca2f99b5c9e75359e3ee24611aed7265fef..470f870065531d1159c89ba0cff69346dd66ed57 100644 (file)
--- a/ShellPkg/Library/UefiShellDebug1CommandsLib/Pci.c
+++ b/ShellPkg/Library/UefiShellDebug1CommandsLib/Pci.c
@@ -1492,6 +1492,7 @@ PciGetNextBusRange (
   @param[in] ConfigSpace     Data in PCI configuration space.\r
   @param[in] Address         Address used to access configuration space of this PCI device.\r
   @param[in] IoDev           Handle used to access configuration space of PCI device.\r
+  @param[in] EnhancedDump    The print format for the dump data.\r
 \r
   @retval EFI_SUCCESS     The command completed successfully.\r
 **/\r
@@ -1618,11 +1619,12 @@ PciExplainBridgeControl (
 /**\r
   Print each capability structure.\r
 \r
-  @param[in] IoDev      The pointer to the deivce.\r
-  @param[in] Address    The address to start at.\r
-  @param[in] CapPtr     The offset from the address.\r
+  @param[in] IoDev            The pointer to the deivce.\r
+  @param[in] Address          The address to start at.\r
+  @param[in] CapPtr           The offset from the address.\r
+  @param[in] EnhancedDump     The print format for the dump data.\r
 \r
-  @retval EFI_SUCCESS     The operation was successful.\r
+  @retval EFI_SUCCESS         The operation was successful.\r
 **/\r
 EFI_STATUS\r
 PciExplainCapabilityStruct (\r
@@ -1635,9 +1637,13 @@ PciExplainCapabilityStruct (
 /**\r
   Display Pcie device structure.\r
 \r
-  @param[in] IoDev          The pointer to the root pci protocol.\r
-  @param[in] Address        The Address to start at.\r
-  @param[in] CapabilityPtr  The offset from the address to start.\r
+  @param[in] IoDev            The pointer to the root pci protocol.\r
+  @param[in] Address          The Address to start at.\r
+  @param[in] CapabilityPtr    The offset from the address to start.\r
+  @param[in] EnhancedDump     The print format for the dump data.\r
+  \r
+  @retval EFI_SUCCESS           The command completed successfully.\r
+  @retval @retval EFI_SUCCESS   Pci express extend space IO is not suppoted.   \r
 **/\r
 EFI_STATUS\r
 PciExplainPciExpress (\r
@@ -2660,6 +2666,7 @@ PciGetNextBusRange (
   @param[in] ConfigSpace     Data in PCI configuration space.\r
   @param[in] Address         Address used to access configuration space of this PCI device.\r
   @param[in] IoDev           Handle used to access configuration space of PCI device.\r
+  @param[in] EnhancedDump    The print format for the dump data.\r
 \r
   @retval EFI_SUCCESS     The command completed successfully.\r
 **/\r
@@ -3790,9 +3797,10 @@ PciExplainBridgeControl (
 /**\r
   Print each capability structure.\r
 \r
-  @param[in] IoDev      The pointer to the deivce.\r
-  @param[in] Address    The address to start at.\r
-  @param[in] CapPtr     The offset from the address.\r
+  @param[in] IoDev            The pointer to the deivce.\r
+  @param[in] Address          The address to start at.\r
+  @param[in] CapPtr           The offset from the address.\r
+  @param[in] EnhancedDump     The print format for the dump data.\r
 \r
   @retval EFI_SUCCESS     The operation was successful.\r
 **/\r
@@ -5274,66 +5282,48 @@ PrintPciExtendedCapabilityDetails(
   switch (HeaderAddress->CapabilityId){\r
     case PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_ID:\r
       return PrintInterpretedExtendedCompatibilityAer(HeaderAddress, HeadersBaseAddress);\r
-      break;\r
     case PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_CONTROL_ID:\r
       return PrintInterpretedExtendedCompatibilityLinkControl(HeaderAddress, HeadersBaseAddress);\r
-      break;\r
     case PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_ID:\r
       return PrintInterpretedExtendedCompatibilityLinkDeclaration(HeaderAddress, HeadersBaseAddress);\r
-      break;\r
     case PCI_EXPRESS_EXTENDED_CAPABILITY_SERIAL_NUMBER_ID:\r
       return PrintInterpretedExtendedCompatibilitySerialNumber(HeaderAddress, HeadersBaseAddress);\r
-      break;\r
     case PCI_EXPRESS_EXTENDED_CAPABILITY_POWER_BUDGETING_ID:\r
       return PrintInterpretedExtendedCompatibilityPowerBudgeting(HeaderAddress, HeadersBaseAddress);\r
-      break;\r
     case PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_ID:\r
       return PrintInterpretedExtendedCompatibilityAcs(HeaderAddress, HeadersBaseAddress);\r
-      break;\r
     case PCI_EXPRESS_EXTENDED_CAPABILITY_LATENCE_TOLERANCE_REPORTING_ID:\r
       return PrintInterpretedExtendedCompatibilityLatencyToleranceReporting(HeaderAddress, HeadersBaseAddress);\r
-      break;\r
     case PCI_EXPRESS_EXTENDED_CAPABILITY_ARI_CAPABILITY_ID:\r
       return PrintInterpretedExtendedCompatibilityAri(HeaderAddress, HeadersBaseAddress);\r
-      break;\r
     case PCI_EXPRESS_EXTENDED_CAPABILITY_RCRB_HEADER_ID:\r
       return PrintInterpretedExtendedCompatibilityRcrb(HeaderAddress, HeadersBaseAddress);\r
-      break;\r
     case PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_ID:\r
       return PrintInterpretedExtendedCompatibilityVendorSpecific(HeaderAddress, HeadersBaseAddress);\r
-      break;\r
     case PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_ID:\r
       return PrintInterpretedExtendedCompatibilityDynamicPowerAllocation(HeaderAddress, HeadersBaseAddress);\r
-      break;\r
     case PCI_EXPRESS_EXTENDED_CAPABILITY_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION_ID:\r
       return PrintInterpretedExtendedCompatibilityECEA(HeaderAddress, HeadersBaseAddress);\r
-      break;\r
     case PCI_EXPRESS_EXTENDED_CAPABILITY_VIRTUAL_CHANNEL_ID:\r
     case PCI_EXPRESS_EXTENDED_CAPABILITY_MULTI_FUNCTION_VIRTUAL_CHANNEL_ID:\r
       return PrintInterpretedExtendedCompatibilityVirtualChannel(HeaderAddress, HeadersBaseAddress);\r
-      break;\r
     case PCI_EXPRESS_EXTENDED_CAPABILITY_MULTICAST_ID: \r
       //\r
       // should only be present if PCIE_CAP_DEVICEPORT_TYPE(PciExpressCapPtr->PcieCapReg) == 0100b, 0101b, or 0110b\r
       //\r
       return PrintInterpretedExtendedCompatibilityMulticast(HeaderAddress, HeadersBaseAddress, PciExpressCapPtr);\r
-      break;\r
     case PCI_EXPRESS_EXTENDED_CAPABILITY_RESIZABLE_BAR_ID:\r
       return PrintInterpretedExtendedCompatibilityResizeableBar(HeaderAddress, HeadersBaseAddress);\r
-      break;\r
     case PCI_EXPRESS_EXTENDED_CAPABILITY_TPH_ID:\r
       return PrintInterpretedExtendedCompatibilityTph(HeaderAddress, HeadersBaseAddress);\r
-      break;\r
     case PCI_EXPRESS_EXTENDED_CAPABILITY_SECONDARY_PCIE_ID:\r
       return PrintInterpretedExtendedCompatibilitySecondary(HeaderAddress, HeadersBaseAddress, PciExpressCapPtr);\r
-      break;\r
     default:\r
       ShellPrintEx (-1, -1,\r
         L"Unknown PCIe extended capability ID (%04xh).  No interpretation available.\r\n",\r
         HeaderAddress->CapabilityId\r
         );\r
       return EFI_SUCCESS;\r
-      break;\r
   };\r
 \r
 }\r
@@ -5344,6 +5334,8 @@ PrintPciExtendedCapabilityDetails(
   @param[in] IoDev          The pointer to the root pci protocol.\r
   @param[in] Address        The Address to start at.\r
   @param[in] CapabilityPtr  The offset from the address to start.\r
+  @param[in] EnhancedDump   The print format for the dump data.\r
+  \r
 **/\r
 EFI_STATUS\r
 PciExplainPciExpress (\r