/** @file\r
Main file for Pci shell Debug1 function.\r
\r
- Copyright (c) 2005 - 2010, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2013 Hewlett-Packard Development Company, L.P.\r
+ Copyright (c) 2005 - 2014, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
}\r
};\r
\r
-#define EFI_HEX_DISP_SIZE 32\r
-BOOLEAN\r
-PrivateDumpHex (\r
- IN UINTN Indent,\r
- IN UINTN Offset,\r
- IN UINTN DataSize,\r
- IN VOID *UserData\r
- )\r
-/*++\r
-\r
-Routine Description:\r
-\r
- Add page break feature to the DumpHex\r
-\r
-Arguments:\r
- Indent - The indent space\r
-\r
- Offset - The offset\r
-\r
- DataSize - The data size\r
-\r
- UserData - The data\r
-\r
-Returns:\r
-\r
- TRUE - The dump is broke\r
- FALSE - The dump is completed\r
-\r
-**/\r
-{\r
- UINTN DispSize;\r
- UINT8 *DispData;\r
-\r
- DispSize = EFI_HEX_DISP_SIZE;\r
- DispData = (UINT8 *) UserData;\r
-\r
- while (DataSize!=0) {\r
- if (ShellGetExecutionBreakFlag ()) {\r
- return TRUE;\r
- }\r
-\r
- if (DataSize > EFI_HEX_DISP_SIZE) {\r
- DataSize -= EFI_HEX_DISP_SIZE;\r
- } else {\r
- DispSize = DataSize;\r
- DataSize = 0;\r
- }\r
-\r
- DumpHex (Indent, Offset + DispData - (UINT8 *) UserData, DispSize, DispData);\r
- DispData += DispSize;\r
- }\r
-\r
- return FALSE;\r
-}\r
-\r
-//\r
-// Implemetations\r
-//\r
-VOID\r
-PciGetClassStrings (\r
- IN UINT32 ClassCode,\r
- IN OUT PCI_CLASS_STRINGS *ClassStrings\r
- )\r
-/*++\r
-Routine Description:\r
\r
+/**\r
Generates printable Unicode strings that represent PCI device class,\r
subclass and programmed I/F based on a value passed to the function.\r
\r
-Arguments:\r
-\r
- ClassCode Value representing the PCI "Class Code" register read from a\r
+ @param[in] ClassCode Value representing the PCI "Class Code" register read from a\r
PCI device. The encodings are:\r
bits 23:16 - Base Class Code\r
bits 15:8 - Sub-Class Code\r
bits 7:0 - Programming Interface\r
- ClassStrings Pointer of PCI_CLASS_STRINGS structure, which contains\r
+ @param[in, out] ClassStrings Pointer of PCI_CLASS_STRINGS structure, which contains\r
printable class strings corresponding to ClassCode. The\r
caller must not modify the strings that are pointed by\r
the fields in ClassStrings.\r
-Returns:\r
-\r
- None\r
**/\r
+VOID\r
+PciGetClassStrings (\r
+ IN UINT32 ClassCode,\r
+ IN OUT PCI_CLASS_STRINGS *ClassStrings\r
+ )\r
{\r
INTN Index;\r
UINT8 Code;\r
return ;\r
}\r
\r
+/**\r
+ Print strings that represent PCI device class, subclass and programmed I/F.\r
+\r
+ @param[in] ClassCodePtr Points to the memory which stores register Class Code in PCI\r
+ configuation space.\r
+ @param[in] IncludePIF If the printed string should include the programming I/F part\r
+**/\r
VOID\r
PciPrintClassCode (\r
IN UINT8 *ClassCodePtr,\r
IN BOOLEAN IncludePIF\r
)\r
-/*++\r
-Routine Description:\r
-\r
- Print strings that represent PCI device class, subclass and programmed I/F\r
-\r
-Arguments:\r
-\r
- ClassCodePtr Points to the memory which stores register Class Code in PCI\r
- configuation space.\r
- IncludePIF If the printed string should include the programming I/F part\r
-Returns:\r
-\r
- None\r
-**/\r
{\r
UINT32 ClassCode;\r
PCI_CLASS_STRINGS ClassStrings;\r
- CHAR16 OutputString[PCI_CLASS_STRING_LIMIT + 1];\r
\r
ClassCode = 0;\r
ClassCode |= ClassCodePtr[0];\r
\r
if (IncludePIF) {\r
//\r
- // Only print base class and sub class name\r
+ // Print base class, sub class, and programming inferface name\r
//\r
- ShellPrintEx(-1,-1, L"%s - %s - %s",\r
+ ShellPrintEx (-1, -1, L"%s - %s - %s",\r
ClassStrings.BaseClass,\r
ClassStrings.SubClass,\r
ClassStrings.PIFClass\r
\r
} else {\r
//\r
- // Print base class, sub class, and programming inferface name\r
+ // Only print base class and sub class name\r
//\r
- UnicodeSPrint (\r
- OutputString,\r
- PCI_CLASS_STRING_LIMIT * sizeof (CHAR16),\r
- L"%s - %s",\r
+ ShellPrintEx (-1, -1, L"%s - %s",\r
ClassStrings.BaseClass,\r
ClassStrings.SubClass\r
- );\r
-\r
- OutputString[PCI_CLASS_STRING_LIMIT] = 0;\r
- ShellPrintEx(-1,-1, L"%s", OutputString);\r
+ );\r
}\r
}\r
\r
-EFI_STATUS\r
-PciDump (\r
- IN EFI_HANDLE ImageHandle,\r
- IN EFI_SYSTEM_TABLE *SystemTable\r
- );\r
+/**\r
+ This function finds out the protocol which is in charge of the given\r
+ segment, and its bus range covers the current bus number. It lookes\r
+ each instances of RootBridgeIoProtocol handle, until the one meets the\r
+ criteria is found.\r
+\r
+ @param[in] HandleBuf Buffer which holds all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.\r
+ @param[in] HandleCount Count of all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.\r
+ @param[in] Segment Segment number of device we are dealing with.\r
+ @param[in] Bus Bus number of device we are dealing with.\r
+ @param[out] IoDev Handle used to access configuration space of PCI device.\r
+\r
+ @retval EFI_SUCCESS The command completed successfully.\r
+ @retval EFI_INVALID_PARAMETER Invalid parameter.\r
\r
+**/\r
EFI_STATUS\r
PciFindProtocolInterface (\r
IN EFI_HANDLE *HandleBuf,\r
OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **IoDev\r
);\r
\r
+/**\r
+ This function gets the protocol interface from the given handle, and\r
+ obtains its address space descriptors.\r
+\r
+ @param[in] Handle The PCI_ROOT_BRIDIGE_IO_PROTOCOL handle.\r
+ @param[out] IoDev Handle used to access configuration space of PCI device.\r
+ @param[out] Descriptors Points to the address space descriptors.\r
+\r
+ @retval EFI_SUCCESS The command completed successfully\r
+**/\r
EFI_STATUS\r
PciGetProtocolAndResource (\r
IN EFI_HANDLE Handle,\r
OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR **Descriptors\r
);\r
\r
+/**\r
+ This function get the next bus range of given address space descriptors.\r
+ It also moves the pointer backward a node, to get prepared to be called\r
+ again.\r
+\r
+ @param[in, out] Descriptors Points to current position of a serial of address space\r
+ descriptors.\r
+ @param[out] MinBus The lower range of bus number.\r
+ @param[out] MaxBus The upper range of bus number.\r
+ @param[out] IsEnd Meet end of the serial of descriptors.\r
+\r
+ @retval EFI_SUCCESS The command completed successfully.\r
+**/\r
EFI_STATUS\r
PciGetNextBusRange (\r
IN OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR **Descriptors,\r
OUT BOOLEAN *IsEnd\r
);\r
\r
+/**\r
+ Explain the data in PCI configuration space. The part which is common for\r
+ PCI device and bridge is interpreted in this function. It calls other\r
+ functions to interpret data unique for device or bridge.\r
+\r
+ @param[in] ConfigSpace Data in PCI configuration space.\r
+ @param[in] Address Address used to access configuration space of this PCI device.\r
+ @param[in] IoDev Handle used to access configuration space of PCI device.\r
+\r
+ @retval EFI_SUCCESS The command completed successfully.\r
+**/\r
EFI_STATUS\r
PciExplainData (\r
IN PCI_CONFIG_SPACE *ConfigSpace,\r
IN UINT64 Address,\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r
+ IN CONST UINT16 EnhancedDump\r
);\r
\r
+/**\r
+ Explain the device specific part of data in PCI configuration space.\r
+\r
+ @param[in] Device Data in PCI configuration space.\r
+ @param[in] Address Address used to access configuration space of this PCI device.\r
+ @param[in] IoDev Handle used to access configuration space of PCI device.\r
+\r
+ @retval EFI_SUCCESS The command completed successfully.\r
+**/\r
EFI_STATUS\r
PciExplainDeviceData (\r
IN PCI_DEVICE_HEADER *Device,\r
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
);\r
\r
+/**\r
+ Explain the bridge specific part of data in PCI configuration space.\r
+\r
+ @param[in] Bridge Bridge specific data region in PCI configuration space.\r
+ @param[in] Address Address used to access configuration space of this PCI device.\r
+ @param[in] IoDev Handle used to access configuration space of PCI device.\r
+\r
+ @retval EFI_SUCCESS The command completed successfully.\r
+**/\r
EFI_STATUS\r
PciExplainBridgeData (\r
- IN PCI_BRIDGE_HEADER *Bridge,\r
- IN UINT64 Address,\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
+ IN PCI_BRIDGE_HEADER *Bridge,\r
+ IN UINT64 Address,\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
);\r
\r
+/**\r
+ Explain the Base Address Register(Bar) in PCI configuration space.\r
+\r
+ @param[in] Bar Points to the Base Address Register intended to interpret.\r
+ @param[in] Command Points to the register Command.\r
+ @param[in] Address Address used to access configuration space of this PCI device.\r
+ @param[in] IoDev Handle used to access configuration space of PCI device.\r
+ @param[in, out] Index The Index.\r
+\r
+ @retval EFI_SUCCESS The command completed successfully.\r
+**/\r
EFI_STATUS\r
PciExplainBar (\r
IN UINT32 *Bar,\r
IN OUT UINTN *Index\r
);\r
\r
+/**\r
+ Explain the cardbus specific part of data in PCI configuration space.\r
+\r
+ @param[in] CardBus CardBus specific region of PCI configuration space.\r
+ @param[in] Address Address used to access configuration space of this PCI device.\r
+ @param[in] IoDev Handle used to access configuration space of PCI device.\r
+\r
+ @retval EFI_SUCCESS The command completed successfully.\r
+**/\r
EFI_STATUS\r
PciExplainCardBusData (\r
IN PCI_CARDBUS_HEADER *CardBus,\r
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
);\r
\r
+/**\r
+ Explain each meaningful bit of register Status. The definition of Status is\r
+ slightly different depending on the PCI header type.\r
+\r
+ @param[in] Status Points to the content of register Status.\r
+ @param[in] MainStatus Indicates if this register is main status(not secondary\r
+ status).\r
+ @param[in] HeaderType Header type of this PCI device.\r
+\r
+ @retval EFI_SUCCESS The command completed successfully.\r
+**/\r
EFI_STATUS\r
PciExplainStatus (\r
IN UINT16 *Status,\r
IN PCI_HEADER_TYPE HeaderType\r
);\r
\r
+/**\r
+ Explain each meaningful bit of register Command.\r
+\r
+ @param[in] Command Points to the content of register Command.\r
+\r
+ @retval EFI_SUCCESS The command completed successfully.\r
+**/\r
EFI_STATUS\r
PciExplainCommand (\r
IN UINT16 *Command\r
);\r
\r
+/**\r
+ Explain each meaningful bit of register Bridge Control.\r
+\r
+ @param[in] BridgeControl Points to the content of register Bridge Control.\r
+ @param[in] HeaderType The headertype.\r
+\r
+ @retval EFI_SUCCESS The command completed successfully.\r
+**/\r
EFI_STATUS\r
PciExplainBridgeControl (\r
IN UINT16 *BridgeControl,\r
IN PCI_HEADER_TYPE HeaderType\r
);\r
\r
+/**\r
+ Print each capability structure.\r
+\r
+ @param[in] IoDev The pointer to the deivce.\r
+ @param[in] Address The address to start at.\r
+ @param[in] CapPtr The offset from the address.\r
+\r
+ @retval EFI_SUCCESS The operation was successful.\r
+**/\r
EFI_STATUS\r
PciExplainCapabilityStruct (\r
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r
IN UINT64 Address,\r
- IN UINT8 CapPtr\r
+ IN UINT8 CapPtr,\r
+ IN CONST UINT16 EnhancedDump\r
);\r
\r
+/**\r
+ Display Pcie device structure.\r
+\r
+ @param[in] IoDev The pointer to the root pci protocol.\r
+ @param[in] Address The Address to start at.\r
+ @param[in] CapabilityPtr The offset from the address to start.\r
+**/\r
EFI_STATUS\r
PciExplainPciExpress (\r
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r
IN UINT64 Address,\r
- IN UINT8 CapabilityPtr\r
+ IN UINT8 CapabilityPtr,\r
+ IN CONST UINT16 EnhancedDump\r
);\r
\r
+/**\r
+ Print out information of the capability information.\r
+\r
+ @param[in] PciExpressCap The pointer to the structure about the device.\r
+\r
+ @retval EFI_SUCCESS The operation was successful.\r
+**/\r
EFI_STATUS\r
ExplainPcieCapReg (\r
IN PCIE_CAP_STURCTURE *PciExpressCap\r
-);\r
+ );\r
+\r
+/**\r
+ Print out information of the device capability information.\r
\r
+ @param[in] PciExpressCap The pointer to the structure about the device.\r
+\r
+ @retval EFI_SUCCESS The operation was successful.\r
+**/\r
EFI_STATUS\r
ExplainPcieDeviceCap (\r
IN PCIE_CAP_STURCTURE *PciExpressCap\r
-);\r
+ );\r
+\r
+/**\r
+ Print out information of the device control information.\r
\r
+ @param[in] PciExpressCap The pointer to the structure about the device.\r
+\r
+ @retval EFI_SUCCESS The operation was successful.\r
+**/\r
EFI_STATUS\r
ExplainPcieDeviceControl (\r
IN PCIE_CAP_STURCTURE *PciExpressCap\r
-);\r
+ );\r
+\r
+/**\r
+ Print out information of the device status information.\r
\r
+ @param[in] PciExpressCap The pointer to the structure about the device.\r
+\r
+ @retval EFI_SUCCESS The operation was successful.\r
+**/\r
EFI_STATUS\r
ExplainPcieDeviceStatus (\r
IN PCIE_CAP_STURCTURE *PciExpressCap\r
-);\r
+ );\r
+\r
+/**\r
+ Print out information of the device link information.\r
\r
+ @param[in] PciExpressCap The pointer to the structure about the device.\r
+\r
+ @retval EFI_SUCCESS The operation was successful.\r
+**/\r
EFI_STATUS\r
ExplainPcieLinkCap (\r
IN PCIE_CAP_STURCTURE *PciExpressCap\r
-);\r
+ );\r
+\r
+/**\r
+ Print out information of the device link control information.\r
\r
+ @param[in] PciExpressCap The pointer to the structure about the device.\r
+\r
+ @retval EFI_SUCCESS The operation was successful.\r
+**/\r
EFI_STATUS\r
ExplainPcieLinkControl (\r
IN PCIE_CAP_STURCTURE *PciExpressCap\r
-);\r
+ );\r
+\r
+/**\r
+ Print out information of the device link status information.\r
\r
+ @param[in] PciExpressCap The pointer to the structure about the device.\r
+\r
+ @retval EFI_SUCCESS The operation was successful.\r
+**/\r
EFI_STATUS\r
ExplainPcieLinkStatus (\r
IN PCIE_CAP_STURCTURE *PciExpressCap\r
-);\r
+ );\r
+\r
+/**\r
+ Print out information of the device slot information.\r
\r
+ @param[in] PciExpressCap The pointer to the structure about the device.\r
+\r
+ @retval EFI_SUCCESS The operation was successful.\r
+**/\r
EFI_STATUS\r
ExplainPcieSlotCap (\r
IN PCIE_CAP_STURCTURE *PciExpressCap\r
-);\r
+ );\r
+\r
+/**\r
+ Print out information of the device slot control information.\r
\r
+ @param[in] PciExpressCap The pointer to the structure about the device.\r
+\r
+ @retval EFI_SUCCESS The operation was successful.\r
+**/\r
EFI_STATUS\r
ExplainPcieSlotControl (\r
IN PCIE_CAP_STURCTURE *PciExpressCap\r
-);\r
+ );\r
+\r
+/**\r
+ Print out information of the device slot status information.\r
\r
+ @param[in] PciExpressCap The pointer to the structure about the device.\r
+\r
+ @retval EFI_SUCCESS The operation was successful.\r
+**/\r
EFI_STATUS\r
ExplainPcieSlotStatus (\r
IN PCIE_CAP_STURCTURE *PciExpressCap\r
-);\r
+ );\r
+\r
+/**\r
+ Print out information of the device root information.\r
\r
+ @param[in] PciExpressCap The pointer to the structure about the device.\r
+\r
+ @retval EFI_SUCCESS The operation was successful.\r
+**/\r
EFI_STATUS\r
ExplainPcieRootControl (\r
IN PCIE_CAP_STURCTURE *PciExpressCap\r
-);\r
+ );\r
+\r
+/**\r
+ Print out information of the device root capability information.\r
\r
+ @param[in] PciExpressCap The pointer to the structure about the device.\r
+\r
+ @retval EFI_SUCCESS The operation was successful.\r
+**/\r
EFI_STATUS\r
ExplainPcieRootCap (\r
IN PCIE_CAP_STURCTURE *PciExpressCap\r
-);\r
+ );\r
+\r
+/**\r
+ Print out information of the device root status information.\r
\r
+ @param[in] PciExpressCap The pointer to the structure about the device.\r
+\r
+ @retval EFI_SUCCESS The operation was successful.\r
+**/\r
EFI_STATUS\r
ExplainPcieRootStatus (\r
IN PCIE_CAP_STURCTURE *PciExpressCap\r
-);\r
+ );\r
\r
typedef EFI_STATUS (*PCIE_EXPLAIN_FUNCTION) (IN PCIE_CAP_STURCTURE *PciExpressCap);\r
\r
};\r
\r
\r
+/**\r
+ Function for 'pci' command.\r
+\r
+ @param[in] ImageHandle Handle to the Image (NULL if Internal).\r
+ @param[in] SystemTable Pointer to the System Table (NULL if Internal).\r
+**/\r
SHELL_STATUS\r
EFIAPI\r
ShellCommandRunPci (\r
LIST_ENTRY *Package;\r
CHAR16 *ProblemParam;\r
SHELL_STATUS ShellStatus;\r
- UINTN Size;\r
CONST CHAR16 *Temp;\r
+ UINT64 RetVal;\r
+ UINT16 EnhancedDump;\r
\r
ShellStatus = SHELL_SUCCESS;\r
Status = EFI_SUCCESS;\r
Address = 0;\r
- Size = 0;\r
IoDev = NULL;\r
HandleBuf = NULL;\r
Package = NULL;\r
}\r
} else {\r
\r
+ if (ShellCommandLineGetCount(Package) == 2) {\r
+ ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_TOO_FEW), gShellDebug1HiiHandle);\r
+ ShellStatus = SHELL_INVALID_PARAMETER;\r
+ goto Done;\r
+ }\r
\r
+ if (ShellCommandLineGetCount(Package) > 4) {\r
+ ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_TOO_MANY), gShellDebug1HiiHandle);\r
+ ShellStatus = SHELL_INVALID_PARAMETER;\r
+ goto Done;\r
+ }\r
+ if (ShellCommandLineGetFlag(Package, L"-s") && ShellCommandLineGetValue(Package, L"-s") == NULL) {\r
+ ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_NO_VALUE), gShellDebug1HiiHandle, L"-s");\r
+ ShellStatus = SHELL_INVALID_PARAMETER;\r
+ goto Done;\r
+ }\r
//\r
// Get all instances of PciRootBridgeIo. Allocate space for 1 EFI_HANDLE and\r
// call LibLocateHandle(), if EFI_BUFFER_TOO_SMALL is returned, allocate enough\r
// space for handles and call it again.\r
//\r
HandleBufSize = sizeof (EFI_HANDLE);\r
- HandleBuf = (EFI_HANDLE *) AllocatePool (HandleBufSize);\r
+ HandleBuf = (EFI_HANDLE *) AllocateZeroPool (HandleBufSize);\r
if (HandleBuf == NULL) {\r
ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_OUT_MEM), gShellDebug1HiiHandle);\r
ShellStatus = SHELL_OUT_OF_RESOURCES;\r
//\r
// Argument Count == 1(no other argument): enumerate all pci functions\r
//\r
- if (ShellCommandLineGetCount(Package) == 0) {\r
+ if (ShellCommandLineGetCount(Package) == 1) {\r
gST->ConOut->QueryMode (\r
gST->ConOut,\r
gST->ConOut->Mode->Mode,\r
goto Done;\r
}\r
\r
- if (ShellCommandLineGetCount(Package) == 1) {\r
- ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_TOO_FEW), gShellDebug1HiiHandle);\r
- ShellStatus = SHELL_INVALID_PARAMETER;\r
- goto Done;\r
- }\r
- //\r
- // Arg count >= 3, dump binary of specified function, interpret if necessary\r
- //\r
- if (ShellCommandLineGetCount(Package) > 3) {\r
- ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_TOO_MANY), gShellDebug1HiiHandle);\r
- ShellStatus = SHELL_INVALID_PARAMETER;\r
- goto Done;\r
- }\r
-\r
ExplainData = FALSE;\r
Segment = 0;\r
Bus = 0;\r
\r
Temp = ShellCommandLineGetValue(Package, L"-s");\r
if (Temp != NULL) {\r
- Segment = (UINT16) StrHexToUintn (Temp);\r
+ //\r
+ // Input converted to hexadecimal number.\r
+ //\r
+ if (!EFI_ERROR (ShellConvertStringToUint64 (Temp, &RetVal, TRUE, TRUE))) {\r
+ Segment = (UINT16) RetVal;\r
+ } else {\r
+ ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV_HEX), gShellDebug1HiiHandle);\r
+ ShellStatus = SHELL_INVALID_PARAMETER;\r
+ goto Done;\r
+ }\r
}\r
\r
//\r
//\r
Temp = ShellCommandLineGetRawValue(Package, 1);\r
if (Temp != NULL) {\r
- Bus = (UINT16)StrHexToUintn(Temp);\r
+ //\r
+ // Input converted to hexadecimal number.\r
+ //\r
+ if (!EFI_ERROR (ShellConvertStringToUint64 (Temp, &RetVal, TRUE, TRUE))) {\r
+ Bus = (UINT16) RetVal;\r
+ } else {\r
+ ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV_HEX), gShellDebug1HiiHandle);\r
+ ShellStatus = SHELL_INVALID_PARAMETER;\r
+ goto Done;\r
+ }\r
+\r
if (Bus > MAX_BUS_NUMBER) {\r
ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PROBLEM), gShellDebug1HiiHandle, Temp);\r
ShellStatus = SHELL_INVALID_PARAMETER;\r
}\r
Temp = ShellCommandLineGetRawValue(Package, 2);\r
if (Temp != NULL) {\r
- Device = (UINT16) StrHexToUintn(Temp);\r
+ //\r
+ // Input converted to hexadecimal number.\r
+ //\r
+ if (!EFI_ERROR (ShellConvertStringToUint64 (Temp, &RetVal, TRUE, TRUE))) {\r
+ Device = (UINT16) RetVal;\r
+ } else {\r
+ ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV_HEX), gShellDebug1HiiHandle);\r
+ ShellStatus = SHELL_INVALID_PARAMETER;\r
+ goto Done;\r
+ }\r
+\r
if (Device > MAX_DEVICE_NUMBER){\r
ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PROBLEM), gShellDebug1HiiHandle, Temp);\r
ShellStatus = SHELL_INVALID_PARAMETER;\r
\r
Temp = ShellCommandLineGetRawValue(Package, 3);\r
if (Temp != NULL) {\r
- Func = (UINT16) StrHexToUintn(Temp);\r
+ //\r
+ // Input converted to hexadecimal number.\r
+ //\r
+ if (!EFI_ERROR (ShellConvertStringToUint64 (Temp, &RetVal, TRUE, TRUE))) {\r
+ Func = (UINT16) RetVal;\r
+ } else {\r
+ ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV_HEX), gShellDebug1HiiHandle);\r
+ ShellStatus = SHELL_INVALID_PARAMETER;\r
+ goto Done;\r
+ }\r
+\r
if (Func > MAX_FUNCTION_NUMBER){\r
ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PROBLEM), gShellDebug1HiiHandle, Temp);\r
ShellStatus = SHELL_INVALID_PARAMETER;\r
if (EFI_ERROR (Status)) {\r
ShellPrintHiiEx(\r
-1, -1, NULL, STRING_TOKEN (STR_PCI_NO_FIND), gShellDebug1HiiHandle,\r
- gShellDebug1HiiHandle,\r
Segment,\r
Bus\r
);\r
//\r
SizeOfHeader = sizeof (ConfigSpace.Common) + sizeof (ConfigSpace.NonCommon);\r
\r
- PrivateDumpHex (2, 0, SizeOfHeader, &ConfigSpace);\r
+ DumpHex (2, 0, SizeOfHeader, &ConfigSpace);\r
ShellPrintEx(-1,-1, L"\r\n");\r
\r
//\r
// Dump device dependent Part of configuration space\r
//\r
- PrivateDumpHex (\r
+ DumpHex (\r
2,\r
SizeOfHeader,\r
sizeof (ConfigSpace) - SizeOfHeader,\r
// If "-i" appears in command line, interpret data in configuration space\r
//\r
if (ExplainData) {\r
- Status = PciExplainData (&ConfigSpace, Address, IoDev);\r
+ EnhancedDump = 0;\r
+ if (ShellCommandLineGetFlag(Package, L"-_e")) {\r
+ EnhancedDump = 0xFFFF;\r
+ Temp = ShellCommandLineGetValue(Package, L"-_e");\r
+ if (Temp != NULL) {\r
+ EnhancedDump = (UINT16) ShellHexStrToUintn (Temp);\r
+ }\r
+ }\r
+ Status = PciExplainData (&ConfigSpace, Address, IoDev, EnhancedDump);\r
}\r
}\r
Done:\r
return ShellStatus;\r
}\r
\r
-EFI_STATUS\r
-PciFindProtocolInterface (\r
- IN EFI_HANDLE *HandleBuf,\r
- IN UINTN HandleCount,\r
- IN UINT16 Segment,\r
- IN UINT16 Bus,\r
- OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **IoDev\r
- )\r
-/*++\r
-\r
-Routine Description:\r
-\r
+/**\r
This function finds out the protocol which is in charge of the given\r
segment, and its bus range covers the current bus number. It lookes\r
each instances of RootBridgeIoProtocol handle, until the one meets the\r
criteria is found.\r
\r
-Arguments:\r
-\r
- HandleBuf Buffer which holds all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles\r
- HandleCount Count of all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles\r
- Segment Segment number of device we are dealing with\r
- Bus Bus number of device we are dealing with\r
- IoDev Handle used to access configuration space of PCI device\r
+ @param[in] HandleBuf Buffer which holds all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.\r
+ @param[in] HandleCount Count of all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.\r
+ @param[in] Segment Segment number of device we are dealing with.\r
+ @param[in] Bus Bus number of device we are dealing with.\r
+ @param[out] IoDev Handle used to access configuration space of PCI device.\r
\r
-Returns:\r
-\r
- EFI_SUCCESS - The command completed successfully\r
- EFI_INVALID_PARAMETER - Invalid parameter\r
+ @retval EFI_SUCCESS The command completed successfully.\r
+ @retval EFI_INVALID_PARAMETER Invalid parameter.\r
\r
**/\r
+EFI_STATUS\r
+PciFindProtocolInterface (\r
+ IN EFI_HANDLE *HandleBuf,\r
+ IN UINTN HandleCount,\r
+ IN UINT16 Segment,\r
+ IN UINT16 Bus,\r
+ OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **IoDev\r
+ )\r
{\r
UINTN Index;\r
EFI_STATUS Status;\r
- BOOLEAN FoundInterface;\r
EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptors;\r
UINT16 MinBus;\r
UINT16 MaxBus;\r
BOOLEAN IsEnd;\r
\r
- FoundInterface = FALSE;\r
//\r
// Go through all handles, until the one meets the criteria is found\r
//\r
}\r
\r
if (MinBus <= Bus && MaxBus >= Bus) {\r
- FoundInterface = TRUE;\r
- break;\r
+ return EFI_SUCCESS;\r
}\r
}\r
}\r
\r
- if (FoundInterface) {\r
- return EFI_SUCCESS;\r
- } else {\r
- return EFI_INVALID_PARAMETER;\r
- }\r
+ return EFI_NOT_FOUND;\r
}\r
\r
+/**\r
+ This function gets the protocol interface from the given handle, and\r
+ obtains its address space descriptors.\r
+\r
+ @param[in] Handle The PCI_ROOT_BRIDIGE_IO_PROTOCOL handle.\r
+ @param[out] IoDev Handle used to access configuration space of PCI device.\r
+ @param[out] Descriptors Points to the address space descriptors.\r
+\r
+ @retval EFI_SUCCESS The command completed successfully\r
+**/\r
EFI_STATUS\r
PciGetProtocolAndResource (\r
IN EFI_HANDLE Handle,\r
OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **IoDev,\r
OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR **Descriptors\r
)\r
-/*++\r
-\r
-Routine Description:\r
-\r
- This function gets the protocol interface from the given handle, and\r
- obtains its address space descriptors.\r
-\r
-Arguments:\r
-\r
- Handle The PCI_ROOT_BRIDIGE_IO_PROTOCOL handle\r
- IoDev Handle used to access configuration space of PCI device\r
- Descriptors Points to the address space descriptors\r
-\r
-Returns:\r
-\r
- EFI_SUCCESS The command completed successfully\r
-\r
-**/\r
{\r
EFI_STATUS Status;\r
\r
}\r
}\r
\r
+/**\r
+ This function get the next bus range of given address space descriptors.\r
+ It also moves the pointer backward a node, to get prepared to be called\r
+ again.\r
+\r
+ @param[in, out] Descriptors Points to current position of a serial of address space\r
+ descriptors.\r
+ @param[out] MinBus The lower range of bus number.\r
+ @param[out] MaxBus The upper range of bus number.\r
+ @param[out] IsEnd Meet end of the serial of descriptors.\r
+\r
+ @retval EFI_SUCCESS The command completed successfully.\r
+**/\r
EFI_STATUS\r
PciGetNextBusRange (\r
IN OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR **Descriptors,\r
OUT UINT16 *MaxBus,\r
OUT BOOLEAN *IsEnd\r
)\r
-/*++\r
-\r
-Routine Description:\r
-\r
- This function get the next bus range of given address space descriptors.\r
- It also moves the pointer backward a node, to get prepared to be called\r
- again.\r
-\r
-Arguments:\r
-\r
- Descriptors points to current position of a serial of address space\r
- descriptors\r
- MinBus The lower range of bus number\r
- ManBus The upper range of bus number\r
- IsEnd Meet end of the serial of descriptors\r
-\r
-Returns:\r
-\r
- EFI_SUCCESS The command completed successfully\r
-\r
-**/\r
{\r
*IsEnd = FALSE;\r
\r
// if a bus typed one is found and its bus range covers bus, this handle\r
// is the handle we are looking for.\r
//\r
- if ((*Descriptors)->Desc == ACPI_END_TAG_DESCRIPTOR) {\r
- *IsEnd = TRUE;\r
- }\r
\r
while ((*Descriptors)->Desc != ACPI_END_TAG_DESCRIPTOR) {\r
if ((*Descriptors)->ResType == ACPI_ADDRESS_SPACE_TYPE_BUS) {\r
*MinBus = (UINT16) (*Descriptors)->AddrRangeMin;\r
*MaxBus = (UINT16) (*Descriptors)->AddrRangeMax;\r
(*Descriptors)++;\r
- break;\r
+ return (EFI_SUCCESS);\r
}\r
\r
(*Descriptors)++;\r
}\r
\r
+ if ((*Descriptors)->Desc == ACPI_END_TAG_DESCRIPTOR) {\r
+ *IsEnd = TRUE;\r
+ }\r
+\r
return EFI_SUCCESS;\r
}\r
\r
-EFI_STATUS\r
-PciExplainData (\r
- IN PCI_CONFIG_SPACE *ConfigSpace,\r
- IN UINT64 Address,\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
- )\r
-/*++\r
-\r
-Routine Description:\r
-\r
+/**\r
Explain the data in PCI configuration space. The part which is common for\r
PCI device and bridge is interpreted in this function. It calls other\r
functions to interpret data unique for device or bridge.\r
\r
-Arguments:\r
-\r
- ConfigSpace Data in PCI configuration space\r
- Address Address used to access configuration space of this PCI device\r
- IoDev Handle used to access configuration space of PCI device\r
-\r
-Returns:\r
-\r
- EFI_SUCCESS The command completed successfully\r
+ @param[in] ConfigSpace Data in PCI configuration space.\r
+ @param[in] Address Address used to access configuration space of this PCI device.\r
+ @param[in] IoDev Handle used to access configuration space of PCI device.\r
\r
+ @retval EFI_SUCCESS The command completed successfully.\r
**/\r
+EFI_STATUS\r
+PciExplainData (\r
+ IN PCI_CONFIG_SPACE *ConfigSpace,\r
+ IN UINT64 Address,\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r
+ IN CONST UINT16 EnhancedDump\r
+ )\r
{\r
PCI_COMMON_HEADER *Common;\r
PCI_HEADER_TYPE HeaderType;\r
\r
Common = &(ConfigSpace->Common);\r
\r
- Print (L"\n");\r
+ ShellPrintEx (-1, -1, L"\r\n");\r
\r
//\r
// Print Vendor Id and Device Id\r
//\r
// Print register Revision ID\r
//\r
- ShellPrintEx(-1, -1, L"/r/n");\r
+ ShellPrintEx(-1, -1, L"\r\n");\r
ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_RID), gShellDebug1HiiHandle,\r
INDEX_OF (&(Common->RevisionId)),\r
Common->RevisionId\r
//\r
// Print register BIST\r
//\r
- ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_BIST), gShellDebug1HiiHandle, INDEX_OF (&(Common->BIST)));\r
- if ((Common->BIST & PCI_BIT_7) != 0) {\r
- ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_CAP), gShellDebug1HiiHandle, 0x0f & Common->BIST);\r
+ ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_BIST), gShellDebug1HiiHandle, INDEX_OF (&(Common->Bist)));\r
+ if ((Common->Bist & PCI_BIT_7) != 0) {\r
+ ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_CAP), gShellDebug1HiiHandle, 0x0f & Common->Bist);\r
} else {\r
ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_CAP_NO), gShellDebug1HiiHandle);\r
}\r
//\r
ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_CLASS), gShellDebug1HiiHandle);\r
PciPrintClassCode ((UINT8 *) Common->ClassCode, TRUE);\r
- Print (L"\n");\r
+ ShellPrintEx (-1, -1, L"\r\n");\r
\r
if (ShellGetExecutionBreakFlag()) {\r
return EFI_SUCCESS;\r
);\r
CapPtr = ConfigSpace->NonCommon.CardBus.CapabilitiesPtr;\r
break;\r
+ case PciUndefined:\r
+ default:\r
+ break;\r
}\r
//\r
// If Status bit4 is 1, dump or explain capability structure\r
//\r
if ((Common->Status) & EFI_PCI_STATUS_CAPABILITY) {\r
- PciExplainCapabilityStruct (IoDev, Address, CapPtr);\r
+ PciExplainCapabilityStruct (IoDev, Address, CapPtr, EnhancedDump);\r
}\r
\r
return Status;\r
}\r
\r
+/**\r
+ Explain the device specific part of data in PCI configuration space.\r
+\r
+ @param[in] Device Data in PCI configuration space.\r
+ @param[in] Address Address used to access configuration space of this PCI device.\r
+ @param[in] IoDev Handle used to access configuration space of PCI device.\r
+\r
+ @retval EFI_SUCCESS The command completed successfully.\r
+**/\r
EFI_STATUS\r
PciExplainDeviceData (\r
IN PCI_DEVICE_HEADER *Device,\r
IN UINT64 Address,\r
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
)\r
-/*++\r
-\r
-Routine Description:\r
-\r
- Explain the device specific part of data in PCI configuration space.\r
-\r
-Arguments:\r
-\r
- Device Data in PCI configuration space\r
- Address Address used to access configuration space of this PCI device\r
- IoDev Handle used to access configuration space of PCI device\r
-\r
-Returns:\r
-\r
- EFI_SUCCESS The command completed successfully\r
-\r
-**/\r
{\r
UINTN Index;\r
BOOLEAN BarExist;\r
if (!BarExist) {\r
BarExist = TRUE;\r
ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_START_TYPE), gShellDebug1HiiHandle);\r
- Print (L" --------------------------------------------------------------------------");\r
+ ShellPrintEx (-1, -1, L" --------------------------------------------------------------------------");\r
}\r
\r
Status = PciExplainBar (\r
ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NONE), gShellDebug1HiiHandle);\r
\r
} else {\r
- Print (L"\n --------------------------------------------------------------------------");\r
+ ShellPrintEx (-1, -1, L"\r\n --------------------------------------------------------------------------");\r
}\r
\r
//\r
return EFI_SUCCESS;\r
}\r
\r
+/**\r
+ Explain the bridge specific part of data in PCI configuration space.\r
+\r
+ @param[in] Bridge Bridge specific data region in PCI configuration space.\r
+ @param[in] Address Address used to access configuration space of this PCI device.\r
+ @param[in] IoDev Handle used to access configuration space of PCI device.\r
+\r
+ @retval EFI_SUCCESS The command completed successfully.\r
+**/\r
EFI_STATUS\r
PciExplainBridgeData (\r
IN PCI_BRIDGE_HEADER *Bridge,\r
IN UINT64 Address,\r
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
)\r
-/*++\r
-\r
-Routine Description:\r
-\r
- Explain the bridge specific part of data in PCI configuration space.\r
-\r
-Arguments:\r
-\r
- Bridge Bridge specific data region in PCI configuration space\r
- Address Address used to access configuration space of this PCI device\r
- IoDev Handle used to access configuration space of PCI device\r
-\r
-Returns:\r
-\r
- EFI_SUCCESS The command completed successfully\r
-\r
-**/\r
{\r
UINTN Index;\r
BOOLEAN BarExist;\r
if (!BarExist) {\r
BarExist = TRUE;\r
ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_START_TYPE_2), gShellDebug1HiiHandle);\r
- Print (L" --------------------------------------------------------------------------");\r
+ ShellPrintEx (-1, -1, L" --------------------------------------------------------------------------");\r
}\r
\r
Status = PciExplainBar (\r
if (!BarExist) {\r
ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NONE), gShellDebug1HiiHandle);\r
} else {\r
- Print (L"\n --------------------------------------------------------------------------");\r
+ ShellPrintEx (-1, -1, L"\r\n --------------------------------------------------------------------------");\r
}\r
\r
//\r
INDEX_OF (&(Bridge->SubordinateBus))\r
);\r
\r
- Print (L" ------------------------------------------------------\n");\r
+ ShellPrintEx (-1, -1, L" ------------------------------------------------------\r\n");\r
\r
ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BRIDGE), gShellDebug1HiiHandle, Bridge->PrimaryBus);\r
ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BRIDGE), gShellDebug1HiiHandle, Bridge->SecondaryBus);\r
// base and limit address are listed.\r
//\r
ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RESOURCE_TYPE), gShellDebug1HiiHandle);\r
- Print (L"----------------------------------------------------------------------\n");\r
+ ShellPrintEx (-1, -1, L"----------------------------------------------------------------------\r\n");\r
\r
//\r
// IO Base & Limit\r
return EFI_SUCCESS;\r
}\r
\r
+/**\r
+ Explain the Base Address Register(Bar) in PCI configuration space.\r
+\r
+ @param[in] Bar Points to the Base Address Register intended to interpret.\r
+ @param[in] Command Points to the register Command.\r
+ @param[in] Address Address used to access configuration space of this PCI device.\r
+ @param[in] IoDev Handle used to access configuration space of PCI device.\r
+ @param[in, out] Index The Index.\r
+\r
+ @retval EFI_SUCCESS The command completed successfully.\r
+**/\r
EFI_STATUS\r
PciExplainBar (\r
IN UINT32 *Bar,\r
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r
IN OUT UINTN *Index\r
)\r
-/*++\r
-\r
-Routine Description:\r
-\r
- Explain the Base Address Register(Bar) in PCI configuration space.\r
-\r
-Arguments:\r
-\r
- Bar Points to the Base Address Register intended to interpret\r
- Command Points to the register Command\r
- Address Address used to access configuration space of this PCI device\r
- IoDev Handle used to access configuration space of PCI device\r
- Index The Index\r
-\r
-Returns:\r
-\r
- EFI_SUCCESS The command completed successfully\r
-\r
-**/\r
{\r
UINT16 OldCommand;\r
UINT16 NewCommand;\r
} else if ((*Bar & PCI_BIT_1) == 0 && (*Bar & PCI_BIT_2) != 0) {\r
Bar64 = 0x0;\r
CopyMem (&Bar64, Bar, sizeof (UINT64));\r
- ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_ONE_VAR_2), gShellDebug1HiiHandle, RShiftU64 ((Bar64 & 0xfffffffffffffff0), 32));\r
- ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_ONE_VAR_3), gShellDebug1HiiHandle, (UINT32) (Bar64 & 0xfffffffffffffff0));\r
+ ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_ONE_VAR_2), gShellDebug1HiiHandle, (UINT32) RShiftU64 ((Bar64 & 0xfffffffffffffff0ULL), 32));\r
+ ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_ONE_VAR_3), gShellDebug1HiiHandle, (UINT32) (Bar64 & 0xfffffffffffffff0ULL));\r
ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MEM), gShellDebug1HiiHandle);\r
ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_64_BITS), gShellDebug1HiiHandle);\r
IsBar32 = FALSE;\r
//\r
IsMem = FALSE;\r
ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_ONE_VAR_4), gShellDebug1HiiHandle, *Bar & 0xfffffffc);\r
- Print (L"I/O ");\r
+ ShellPrintEx (-1, -1, L"I/O ");\r
}\r
\r
//\r
\r
OldBar64 = 0x0;\r
CopyMem (&OldBar64, Bar, sizeof (UINT64));\r
- NewBar64 = 0xffffffffffffffff;\r
+ NewBar64 = 0xffffffffffffffffULL;\r
\r
IoDev->Pci.Write (IoDev, EfiPciWidthUint32, RegAddress, 2, &NewBar64);\r
IoDev->Pci.Read (IoDev, EfiPciWidthUint32, RegAddress, 2, &NewBar64);\r
IoDev->Pci.Write (IoDev, EfiPciWidthUint32, RegAddress, 2, &OldBar64);\r
\r
if (IsMem) {\r
- NewBar64 = NewBar64 & 0xfffffffffffffff0;\r
+ NewBar64 = NewBar64 & 0xfffffffffffffff0ULL;\r
NewBar64 = (~NewBar64) + 1;\r
\r
} else {\r
- NewBar64 = NewBar64 & 0xfffffffffffffffc;\r
+ NewBar64 = NewBar64 & 0xfffffffffffffffcULL;\r
NewBar64 = (~NewBar64) + 1;\r
NewBar64 = NewBar64 & 0x000000000000ffff;\r
}\r
ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NEWBAR_32_2), gShellDebug1HiiHandle, NewBar32 + (*Bar & 0xfffffff0) - 1);\r
\r
} else {\r
- ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RSHIFT), gShellDebug1HiiHandle, RShiftU64 (NewBar64, 32));\r
+ ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RSHIFT), gShellDebug1HiiHandle, (UINT32) RShiftU64 (NewBar64, 32));\r
ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RSHIFT), gShellDebug1HiiHandle, (UINT32) NewBar64);\r
- Print (L" ");\r
+ ShellPrintEx (-1, -1, L" ");\r
ShellPrintHiiEx(-1, -1, NULL,\r
STRING_TOKEN (STR_PCI2_RSHIFT),\r
gShellDebug1HiiHandle,\r
- RShiftU64 ((NewBar64 + (Bar64 & 0xfffffffffffffff0) - 1), 32)\r
+ (UINT32) RShiftU64 ((NewBar64 + (Bar64 & 0xfffffffffffffff0ULL) - 1), 32)\r
);\r
- ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RSHIFT), gShellDebug1HiiHandle, (UINT32) (NewBar64 + (Bar64 & 0xfffffffffffffff0) - 1));\r
+ ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RSHIFT), gShellDebug1HiiHandle, (UINT32) (NewBar64 + (Bar64 & 0xfffffffffffffff0ULL) - 1));\r
\r
}\r
} else {\r
return EFI_SUCCESS;\r
}\r
\r
+/**\r
+ Explain the cardbus specific part of data in PCI configuration space.\r
+\r
+ @param[in] CardBus CardBus specific region of PCI configuration space.\r
+ @param[in] Address Address used to access configuration space of this PCI device.\r
+ @param[in] IoDev Handle used to access configuration space of PCI device.\r
+\r
+ @retval EFI_SUCCESS The command completed successfully.\r
+**/\r
EFI_STATUS\r
PciExplainCardBusData (\r
IN PCI_CARDBUS_HEADER *CardBus,\r
IN UINT64 Address,\r
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
)\r
-/*++\r
-\r
-Routine Description:\r
-\r
- Explain the cardbus specific part of data in PCI configuration space.\r
-\r
-Arguments:\r
-\r
- CardBus CardBus specific region of PCI configuration space\r
- Address Address used to access configuration space of this PCI device\r
- IoDev Handle used to access configuration space of PCI device\r
-\r
-Returns:\r
-\r
- EFI_SUCCESS The command completed successfully\r
-\r
-**/\r
{\r
BOOLEAN Io32Bit;\r
PCI_CARDBUS_DATA *CardBusData;\r
INDEX_OF (&(CardBus->SubordinateBusNumber))\r
);\r
\r
- Print (L" ------------------------------------------------------\n");\r
+ ShellPrintEx (-1, -1, L" ------------------------------------------------------\r\n");\r
\r
ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_CARDBUS), gShellDebug1HiiHandle, CardBus->PciBusNumber);\r
ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_CARDBUS_2), gShellDebug1HiiHandle, CardBus->CardBusBusNumber);\r
// Print Memory/Io ranges this cardbus bridge forwards\r
//\r
ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RESOURCE_TYPE_2), gShellDebug1HiiHandle);\r
- Print (L"----------------------------------------------------------------------\n");\r
+ ShellPrintEx (-1, -1, L"----------------------------------------------------------------------\r\n");\r
\r
ShellPrintHiiEx(-1, -1, NULL,\r
STRING_TOKEN (STR_PCI2_MEM_3),\r
INDEX_OF (&(CardBus->IoBase0)),\r
Io32Bit ? L" 32 bit" : L" 16 bit",\r
CardBus->IoBase0 & (Io32Bit ? 0xfffffffc : 0x0000fffc),\r
- CardBus->IoLimit0 & (Io32Bit ? 0xffffffff : 0x0000ffff) | 0x00000003\r
+ (CardBus->IoLimit0 & (Io32Bit ? 0xffffffff : 0x0000ffff)) | 0x00000003\r
);\r
\r
Io32Bit = (BOOLEAN) (CardBus->IoBase1 & PCI_BIT_0);\r
INDEX_OF (&(CardBus->IoBase1)),\r
Io32Bit ? L" 32 bit" : L" 16 bit",\r
CardBus->IoBase1 & (Io32Bit ? 0xfffffffc : 0x0000fffc),\r
- CardBus->IoLimit1 & (Io32Bit ? 0xffffffff : 0x0000ffff) | 0x00000003\r
+ (CardBus->IoLimit1 & (Io32Bit ? 0xffffffff : 0x0000ffff)) | 0x00000003\r
);\r
\r
//\r
return EFI_SUCCESS;\r
}\r
\r
+/**\r
+ Explain each meaningful bit of register Status. The definition of Status is\r
+ slightly different depending on the PCI header type.\r
+\r
+ @param[in] Status Points to the content of register Status.\r
+ @param[in] MainStatus Indicates if this register is main status(not secondary\r
+ status).\r
+ @param[in] HeaderType Header type of this PCI device.\r
+\r
+ @retval EFI_SUCCESS The command completed successfully.\r
+**/\r
EFI_STATUS\r
PciExplainStatus (\r
IN UINT16 *Status,\r
IN BOOLEAN MainStatus,\r
IN PCI_HEADER_TYPE HeaderType\r
)\r
-/*++\r
-\r
-Routine Description:\r
-\r
- Explain each meaningful bit of register Status. The definition of Status is\r
- slightly different depending on the PCI header type.\r
-\r
-Arguments:\r
-\r
- Status Points to the content of register Status\r
- MainStatus Indicates if this register is main status(not secondary\r
- status)\r
- HeaderType Header type of this PCI device\r
-\r
-Returns:\r
-\r
- EFI_SUCCESS The command completed successfully\r
-\r
-**/\r
{\r
if (MainStatus) {\r
ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_STATUS), gShellDebug1HiiHandle, INDEX_OF (Status), *Status);\r
return EFI_SUCCESS;\r
}\r
\r
-EFI_STATUS\r
-PciExplainCommand (\r
- IN UINT16 *Command\r
- )\r
-/*++\r
-\r
-Routine Description:\r
-\r
+/**\r
Explain each meaningful bit of register Command.\r
\r
-Arguments:\r
-\r
- Command Points to the content of register Command\r
-\r
-Returns:\r
-\r
- EFI_SUCCESS The command completed successfully\r
+ @param[in] Command Points to the content of register Command.\r
\r
+ @retval EFI_SUCCESS The command completed successfully.\r
**/\r
+EFI_STATUS\r
+PciExplainCommand (\r
+ IN UINT16 *Command\r
+ )\r
{\r
//\r
// Print the binary value of register Command\r
return EFI_SUCCESS;\r
}\r
\r
+/**\r
+ Explain each meaningful bit of register Bridge Control.\r
+\r
+ @param[in] BridgeControl Points to the content of register Bridge Control.\r
+ @param[in] HeaderType The headertype.\r
+\r
+ @retval EFI_SUCCESS The command completed successfully.\r
+**/\r
EFI_STATUS\r
PciExplainBridgeControl (\r
IN UINT16 *BridgeControl,\r
IN PCI_HEADER_TYPE HeaderType\r
)\r
-/*++\r
-\r
-Routine Description:\r
-\r
- Explain each meaningful bit of register Bridge Control.\r
-\r
-Arguments:\r
-\r
- BridgeControl Points to the content of register Bridge Control\r
- HeaderType The headertype\r
-\r
-Returns:\r
-\r
- EFI_SUCCESS The command completed successfully\r
-\r
-**/\r
{\r
ShellPrintHiiEx(-1, -1, NULL,\r
STRING_TOKEN (STR_PCI2_BRIDGE_CONTROL),\r
return EFI_SUCCESS;\r
}\r
\r
+/**\r
+ Print each capability structure.\r
+\r
+ @param[in] IoDev The pointer to the deivce.\r
+ @param[in] Address The address to start at.\r
+ @param[in] CapPtr The offset from the address.\r
+\r
+ @retval EFI_SUCCESS The operation was successful.\r
+**/\r
EFI_STATUS\r
PciExplainCapabilityStruct (\r
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r
IN UINT64 Address,\r
- IN UINT8 CapPtr\r
+ IN UINT8 CapPtr,\r
+ IN CONST UINT16 EnhancedDump\r
)\r
{\r
UINT8 CapabilityPtr;\r
// Explain PciExpress data\r
//\r
if (EFI_PCI_CAPABILITY_ID_PCIEXP == CapabilityID) {\r
- PciExplainPciExpress (IoDev, Address, CapabilityPtr);\r
+ PciExplainPciExpress (IoDev, Address, CapabilityPtr, EnhancedDump);\r
return EFI_SUCCESS;\r
}\r
//\r
return EFI_SUCCESS;\r
}\r
\r
+/**\r
+ Print out information of the capability information.\r
+\r
+ @param[in] PciExpressCap The pointer to the structure about the device.\r
+\r
+ @retval EFI_SUCCESS The operation was successful.\r
+**/\r
EFI_STATUS\r
ExplainPcieCapReg (\r
IN PCIE_CAP_STURCTURE *PciExpressCap\r
-)\r
+ )\r
{\r
UINT16 PcieCapReg;\r
CHAR16 *DevicePortType;\r
\r
PcieCapReg = PciExpressCap->PcieCapReg;\r
- Print (\r
- L" Capability Version(3:0): %E0x%04x%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Capability Version(3:0): %E0x%04x%N\r\n",\r
PCIE_CAP_VERSION (PcieCapReg)\r
);\r
if ((UINT8) PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg) < PCIE_DEVICE_PORT_TYPE_MAX) {\r
} else {\r
DevicePortType = L"Unknown Type";\r
}\r
- Print (\r
- L" Device/PortType(7:4): %E%s%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Device/PortType(7:4): %E%s%N\r\n",\r
DevicePortType\r
);\r
//\r
//\r
if (PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg) == PCIE_ROOT_COMPLEX_ROOT_PORT ||\r
PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg) == PCIE_SWITCH_DOWNSTREAM_PORT) {\r
- Print (\r
- L" Slot Implemented(8): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Slot Implemented(8): %E%d%N\r\n",\r
PCIE_CAP_SLOT_IMPLEMENTED (PcieCapReg)\r
);\r
}\r
- Print (\r
- L" Interrupt Message Number(13:9): %E0x%05x%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Interrupt Message Number(13:9): %E0x%05x%N\r\n",\r
PCIE_CAP_INT_MSG_NUM (PcieCapReg)\r
);\r
return EFI_SUCCESS;\r
}\r
\r
+/**\r
+ Print out information of the device capability information.\r
+\r
+ @param[in] PciExpressCap The pointer to the structure about the device.\r
+\r
+ @retval EFI_SUCCESS The operation was successful.\r
+**/\r
EFI_STATUS\r
ExplainPcieDeviceCap (\r
IN PCIE_CAP_STURCTURE *PciExpressCap\r
-)\r
+ )\r
{\r
UINT16 PcieCapReg;\r
UINT32 PcieDeviceCap;\r
PcieCapReg = PciExpressCap->PcieCapReg;\r
PcieDeviceCap = PciExpressCap->PcieDeviceCap;\r
DevicePortType = (UINT8) PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg);\r
- Print (L" Max_Payload_Size Supported(2:0): ");\r
+ ShellPrintEx (-1, -1, L" Max_Payload_Size Supported(2:0): ");\r
if (PCIE_CAP_MAX_PAYLOAD (PcieDeviceCap) < 6) {\r
- Print (L"%E%d bytes%N\n", 1 << (PCIE_CAP_MAX_PAYLOAD (PcieDeviceCap) + 7));\r
+ ShellPrintEx (-1, -1, L"%E%d bytes%N\r\n", 1 << (PCIE_CAP_MAX_PAYLOAD (PcieDeviceCap) + 7));\r
} else {\r
- Print (L"%EUnknown%N\n");\r
+ ShellPrintEx (-1, -1, L"%EUnknown%N\r\n");\r
}\r
- Print (\r
- L" Phantom Functions Supported(4:3): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Phantom Functions Supported(4:3): %E%d%N\r\n",\r
PCIE_CAP_PHANTOM_FUNC (PcieDeviceCap)\r
);\r
- Print (\r
- L" Extended Tag Field Supported(5): %E%d-bit Tag field supported%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Extended Tag Field Supported(5): %E%d-bit Tag field supported%N\r\n",\r
PCIE_CAP_EXTENDED_TAG (PcieDeviceCap) ? 8 : 5\r
);\r
//\r
// Endpoint L0s and L1 Acceptable Latency is only valid for Endpoint\r
//\r
if (IS_PCIE_ENDPOINT (DevicePortType)) {\r
- L0sLatency = (UINT8) PCIE_CAP_L0sLatency (PcieDeviceCap);\r
- L1Latency = (UINT8) PCIE_CAP_L1Latency (PcieDeviceCap);\r
- Print (L" Endpoint L0s Acceptable Latency(8:6): ");\r
+ L0sLatency = (UINT8) PCIE_CAP_L0SLATENCY (PcieDeviceCap);\r
+ L1Latency = (UINT8) PCIE_CAP_L1LATENCY (PcieDeviceCap);\r
+ ShellPrintEx (-1, -1, L" Endpoint L0s Acceptable Latency(8:6): ");\r
if (L0sLatency < 4) {\r
- Print (L"%EMaximum of %d ns%N\n", 1 << (L0sLatency + 6));\r
+ ShellPrintEx (-1, -1, L"%EMaximum of %d ns%N\r\n", 1 << (L0sLatency + 6));\r
} else {\r
if (L0sLatency < 7) {\r
- Print (L"%EMaximum of %d us%N\n", 1 << (L0sLatency - 3));\r
+ ShellPrintEx (-1, -1, L"%EMaximum of %d us%N\r\n", 1 << (L0sLatency - 3));\r
} else {\r
- Print (L"%ENo limit%N\n");\r
+ ShellPrintEx (-1, -1, L"%ENo limit%N\r\n");\r
}\r
}\r
- Print (L" Endpoint L1 Acceptable Latency(11:9): ");\r
+ ShellPrintEx (-1, -1, L" Endpoint L1 Acceptable Latency(11:9): ");\r
if (L1Latency < 7) {\r
- Print (L"%EMaximum of %d us%N\n", 1 << (L1Latency + 1));\r
+ ShellPrintEx (-1, -1, L"%EMaximum of %d us%N\r\n", 1 << (L1Latency + 1));\r
} else {\r
- Print (L"%ENo limit%N\n");\r
+ ShellPrintEx (-1, -1, L"%ENo limit%N\r\n");\r
}\r
}\r
- Print (\r
- L" Role-based Error Reporting(15): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Role-based Error Reporting(15): %E%d%N\r\n",\r
PCIE_CAP_ERR_REPORTING (PcieDeviceCap)\r
);\r
//\r
// b) Captured Slot Power Scale\r
//\r
if (DevicePortType == PCIE_SWITCH_UPSTREAM_PORT) {\r
- Print (\r
- L" Captured Slot Power Limit Value(25:18): %E0x%02x%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Captured Slot Power Limit Value(25:18): %E0x%02x%N\r\n",\r
PCIE_CAP_SLOT_POWER_VALUE (PcieDeviceCap)\r
);\r
- Print (\r
- L" Captured Slot Power Limit Scale(27:26): %E%s%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Captured Slot Power Limit Scale(27:26): %E%s%N\r\n",\r
SlotPwrLmtScaleTable[PCIE_CAP_SLOT_POWER_SCALE (PcieDeviceCap)]\r
);\r
}\r
// Function Level Reset Capability is only valid for Endpoint\r
//\r
if (IS_PCIE_ENDPOINT (DevicePortType)) {\r
- Print (\r
- L" Function Level Reset Capability(28): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Function Level Reset Capability(28): %E%d%N\r\n",\r
PCIE_CAP_FUNC_LEVEL_RESET (PcieDeviceCap)\r
);\r
}\r
return EFI_SUCCESS;\r
}\r
\r
+/**\r
+ Print out information of the device control information.\r
+\r
+ @param[in] PciExpressCap The pointer to the structure about the device.\r
+\r
+ @retval EFI_SUCCESS The operation was successful.\r
+**/\r
EFI_STATUS\r
ExplainPcieDeviceControl (\r
IN PCIE_CAP_STURCTURE *PciExpressCap\r
-)\r
+ )\r
{\r
UINT16 PcieCapReg;\r
UINT16 PcieDeviceControl;\r
\r
PcieCapReg = PciExpressCap->PcieCapReg;\r
PcieDeviceControl = PciExpressCap->DeviceControl;\r
- Print (\r
- L" Correctable Error Reporting Enable(0): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Correctable Error Reporting Enable(0): %E%d%N\r\n",\r
PCIE_CAP_COR_ERR_REPORTING_ENABLE (PcieDeviceControl)\r
);\r
- Print (\r
- L" Non-Fatal Error Reporting Enable(1): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Non-Fatal Error Reporting Enable(1): %E%d%N\r\n",\r
PCIE_CAP_NONFAT_ERR_REPORTING_ENABLE (PcieDeviceControl)\r
);\r
- Print (\r
- L" Fatal Error Reporting Enable(2): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Fatal Error Reporting Enable(2): %E%d%N\r\n",\r
PCIE_CAP_FATAL_ERR_REPORTING_ENABLE (PcieDeviceControl)\r
);\r
- Print (\r
- L" Unsupported Request Reporting Enable(3): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Unsupported Request Reporting Enable(3): %E%d%N\r\n",\r
PCIE_CAP_UNSUP_REQ_REPORTING_ENABLE (PcieDeviceControl)\r
);\r
- Print (\r
- L" Enable Relaxed Ordering(4): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Enable Relaxed Ordering(4): %E%d%N\r\n",\r
PCIE_CAP_RELAXED_ORDERING_ENABLE (PcieDeviceControl)\r
);\r
- Print (L" Max_Payload_Size(7:5): ");\r
+ ShellPrintEx (-1, -1, L" Max_Payload_Size(7:5): ");\r
if (PCIE_CAP_MAX_PAYLOAD_SIZE (PcieDeviceControl) < 6) {\r
- Print (L"%E%d bytes%N\n", 1 << (PCIE_CAP_MAX_PAYLOAD_SIZE (PcieDeviceControl) + 7));\r
+ ShellPrintEx (-1, -1, L"%E%d bytes%N\r\n", 1 << (PCIE_CAP_MAX_PAYLOAD_SIZE (PcieDeviceControl) + 7));\r
} else {\r
- Print (L"%EUnknown%N\n");\r
+ ShellPrintEx (-1, -1, L"%EUnknown%N\r\n");\r
}\r
- Print (\r
- L" Extended Tag Field Enable(8): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Extended Tag Field Enable(8): %E%d%N\r\n",\r
PCIE_CAP_EXTENDED_TAG_ENABLE (PcieDeviceControl)\r
);\r
- Print (\r
- L" Phantom Functions Enable(9): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Phantom Functions Enable(9): %E%d%N\r\n",\r
PCIE_CAP_PHANTOM_FUNC_ENABLE (PcieDeviceControl)\r
);\r
- Print (\r
- L" Auxiliary (AUX) Power PM Enable(10): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Auxiliary (AUX) Power PM Enable(10): %E%d%N\r\n",\r
PCIE_CAP_AUX_PM_ENABLE (PcieDeviceControl)\r
);\r
- Print (\r
- L" Enable No Snoop(11): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Enable No Snoop(11): %E%d%N\r\n",\r
PCIE_CAP_NO_SNOOP_ENABLE (PcieDeviceControl)\r
);\r
- Print (L" Max_Read_Request_Size(14:12): ");\r
+ ShellPrintEx (-1, -1, L" Max_Read_Request_Size(14:12): ");\r
if (PCIE_CAP_MAX_READ_REQ_SIZE (PcieDeviceControl) < 6) {\r
- Print (L"%E%d bytes%N\n", 1 << (PCIE_CAP_MAX_READ_REQ_SIZE (PcieDeviceControl) + 7));\r
+ ShellPrintEx (-1, -1, L"%E%d bytes%N\r\n", 1 << (PCIE_CAP_MAX_READ_REQ_SIZE (PcieDeviceControl) + 7));\r
} else {\r
- Print (L"%EUnknown%N\n");\r
+ ShellPrintEx (-1, -1, L"%EUnknown%N\r\n");\r
}\r
//\r
// Read operation is only valid for PCI Express to PCI/PCI-X Bridges\r
//\r
if (PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg) == PCIE_PCIE_TO_PCIX_BRIDGE) {\r
- Print (\r
- L" Bridge Configuration Retry Enable(15): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Bridge Configuration Retry Enable(15): %E%d%N\r\n",\r
PCIE_CAP_BRG_CONF_RETRY (PcieDeviceControl)\r
);\r
}\r
return EFI_SUCCESS;\r
}\r
\r
+/**\r
+ Print out information of the device status information.\r
+\r
+ @param[in] PciExpressCap The pointer to the structure about the device.\r
+\r
+ @retval EFI_SUCCESS The operation was successful.\r
+**/\r
EFI_STATUS\r
ExplainPcieDeviceStatus (\r
IN PCIE_CAP_STURCTURE *PciExpressCap\r
-)\r
+ )\r
{\r
UINT16 PcieDeviceStatus;\r
\r
PcieDeviceStatus = PciExpressCap->DeviceStatus;\r
- Print (\r
- L" Correctable Error Detected(0): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Correctable Error Detected(0): %E%d%N\r\n",\r
PCIE_CAP_COR_ERR_DETECTED (PcieDeviceStatus)\r
);\r
- Print (\r
- L" Non-Fatal Error Detected(1): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Non-Fatal Error Detected(1): %E%d%N\r\n",\r
PCIE_CAP_NONFAT_ERR_DETECTED (PcieDeviceStatus)\r
);\r
- Print (\r
- L" Fatal Error Detected(2): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Fatal Error Detected(2): %E%d%N\r\n",\r
PCIE_CAP_FATAL_ERR_DETECTED (PcieDeviceStatus)\r
);\r
- Print (\r
- L" Unsupported Request Detected(3): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Unsupported Request Detected(3): %E%d%N\r\n",\r
PCIE_CAP_UNSUP_REQ_DETECTED (PcieDeviceStatus)\r
);\r
- Print (\r
- L" AUX Power Detected(4): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" AUX Power Detected(4): %E%d%N\r\n",\r
PCIE_CAP_AUX_POWER_DETECTED (PcieDeviceStatus)\r
);\r
- Print (\r
- L" Transactions Pending(5): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Transactions Pending(5): %E%d%N\r\n",\r
PCIE_CAP_TRANSACTION_PENDING (PcieDeviceStatus)\r
);\r
return EFI_SUCCESS;\r
}\r
\r
+/**\r
+ Print out information of the device link information.\r
+\r
+ @param[in] PciExpressCap The pointer to the structure about the device.\r
+\r
+ @retval EFI_SUCCESS The operation was successful.\r
+**/\r
EFI_STATUS\r
ExplainPcieLinkCap (\r
IN PCIE_CAP_STURCTURE *PciExpressCap\r
-)\r
+ )\r
{\r
UINT32 PcieLinkCap;\r
- CHAR16 *SupLinkSpeeds;\r
- CHAR16 *ASPM;\r
+ CHAR16 *MaxLinkSpeed;\r
+ CHAR16 *AspmValue;\r
\r
PcieLinkCap = PciExpressCap->LinkCap;\r
- switch (PCIE_CAP_SUP_LINK_SPEEDS (PcieLinkCap)) {\r
+ switch (PCIE_CAP_MAX_LINK_SPEED (PcieLinkCap)) {\r
case 1:\r
- SupLinkSpeeds = L"2.5 GT/s";\r
+ MaxLinkSpeed = L"2.5 GT/s";\r
break;\r
case 2:\r
- SupLinkSpeeds = L"5.0 GT/s and 2.5 GT/s";\r
+ MaxLinkSpeed = L"5.0 GT/s";\r
+ break;\r
+ case 3:\r
+ MaxLinkSpeed = L"8.0 GT/s";\r
break;\r
default:\r
- SupLinkSpeeds = L"Unknown";\r
+ MaxLinkSpeed = L"Unknown";\r
break;\r
}\r
- Print (\r
- L" Supported Link Speeds(3:0): %E%s supported%N\n",\r
- SupLinkSpeeds\r
+ ShellPrintEx (-1, -1,\r
+ L" Maximum Link Speed(3:0): %E%s%N\r\n",\r
+ MaxLinkSpeed\r
);\r
- Print (\r
- L" Maximum Link Width(9:4): %Ex%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Maximum Link Width(9:4): %Ex%d%N\r\n",\r
PCIE_CAP_MAX_LINK_WIDTH (PcieLinkCap)\r
);\r
switch (PCIE_CAP_ASPM_SUPPORT (PcieLinkCap)) {\r
+ case 0:\r
+ AspmValue = L"Not";\r
+ break;\r
case 1:\r
- ASPM = L"L0s Entry";\r
+ AspmValue = L"L0s";\r
+ break;\r
+ case 2:\r
+ AspmValue = L"L1";\r
break;\r
case 3:\r
- ASPM = L"L0s and L1";\r
+ AspmValue = L"L0s and L1";\r
break;\r
default:\r
- ASPM = L"Reserved";\r
+ AspmValue = L"Reserved";\r
break;\r
}\r
- Print (\r
- L" Active State Power Management Support(11:10): %E%s Supported%N\n",\r
- ASPM\r
+ ShellPrintEx (-1, -1,\r
+ L" Active State Power Management Support(11:10): %E%s Supported%N\r\n",\r
+ AspmValue\r
);\r
- Print (\r
- L" L0s Exit Latency(14:12): %E%s%N\n",\r
- L0sLatencyStrTable[PCIE_CAP_L0s_LATENCY (PcieLinkCap)]\r
+ ShellPrintEx (-1, -1,\r
+ L" L0s Exit Latency(14:12): %E%s%N\r\n",\r
+ L0sLatencyStrTable[PCIE_CAP_L0S_LATENCY (PcieLinkCap)]\r
);\r
- Print (\r
- L" L1 Exit Latency(17:15): %E%s%N\n",\r
- L1LatencyStrTable[PCIE_CAP_L0s_LATENCY (PcieLinkCap)]\r
+ ShellPrintEx (-1, -1,\r
+ L" L1 Exit Latency(17:15): %E%s%N\r\n",\r
+ L1LatencyStrTable[PCIE_CAP_L0S_LATENCY (PcieLinkCap)]\r
);\r
- Print (\r
- L" Clock Power Management(18): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Clock Power Management(18): %E%d%N\r\n",\r
PCIE_CAP_CLOCK_PM (PcieLinkCap)\r
);\r
- Print (\r
- L" Surprise Down Error Reporting Capable(19): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Surprise Down Error Reporting Capable(19): %E%d%N\r\n",\r
PCIE_CAP_SUP_DOWN_ERR_REPORTING (PcieLinkCap)\r
);\r
- Print (\r
- L" Data Link Layer Link Active Reporting Capable(20): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Data Link Layer Link Active Reporting Capable(20): %E%d%N\r\n",\r
PCIE_CAP_LINK_ACTIVE_REPORTING (PcieLinkCap)\r
);\r
- Print (\r
- L" Link Bandwidth Notification Capability(21): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Link Bandwidth Notification Capability(21): %E%d%N\r\n",\r
PCIE_CAP_LINK_BWD_NOTIF_CAP (PcieLinkCap)\r
);\r
- Print (\r
- L" Port Number(31:24): %E0x%02x%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Port Number(31:24): %E0x%02x%N\r\n",\r
PCIE_CAP_PORT_NUMBER (PcieLinkCap)\r
);\r
return EFI_SUCCESS;\r
}\r
\r
+/**\r
+ Print out information of the device link control information.\r
+\r
+ @param[in] PciExpressCap The pointer to the structure about the device.\r
+\r
+ @retval EFI_SUCCESS The operation was successful.\r
+**/\r
EFI_STATUS\r
ExplainPcieLinkControl (\r
IN PCIE_CAP_STURCTURE *PciExpressCap\r
-)\r
+ )\r
{\r
UINT16 PcieLinkControl;\r
UINT8 DevicePortType;\r
\r
PcieLinkControl = PciExpressCap->LinkControl;\r
DevicePortType = (UINT8) PCIE_CAP_DEVICEPORT_TYPE (PciExpressCap->PcieCapReg);\r
- Print (\r
- L" Active State Power Management Control(1:0): %E%s%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Active State Power Management Control(1:0): %E%s%N\r\n",\r
ASPMCtrlStrTable[PCIE_CAP_ASPM_CONTROL (PcieLinkControl)]\r
);\r
//\r
// RCB is not applicable to switches\r
//\r
if (!IS_PCIE_SWITCH(DevicePortType)) {\r
- Print (\r
- L" Read Completion Boundary (RCB)(3): %E%d byte%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Read Completion Boundary (RCB)(3): %E%d byte%N\r\n",\r
1 << (PCIE_CAP_RCB (PcieLinkControl) + 6)\r
);\r
}\r
if (!IS_PCIE_ENDPOINT (DevicePortType) &&\r
DevicePortType != PCIE_SWITCH_UPSTREAM_PORT &&\r
DevicePortType != PCIE_PCIE_TO_PCIX_BRIDGE) {\r
- Print (\r
- L" Link Disable(4): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Link Disable(4): %E%d%N\r\n",\r
PCIE_CAP_LINK_DISABLE (PcieLinkControl)\r
);\r
}\r
- Print (\r
- L" Common Clock Configuration(6): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Common Clock Configuration(6): %E%d%N\r\n",\r
PCIE_CAP_COMMON_CLK_CONF (PcieLinkControl)\r
);\r
- Print (\r
- L" Extended Synch(7): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Extended Synch(7): %E%d%N\r\n",\r
PCIE_CAP_EXT_SYNC (PcieLinkControl)\r
);\r
- Print (\r
- L" Enable Clock Power Management(8): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Enable Clock Power Management(8): %E%d%N\r\n",\r
PCIE_CAP_CLK_PWR_MNG (PcieLinkControl)\r
);\r
- Print (\r
- L" Hardware Autonomous Width Disable(9): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Hardware Autonomous Width Disable(9): %E%d%N\r\n",\r
PCIE_CAP_HW_AUTO_WIDTH_DISABLE (PcieLinkControl)\r
);\r
- Print (\r
- L" Link Bandwidth Management Interrupt Enable(10): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Link Bandwidth Management Interrupt Enable(10): %E%d%N\r\n",\r
PCIE_CAP_LINK_BDW_MNG_INT_EN (PcieLinkControl)\r
);\r
- Print (\r
- L" Link Autonomous Bandwidth Interrupt Enable(11): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Link Autonomous Bandwidth Interrupt Enable(11): %E%d%N\r\n",\r
PCIE_CAP_LINK_AUTO_BDW_INT_EN (PcieLinkControl)\r
);\r
return EFI_SUCCESS;\r
}\r
\r
+/**\r
+ Print out information of the device link status information.\r
+\r
+ @param[in] PciExpressCap The pointer to the structure about the device.\r
+\r
+ @retval EFI_SUCCESS The operation was successful.\r
+**/\r
EFI_STATUS\r
ExplainPcieLinkStatus (\r
IN PCIE_CAP_STURCTURE *PciExpressCap\r
-)\r
+ )\r
{\r
UINT16 PcieLinkStatus;\r
- CHAR16 *SupLinkSpeeds;\r
+ CHAR16 *CurLinkSpeed;\r
\r
PcieLinkStatus = PciExpressCap->LinkStatus;\r
switch (PCIE_CAP_CUR_LINK_SPEED (PcieLinkStatus)) {\r
case 1:\r
- SupLinkSpeeds = L"2.5 GT/s";\r
+ CurLinkSpeed = L"2.5 GT/s";\r
break;\r
case 2:\r
- SupLinkSpeeds = L"5.0 GT/s";\r
+ CurLinkSpeed = L"5.0 GT/s";\r
+ break;\r
+ case 3:\r
+ CurLinkSpeed = L"8.0 GT/s";\r
break;\r
default:\r
- SupLinkSpeeds = L"Reserved";\r
+ CurLinkSpeed = L"Reserved";\r
break;\r
}\r
- Print (\r
- L" Current Link Speed(3:0): %E%s%N\n",\r
- SupLinkSpeeds\r
+ ShellPrintEx (-1, -1,\r
+ L" Current Link Speed(3:0): %E%s%N\r\n",\r
+ CurLinkSpeed\r
);\r
- Print (\r
- L" Negotiated Link Width(9:4): %Ex%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Negotiated Link Width(9:4): %Ex%d%N\r\n",\r
PCIE_CAP_NEGO_LINK_WIDTH (PcieLinkStatus)\r
);\r
- Print (\r
- L" Link Training(11): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Link Training(11): %E%d%N\r\n",\r
PCIE_CAP_LINK_TRAINING (PcieLinkStatus)\r
);\r
- Print (\r
- L" Slot Clock Configuration(12): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Slot Clock Configuration(12): %E%d%N\r\n",\r
PCIE_CAP_SLOT_CLK_CONF (PcieLinkStatus)\r
);\r
- Print (\r
- L" Data Link Layer Link Active(13): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Data Link Layer Link Active(13): %E%d%N\r\n",\r
PCIE_CAP_DATA_LINK_ACTIVE (PcieLinkStatus)\r
);\r
- Print (\r
- L" Link Bandwidth Management Status(14): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Link Bandwidth Management Status(14): %E%d%N\r\n",\r
PCIE_CAP_LINK_BDW_MNG_STAT (PcieLinkStatus)\r
);\r
- Print (\r
- L" Link Autonomous Bandwidth Status(15): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Link Autonomous Bandwidth Status(15): %E%d%N\r\n",\r
PCIE_CAP_LINK_AUTO_BDW_STAT (PcieLinkStatus)\r
);\r
return EFI_SUCCESS;\r
}\r
\r
+/**\r
+ Print out information of the device slot information.\r
+\r
+ @param[in] PciExpressCap The pointer to the structure about the device.\r
+\r
+ @retval EFI_SUCCESS The operation was successful.\r
+**/\r
EFI_STATUS\r
ExplainPcieSlotCap (\r
IN PCIE_CAP_STURCTURE *PciExpressCap\r
-)\r
+ )\r
{\r
UINT32 PcieSlotCap;\r
\r
PcieSlotCap = PciExpressCap->SlotCap;\r
\r
- Print (\r
- L" Attention Button Present(0): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Attention Button Present(0): %E%d%N\r\n",\r
PCIE_CAP_ATT_BUT_PRESENT (PcieSlotCap)\r
);\r
- Print (\r
- L" Power Controller Present(1): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Power Controller Present(1): %E%d%N\r\n",\r
PCIE_CAP_PWR_CTRLLER_PRESENT (PcieSlotCap)\r
);\r
- Print (\r
- L" MRL Sensor Present(2): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" MRL Sensor Present(2): %E%d%N\r\n",\r
PCIE_CAP_MRL_SENSOR_PRESENT (PcieSlotCap)\r
);\r
- Print (\r
- L" Attention Indicator Present(3): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Attention Indicator Present(3): %E%d%N\r\n",\r
PCIE_CAP_ATT_IND_PRESENT (PcieSlotCap)\r
);\r
- Print (\r
- L" Power Indicator Present(4): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Power Indicator Present(4): %E%d%N\r\n",\r
PCIE_CAP_PWD_IND_PRESENT (PcieSlotCap)\r
);\r
- Print (\r
- L" Hot-Plug Surprise(5): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Hot-Plug Surprise(5): %E%d%N\r\n",\r
PCIE_CAP_HOTPLUG_SUPPRISE (PcieSlotCap)\r
);\r
- Print (\r
- L" Hot-Plug Capable(6): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Hot-Plug Capable(6): %E%d%N\r\n",\r
PCIE_CAP_HOTPLUG_CAPABLE (PcieSlotCap)\r
);\r
- Print (\r
- L" Slot Power Limit Value(14:7): %E0x%02x%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Slot Power Limit Value(14:7): %E0x%02x%N\r\n",\r
PCIE_CAP_SLOT_PWR_LIMIT_VALUE (PcieSlotCap)\r
);\r
- Print (\r
- L" Slot Power Limit Scale(16:15): %E%s%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Slot Power Limit Scale(16:15): %E%s%N\r\n",\r
SlotPwrLmtScaleTable[PCIE_CAP_SLOT_PWR_LIMIT_SCALE (PcieSlotCap)]\r
);\r
- Print (\r
- L" Electromechanical Interlock Present(17): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Electromechanical Interlock Present(17): %E%d%N\r\n",\r
PCIE_CAP_ELEC_INTERLOCK_PRESENT (PcieSlotCap)\r
);\r
- Print (\r
- L" No Command Completed Support(18): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" No Command Completed Support(18): %E%d%N\r\n",\r
PCIE_CAP_NO_COMM_COMPLETED_SUP (PcieSlotCap)\r
);\r
- Print (\r
- L" Physical Slot Number(31:19): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Physical Slot Number(31:19): %E%d%N\r\n",\r
PCIE_CAP_PHY_SLOT_NUM (PcieSlotCap)\r
);\r
\r
return EFI_SUCCESS;\r
}\r
\r
+/**\r
+ Print out information of the device slot control information.\r
+\r
+ @param[in] PciExpressCap The pointer to the structure about the device.\r
+\r
+ @retval EFI_SUCCESS The operation was successful.\r
+**/\r
EFI_STATUS\r
ExplainPcieSlotControl (\r
IN PCIE_CAP_STURCTURE *PciExpressCap\r
-)\r
+ )\r
{\r
UINT16 PcieSlotControl;\r
\r
PcieSlotControl = PciExpressCap->SlotControl;\r
- Print (\r
- L" Attention Button Pressed Enable(0): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Attention Button Pressed Enable(0): %E%d%N\r\n",\r
PCIE_CAP_ATT_BUT_ENABLE (PcieSlotControl)\r
);\r
- Print (\r
- L" Power Fault Detected Enable(1): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Power Fault Detected Enable(1): %E%d%N\r\n",\r
PCIE_CAP_PWR_FLT_DETECT_ENABLE (PcieSlotControl)\r
);\r
- Print (\r
- L" MRL Sensor Changed Enable(2): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" MRL Sensor Changed Enable(2): %E%d%N\r\n",\r
PCIE_CAP_MRL_SENSOR_CHANGE_ENABLE (PcieSlotControl)\r
);\r
- Print (\r
- L" Presence Detect Changed Enable(3): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Presence Detect Changed Enable(3): %E%d%N\r\n",\r
PCIE_CAP_PRES_DETECT_CHANGE_ENABLE (PcieSlotControl)\r
);\r
- Print (\r
- L" Command Completed Interrupt Enable(4): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Command Completed Interrupt Enable(4): %E%d%N\r\n",\r
PCIE_CAP_COMM_CMPL_INT_ENABLE (PcieSlotControl)\r
);\r
- Print (\r
- L" Hot-Plug Interrupt Enable(5): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Hot-Plug Interrupt Enable(5): %E%d%N\r\n",\r
PCIE_CAP_HOTPLUG_INT_ENABLE (PcieSlotControl)\r
);\r
- Print (\r
- L" Attention Indicator Control(7:6): %E%s%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Attention Indicator Control(7:6): %E%s%N\r\n",\r
IndicatorTable[PCIE_CAP_ATT_IND_CTRL (PcieSlotControl)]\r
);\r
- Print (\r
- L" Power Indicator Control(9:8): %E%s%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Power Indicator Control(9:8): %E%s%N\r\n",\r
IndicatorTable[PCIE_CAP_PWR_IND_CTRL (PcieSlotControl)]\r
);\r
- Print (L" Power Controller Control(10): %EPower ");\r
+ ShellPrintEx (-1, -1, L" Power Controller Control(10): %EPower ");\r
if (PCIE_CAP_PWR_CTRLLER_CTRL (PcieSlotControl)) {\r
- Print (L"Off%N\n");\r
+ ShellPrintEx (-1, -1, L"Off%N\r\n");\r
} else {\r
- Print (L"On%N\n");\r
+ ShellPrintEx (-1, -1, L"On%N\r\n");\r
}\r
- Print (\r
- L" Electromechanical Interlock Control(11): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Electromechanical Interlock Control(11): %E%d%N\r\n",\r
PCIE_CAP_ELEC_INTERLOCK_CTRL (PcieSlotControl)\r
);\r
- Print (\r
- L" Data Link Layer State Changed Enable(12): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Data Link Layer State Changed Enable(12): %E%d%N\r\n",\r
PCIE_CAP_DLINK_STAT_CHANGE_ENABLE (PcieSlotControl)\r
);\r
return EFI_SUCCESS;\r
}\r
\r
+/**\r
+ Print out information of the device slot status information.\r
+\r
+ @param[in] PciExpressCap The pointer to the structure about the device.\r
+\r
+ @retval EFI_SUCCESS The operation was successful.\r
+**/\r
EFI_STATUS\r
ExplainPcieSlotStatus (\r
IN PCIE_CAP_STURCTURE *PciExpressCap\r
-)\r
+ )\r
{\r
UINT16 PcieSlotStatus;\r
\r
PcieSlotStatus = PciExpressCap->SlotStatus;\r
\r
- Print (\r
- L" Attention Button Pressed(0): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Attention Button Pressed(0): %E%d%N\r\n",\r
PCIE_CAP_ATT_BUT_PRESSED (PcieSlotStatus)\r
);\r
- Print (\r
- L" Power Fault Detected(1): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Power Fault Detected(1): %E%d%N\r\n",\r
PCIE_CAP_PWR_FLT_DETECTED (PcieSlotStatus)\r
);\r
- Print (\r
- L" MRL Sensor Changed(2): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" MRL Sensor Changed(2): %E%d%N\r\n",\r
PCIE_CAP_MRL_SENSOR_CHANGED (PcieSlotStatus)\r
);\r
- Print (\r
- L" Presence Detect Changed(3): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Presence Detect Changed(3): %E%d%N\r\n",\r
PCIE_CAP_PRES_DETECT_CHANGED (PcieSlotStatus)\r
);\r
- Print (\r
- L" Command Completed(4): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Command Completed(4): %E%d%N\r\n",\r
PCIE_CAP_COMM_COMPLETED (PcieSlotStatus)\r
);\r
- Print (L" MRL Sensor State(5): %EMRL ");\r
+ ShellPrintEx (-1, -1, L" MRL Sensor State(5): %EMRL ");\r
if (PCIE_CAP_MRL_SENSOR_STATE (PcieSlotStatus)) {\r
- Print (L" Opened%N\n");\r
+ ShellPrintEx (-1, -1, L" Opened%N\r\n");\r
} else {\r
- Print (L" Closed%N\n");\r
+ ShellPrintEx (-1, -1, L" Closed%N\r\n");\r
}\r
- Print (L" Presence Detect State(6): ");\r
+ ShellPrintEx (-1, -1, L" Presence Detect State(6): ");\r
if (PCIE_CAP_PRES_DETECT_STATE (PcieSlotStatus)) {\r
- Print (L"%ECard Present in slot%N\n");\r
+ ShellPrintEx (-1, -1, L"%ECard Present in slot%N\r\n");\r
} else {\r
- Print (L"%ESlot Empty%N\n");\r
+ ShellPrintEx (-1, -1, L"%ESlot Empty%N\r\n");\r
}\r
- Print (L" Electromechanical Interlock Status(7): %EElectromechanical Interlock ");\r
+ ShellPrintEx (-1, -1, L" Electromechanical Interlock Status(7): %EElectromechanical Interlock ");\r
if (PCIE_CAP_ELEC_INTERLOCK_STATE (PcieSlotStatus)) {\r
- Print (L"Engaged%N\n");\r
+ ShellPrintEx (-1, -1, L"Engaged%N\r\n");\r
} else {\r
- Print (L"Disengaged%N\n");\r
+ ShellPrintEx (-1, -1, L"Disengaged%N\r\n");\r
}\r
- Print (\r
- L" Data Link Layer State Changed(8): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Data Link Layer State Changed(8): %E%d%N\r\n",\r
PCIE_CAP_DLINK_STAT_CHANGED (PcieSlotStatus)\r
);\r
return EFI_SUCCESS;\r
}\r
\r
+/**\r
+ Print out information of the device root information.\r
+\r
+ @param[in] PciExpressCap The pointer to the structure about the device.\r
+\r
+ @retval EFI_SUCCESS The operation was successful.\r
+**/\r
EFI_STATUS\r
ExplainPcieRootControl (\r
IN PCIE_CAP_STURCTURE *PciExpressCap\r
-)\r
+ )\r
{\r
UINT16 PcieRootControl;\r
\r
PcieRootControl = PciExpressCap->RootControl;\r
\r
- Print (\r
- L" System Error on Correctable Error Enable(0): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" System Error on Correctable Error Enable(0): %E%d%N\r\n",\r
PCIE_CAP_SYSERR_ON_CORERR_EN (PcieRootControl)\r
);\r
- Print (\r
- L" System Error on Non-Fatal Error Enable(1): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" System Error on Non-Fatal Error Enable(1): %E%d%N\r\n",\r
PCIE_CAP_SYSERR_ON_NONFATERR_EN (PcieRootControl)\r
);\r
- Print (\r
- L" System Error on Fatal Error Enable(2): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" System Error on Fatal Error Enable(2): %E%d%N\r\n",\r
PCIE_CAP_SYSERR_ON_FATERR_EN (PcieRootControl)\r
);\r
- Print (\r
- L" PME Interrupt Enable(3): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" PME Interrupt Enable(3): %E%d%N\r\n",\r
PCIE_CAP_PME_INT_ENABLE (PcieRootControl)\r
);\r
- Print (\r
- L" CRS Software Visibility Enable(4): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" CRS Software Visibility Enable(4): %E%d%N\r\n",\r
PCIE_CAP_CRS_SW_VIS_ENABLE (PcieRootControl)\r
);\r
\r
return EFI_SUCCESS;\r
}\r
\r
+/**\r
+ Print out information of the device root capability information.\r
+\r
+ @param[in] PciExpressCap The pointer to the structure about the device.\r
+\r
+ @retval EFI_SUCCESS The operation was successful.\r
+**/\r
EFI_STATUS\r
ExplainPcieRootCap (\r
IN PCIE_CAP_STURCTURE *PciExpressCap\r
-)\r
+ )\r
{\r
UINT16 PcieRootCap;\r
\r
PcieRootCap = PciExpressCap->RsvdP;\r
\r
- Print (\r
- L" CRS Software Visibility(0): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" CRS Software Visibility(0): %E%d%N\r\n",\r
PCIE_CAP_CRS_SW_VIS (PcieRootCap)\r
);\r
\r
return EFI_SUCCESS;\r
}\r
\r
+/**\r
+ Print out information of the device root status information.\r
+\r
+ @param[in] PciExpressCap The pointer to the structure about the device.\r
+\r
+ @retval EFI_SUCCESS The operation was successful.\r
+**/\r
EFI_STATUS\r
ExplainPcieRootStatus (\r
IN PCIE_CAP_STURCTURE *PciExpressCap\r
-)\r
+ )\r
{\r
UINT32 PcieRootStatus;\r
\r
PcieRootStatus = PciExpressCap->RootStatus;\r
\r
- Print (\r
- L" PME Requester ID(15:0): %E0x%04x%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" PME Requester ID(15:0): %E0x%04x%N\r\n",\r
PCIE_CAP_PME_REQ_ID (PcieRootStatus)\r
);\r
- Print (\r
- L" PME Status(16): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" PME Status(16): %E%d%N\r\n",\r
PCIE_CAP_PME_STATUS (PcieRootStatus)\r
);\r
- Print (\r
- L" PME Pending(17): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" PME Pending(17): %E%d%N\r\n",\r
PCIE_CAP_PME_PENDING (PcieRootStatus)\r
);\r
return EFI_SUCCESS;\r
}\r
\r
+/**\r
+ Function to interpret and print out the link control structure\r
+\r
+ @param[in] HeaderAddress The Address of this capability header.\r
+ @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+PrintInterpretedExtendedCompatibilityLinkControl (\r
+ IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
+ IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
+ )\r
+{\r
+ CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_INTERNAL_LINK_CONTROL *Header;\r
+ Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_INTERNAL_LINK_CONTROL*)HeaderAddress;\r
+\r
+ ShellPrintHiiEx(\r
+ -1, -1, NULL, \r
+ STRING_TOKEN (STR_PCI_EXT_CAP_LINK_CONTROL), \r
+ gShellDebug1HiiHandle, \r
+ Header->RootComplexLinkCapabilities,\r
+ Header->RootComplexLinkControl,\r
+ Header->RootComplexLinkStatus\r
+ ); \r
+ DumpHex (\r
+ 4,\r
+ EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
+ sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_INTERNAL_LINK_CONTROL),\r
+ (VOID *) (HeaderAddress)\r
+ );\r
+ return (EFI_SUCCESS);\r
+}\r
+\r
+/**\r
+ Function to interpret and print out the power budgeting structure\r
+\r
+ @param[in] HeaderAddress The Address of this capability header.\r
+ @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+PrintInterpretedExtendedCompatibilityPowerBudgeting (\r
+ IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
+ IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
+ )\r
+{\r
+ CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_POWER_BUDGETING *Header;\r
+ Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_POWER_BUDGETING*)HeaderAddress;\r
+\r
+ ShellPrintHiiEx(\r
+ -1, -1, NULL, \r
+ STRING_TOKEN (STR_PCI_EXT_CAP_POWER), \r
+ gShellDebug1HiiHandle, \r
+ Header->DataSelect,\r
+ Header->Data,\r
+ Header->PowerBudgetCapability\r
+ ); \r
+ DumpHex (\r
+ 4,\r
+ EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
+ sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_POWER_BUDGETING),\r
+ (VOID *) (HeaderAddress)\r
+ );\r
+ return (EFI_SUCCESS);\r
+}\r
+\r
+/**\r
+ Function to interpret and print out the ACS structure\r
+\r
+ @param[in] HeaderAddress The Address of this capability header.\r
+ @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+PrintInterpretedExtendedCompatibilityAcs (\r
+ IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
+ IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
+ )\r
+{\r
+ CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_ACS_EXTENDED *Header;\r
+ UINT16 VectorSize;\r
+ UINT16 LoopCounter;\r
+\r
+ Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_ACS_EXTENDED*)HeaderAddress;\r
+ VectorSize = 0;\r
+\r
+ ShellPrintHiiEx(\r
+ -1, -1, NULL, \r
+ STRING_TOKEN (STR_PCI_EXT_CAP_ACS), \r
+ gShellDebug1HiiHandle, \r
+ Header->AcsCapability,\r
+ Header->AcsControl\r
+ ); \r
+ if (PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_GET_EGRES_CONTROL(Header)) {\r
+ VectorSize = PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_GET_EGRES_VECTOR_SIZE(Header);\r
+ if (VectorSize == 0) {\r
+ VectorSize = 256;\r
+ }\r
+ for (LoopCounter = 0 ; LoopCounter * 8 < VectorSize ; LoopCounter++) {\r
+ ShellPrintHiiEx(\r
+ -1, -1, NULL, \r
+ STRING_TOKEN (STR_PCI_EXT_CAP_ACS2), \r
+ gShellDebug1HiiHandle, \r
+ LoopCounter + 1,\r
+ Header->EgressControlVectorArray[LoopCounter]\r
+ ); \r
+ }\r
+ }\r
+ DumpHex (\r
+ 4,\r
+ EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
+ sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_ACS_EXTENDED) + (VectorSize / 8) - 1,\r
+ (VOID *) (HeaderAddress)\r
+ );\r
+ return (EFI_SUCCESS);\r
+}\r
+\r
+/**\r
+ Function to interpret and print out the latency tolerance reporting structure\r
+\r
+ @param[in] HeaderAddress The Address of this capability header.\r
+ @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+PrintInterpretedExtendedCompatibilityLatencyToleranceReporting (\r
+ IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
+ IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
+ )\r
+{\r
+ CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_LATENCE_TOLERANCE_REPORTING *Header;\r
+ Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_LATENCE_TOLERANCE_REPORTING*)HeaderAddress;\r
+\r
+ ShellPrintHiiEx(\r
+ -1, -1, NULL, \r
+ STRING_TOKEN (STR_PCI_EXT_CAP_LAT), \r
+ gShellDebug1HiiHandle, \r
+ Header->MaxSnoopLatency,\r
+ Header->MaxNoSnoopLatency\r
+ ); \r
+ DumpHex (\r
+ 4,\r
+ EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
+ sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_LATENCE_TOLERANCE_REPORTING),\r
+ (VOID *) (HeaderAddress)\r
+ );\r
+ return (EFI_SUCCESS);\r
+}\r
+\r
+/**\r
+ Function to interpret and print out the serial number structure\r
+\r
+ @param[in] HeaderAddress The Address of this capability header.\r
+ @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+PrintInterpretedExtendedCompatibilitySerialNumber (\r
+ IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
+ IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
+ )\r
+{\r
+ CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_SERIAL_NUMBER *Header;\r
+ Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_SERIAL_NUMBER*)HeaderAddress;\r
+\r
+ ShellPrintHiiEx(\r
+ -1, -1, NULL, \r
+ STRING_TOKEN (STR_PCI_EXT_CAP_SN), \r
+ gShellDebug1HiiHandle, \r
+ Header->SerialNumber\r
+ ); \r
+ DumpHex (\r
+ 4,\r
+ EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
+ sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_SERIAL_NUMBER),\r
+ (VOID *) (HeaderAddress)\r
+ );\r
+ return (EFI_SUCCESS);\r
+}\r
+\r
+/**\r
+ Function to interpret and print out the RCRB structure\r
+\r
+ @param[in] HeaderAddress The Address of this capability header.\r
+ @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+PrintInterpretedExtendedCompatibilityRcrb (\r
+ IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
+ IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
+ )\r
+{\r
+ CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_RCRB_HEADER *Header;\r
+ Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_RCRB_HEADER*)HeaderAddress;\r
+\r
+ ShellPrintHiiEx(\r
+ -1, -1, NULL, \r
+ STRING_TOKEN (STR_PCI_EXT_CAP_RCRB), \r
+ gShellDebug1HiiHandle, \r
+ Header->VendorId,\r
+ Header->DeviceId,\r
+ Header->RcrbCapabilities,\r
+ Header->RcrbControl\r
+ ); \r
+ DumpHex (\r
+ 4,\r
+ EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
+ sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_RCRB_HEADER),\r
+ (VOID *) (HeaderAddress)\r
+ );\r
+ return (EFI_SUCCESS);\r
+}\r
+\r
+/**\r
+ Function to interpret and print out the vendor specific structure\r
+\r
+ @param[in] HeaderAddress The Address of this capability header.\r
+ @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+PrintInterpretedExtendedCompatibilityVendorSpecific (\r
+ IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
+ IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
+ )\r
+{\r
+ CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_VENDOR_SPECIFIC *Header;\r
+ Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_VENDOR_SPECIFIC*)HeaderAddress;\r
+\r
+ ShellPrintHiiEx(\r
+ -1, -1, NULL, \r
+ STRING_TOKEN (STR_PCI_EXT_CAP_VEN), \r
+ gShellDebug1HiiHandle, \r
+ Header->VendorSpecificHeader\r
+ ); \r
+ DumpHex (\r
+ 4,\r
+ EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
+ PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_GET_SIZE(Header),\r
+ (VOID *) (HeaderAddress)\r
+ );\r
+ return (EFI_SUCCESS);\r
+}\r
+\r
+/**\r
+ Function to interpret and print out the Event Collector Endpoint Association structure\r
+\r
+ @param[in] HeaderAddress The Address of this capability header.\r
+ @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+PrintInterpretedExtendedCompatibilityECEA (\r
+ IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
+ IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
+ )\r
+{\r
+ CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION *Header;\r
+ Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION*)HeaderAddress;\r
+\r
+ ShellPrintHiiEx(\r
+ -1, -1, NULL, \r
+ STRING_TOKEN (STR_PCI_EXT_CAP_ECEA), \r
+ gShellDebug1HiiHandle, \r
+ Header->AssociationBitmap\r
+ ); \r
+ DumpHex (\r
+ 4,\r
+ EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
+ sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION),\r
+ (VOID *) (HeaderAddress)\r
+ );\r
+ return (EFI_SUCCESS);\r
+}\r
+\r
+/**\r
+ Function to interpret and print out the ARI structure\r
+\r
+ @param[in] HeaderAddress The Address of this capability header.\r
+ @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+PrintInterpretedExtendedCompatibilityAri (\r
+ IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
+ IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
+ )\r
+{\r
+ CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_ARI_CAPABILITY *Header;\r
+ Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_ARI_CAPABILITY*)HeaderAddress;\r
+\r
+ ShellPrintHiiEx(\r
+ -1, -1, NULL, \r
+ STRING_TOKEN (STR_PCI_EXT_CAP_ARI), \r
+ gShellDebug1HiiHandle, \r
+ Header->AriCapability,\r
+ Header->AriControl\r
+ ); \r
+ DumpHex (\r
+ 4,\r
+ EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
+ sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_ARI_CAPABILITY),\r
+ (VOID *) (HeaderAddress)\r
+ );\r
+ return (EFI_SUCCESS);\r
+}\r
+\r
+/**\r
+ Function to interpret and print out the DPA structure\r
+\r
+ @param[in] HeaderAddress The Address of this capability header.\r
+ @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+PrintInterpretedExtendedCompatibilityDynamicPowerAllocation (\r
+ IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
+ IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
+ )\r
+{\r
+ CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_DYNAMIC_POWER_ALLOCATION *Header;\r
+ UINT8 LinkCount;\r
+ Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_DYNAMIC_POWER_ALLOCATION*)HeaderAddress;\r
+\r
+ ShellPrintHiiEx(\r
+ -1, -1, NULL, \r
+ STRING_TOKEN (STR_PCI_EXT_CAP_DPA), \r
+ gShellDebug1HiiHandle, \r
+ Header->DpaCapability,\r
+ Header->DpaLatencyIndicator,\r
+ Header->DpaStatus,\r
+ Header->DpaControl\r
+ ); \r
+ for (LinkCount = 0 ; LinkCount < PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_GET_SUBSTATE_MAX(Header) + 1 ; LinkCount++) {\r
+ ShellPrintHiiEx(\r
+ -1, -1, NULL, \r
+ STRING_TOKEN (STR_PCI_EXT_CAP_DPA2), \r
+ gShellDebug1HiiHandle, \r
+ LinkCount+1,\r
+ Header->DpaPowerAllocationArray[LinkCount]\r
+ );\r
+ }\r
+ DumpHex (\r
+ 4,\r
+ EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
+ sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_DYNAMIC_POWER_ALLOCATION) - 1 + PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_GET_SUBSTATE_MAX(Header),\r
+ (VOID *) (HeaderAddress)\r
+ );\r
+ return (EFI_SUCCESS);\r
+}\r
+\r
+/**\r
+ Function to interpret and print out the link declaration structure\r
+\r
+ @param[in] HeaderAddress The Address of this capability header.\r
+ @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+PrintInterpretedExtendedCompatibilityLinkDeclaration (\r
+ IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
+ IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
+ )\r
+{\r
+ CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_LINK_DECLARATION *Header;\r
+ UINT8 LinkCount;\r
+ Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_LINK_DECLARATION*)HeaderAddress;\r
+\r
+ ShellPrintHiiEx(\r
+ -1, -1, NULL, \r
+ STRING_TOKEN (STR_PCI_EXT_CAP_LINK_DECLAR), \r
+ gShellDebug1HiiHandle, \r
+ Header->ElementSelfDescription\r
+ );\r
+\r
+ for (LinkCount = 0 ; LinkCount < PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_GET_LINK_COUNT(Header) ; LinkCount++) {\r
+ ShellPrintHiiEx(\r
+ -1, -1, NULL, \r
+ STRING_TOKEN (STR_PCI_EXT_CAP_LINK_DECLAR2), \r
+ gShellDebug1HiiHandle, \r
+ LinkCount+1,\r
+ Header->LinkEntry[LinkCount]\r
+ );\r
+ }\r
+ DumpHex (\r
+ 4,\r
+ EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
+ sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_LINK_DECLARATION) + (PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_GET_LINK_COUNT(Header)-1)*sizeof(UINT32),\r
+ (VOID *) (HeaderAddress)\r
+ );\r
+ return (EFI_SUCCESS);\r
+}\r
+\r
+/**\r
+ Function to interpret and print out the Advanced Error Reporting structure\r
+\r
+ @param[in] HeaderAddress The Address of this capability header.\r
+ @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+PrintInterpretedExtendedCompatibilityAer (\r
+ IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
+ IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
+ )\r
+{\r
+ CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_ADVANCED_ERROR_REPORTING *Header;\r
+ Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_ADVANCED_ERROR_REPORTING*)HeaderAddress;\r
+\r
+ ShellPrintHiiEx(\r
+ -1, -1, NULL, \r
+ STRING_TOKEN (STR_PCI_EXT_CAP_AER), \r
+ gShellDebug1HiiHandle, \r
+ Header->UncorrectableErrorStatus,\r
+ Header->UncorrectableErrorMask,\r
+ Header->UncorrectableErrorSeverity,\r
+ Header->CorrectableErrorStatus,\r
+ Header->CorrectableErrorMask,\r
+ Header->AdvancedErrorCapabilitiesAndControl,\r
+ Header->HeaderLog,\r
+ Header->RootErrorCommand,\r
+ Header->RootErrorStatus,\r
+ Header->ErrorSourceIdentification,\r
+ Header->CorrectableErrorSourceIdentification,\r
+ Header->TlpPrefixLog[0],\r
+ Header->TlpPrefixLog[1],\r
+ Header->TlpPrefixLog[2],\r
+ Header->TlpPrefixLog[3]\r
+ );\r
+ DumpHex (\r
+ 4,\r
+ EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
+ sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_ADVANCED_ERROR_REPORTING),\r
+ (VOID *) (HeaderAddress)\r
+ );\r
+ return (EFI_SUCCESS);\r
+}\r
+\r
+/**\r
+ Function to interpret and print out the multicast structure\r
+\r
+ @param[in] HeaderAddress The Address of this capability header.\r
+ @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
+ @param[in] PciExpressCapPtr The address of the PCIe capabilities structure.\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+PrintInterpretedExtendedCompatibilityMulticast (\r
+ IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
+ IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress,\r
+ IN CONST PCIE_CAP_STURCTURE *PciExpressCapPtr\r
+ )\r
+{\r
+ CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTICAST *Header;\r
+ Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTICAST*)HeaderAddress;\r
+\r
+ ShellPrintHiiEx(\r
+ -1, -1, NULL, \r
+ STRING_TOKEN (STR_PCI_EXT_CAP_MULTICAST), \r
+ gShellDebug1HiiHandle, \r
+ Header->MultiCastCapability,\r
+ Header->MulticastControl,\r
+ Header->McBaseAddress,\r
+ Header->McReceiveAddress,\r
+ Header->McBlockAll,\r
+ Header->McBlockUntranslated,\r
+ Header->McOverlayBar\r
+ );\r
+\r
+ DumpHex (\r
+ 4,\r
+ EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
+ sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTICAST),\r
+ (VOID *) (HeaderAddress)\r
+ );\r
+\r
+ return (EFI_SUCCESS);\r
+}\r
+\r
+/**\r
+ Function to interpret and print out the virtual channel and multi virtual channel structure\r
+\r
+ @param[in] HeaderAddress The Address of this capability header.\r
+ @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+PrintInterpretedExtendedCompatibilityVirtualChannel (\r
+ IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
+ IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
+ )\r
+{\r
+ CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY *Header;\r
+ CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_VC *CapabilityItem;\r
+ UINT32 ItemCount;\r
+ Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY*)HeaderAddress;\r
+\r
+ ShellPrintHiiEx(\r
+ -1, -1, NULL, \r
+ STRING_TOKEN (STR_PCI_EXT_CAP_VC_BASE), \r
+ gShellDebug1HiiHandle, \r
+ Header->ExtendedVcCount,\r
+ Header->PortVcCapability1,\r
+ Header->PortVcCapability2,\r
+ Header->VcArbTableOffset,\r
+ Header->PortVcControl,\r
+ Header->PortVcStatus\r
+ );\r
+ for (ItemCount = 0 ; ItemCount < Header->ExtendedVcCount ; ItemCount++) {\r
+ CapabilityItem = &Header->Capability[ItemCount];\r
+ ShellPrintHiiEx(\r
+ -1, -1, NULL, \r
+ STRING_TOKEN (STR_PCI_EXT_CAP_VC_ITEM), \r
+ gShellDebug1HiiHandle, \r
+ ItemCount+1,\r
+ CapabilityItem->VcResourceCapability,\r
+ CapabilityItem->PortArbTableOffset,\r
+ CapabilityItem->VcResourceControl,\r
+ CapabilityItem->VcResourceStatus\r
+ );\r
+ }\r
+\r
+ DumpHex (\r
+ 4,\r
+ EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
+ sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_VC) + (Header->ExtendedVcCount - 1) * sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY),\r
+ (VOID *) (HeaderAddress)\r
+ );\r
+\r
+ return (EFI_SUCCESS);\r
+}\r
+\r
+/**\r
+ Function to interpret and print out the resizeable bar structure\r
+\r
+ @param[in] HeaderAddress The Address of this capability header.\r
+ @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+PrintInterpretedExtendedCompatibilityResizeableBar (\r
+ IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
+ IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
+ )\r
+{\r
+ CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR *Header;\r
+ UINT32 ItemCount;\r
+ Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR*)HeaderAddress;\r
+\r
+ for (ItemCount = 0 ; ItemCount < (UINT32)GET_NUMBER_RESIZABLE_BARS(Header) ; ItemCount++) {\r
+ ShellPrintHiiEx(\r
+ -1, -1, NULL, \r
+ STRING_TOKEN (STR_PCI_EXT_CAP_RESIZE_BAR), \r
+ gShellDebug1HiiHandle, \r
+ ItemCount+1,\r
+ Header->Capability[ItemCount].ResizableBarCapability,\r
+ Header->Capability[ItemCount].ResizableBarControl\r
+ );\r
+ }\r
+\r
+ DumpHex (\r
+ 4,\r
+ EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
+ (UINT32)GET_NUMBER_RESIZABLE_BARS(Header) * sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_ENTRY),\r
+ (VOID *) (HeaderAddress)\r
+ );\r
+\r
+ return (EFI_SUCCESS);\r
+}\r
+\r
+/**\r
+ Function to interpret and print out the TPH structure\r
+\r
+ @param[in] HeaderAddress The Address of this capability header.\r
+ @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+PrintInterpretedExtendedCompatibilityTph (\r
+ IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
+ IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
+ )\r
+{\r
+ CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_TPH *Header;\r
+ Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_TPH*)HeaderAddress;\r
+\r
+ ShellPrintHiiEx(\r
+ -1, -1, NULL, \r
+ STRING_TOKEN (STR_PCI_EXT_CAP_TPH), \r
+ gShellDebug1HiiHandle, \r
+ Header->TphRequesterCapability,\r
+ Header->TphRequesterControl\r
+ );\r
+ DumpHex (\r
+ 8,\r
+ EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)Header->TphStTable - (UINT8*)HeadersBaseAddress),\r
+ GET_TPH_TABLE_SIZE(Header),\r
+ (VOID *)Header->TphStTable\r
+ );\r
+\r
+ DumpHex (\r
+ 4,\r
+ EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
+ sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_TPH) + GET_TPH_TABLE_SIZE(Header) - sizeof(UINT16),\r
+ (VOID *) (HeaderAddress)\r
+ );\r
+\r
+ return (EFI_SUCCESS);\r
+}\r
+\r
+/**\r
+ Function to interpret and print out the secondary PCIe capability structure\r
+\r
+ @param[in] HeaderAddress The Address of this capability header.\r
+ @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
+ @param[in] PciExpressCapPtr The address of the PCIe capabilities structure.\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+PrintInterpretedExtendedCompatibilitySecondary (\r
+ IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
+ IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress,\r
+ IN CONST PCIE_CAP_STURCTURE *PciExpressCapPtr\r
+ )\r
+{\r
+ CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_SECONDARY_PCIE *Header;\r
+ Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_SECONDARY_PCIE*)HeaderAddress;\r
+\r
+ ShellPrintHiiEx(\r
+ -1, -1, NULL, \r
+ STRING_TOKEN (STR_PCI_EXT_CAP_SECONDARY), \r
+ gShellDebug1HiiHandle, \r
+ Header->LinkControl3,\r
+ Header->LaneErrorStatus\r
+ );\r
+ DumpHex (\r
+ 8,\r
+ EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)Header->EqualizationControl - (UINT8*)HeadersBaseAddress),\r
+ PCIE_CAP_MAX_LINK_WIDTH(PciExpressCapPtr->LinkCap),\r
+ (VOID *)Header->EqualizationControl\r
+ );\r
+\r
+ DumpHex (\r
+ 4,\r
+ EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
+ sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_TPH) - sizeof(Header->EqualizationControl) + PCIE_CAP_MAX_LINK_WIDTH(PciExpressCapPtr->LinkCap),\r
+ (VOID *) (HeaderAddress)\r
+ );\r
+\r
+ return (EFI_SUCCESS);\r
+}\r
+\r
+/**\r
+ Display Pcie extended capability details\r
+\r
+ @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
+ @param[in] HeaderAddress The address of this capability header.\r
+ @param[in] PciExpressCapPtr The address of the PCIe capabilities structure.\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+PrintPciExtendedCapabilityDetails(\r
+ IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress, \r
+ IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
+ IN CONST PCIE_CAP_STURCTURE *PciExpressCapPtr\r
+ )\r
+{\r
+ switch (HeaderAddress->CapabilityId){\r
+ case PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_ID:\r
+ return PrintInterpretedExtendedCompatibilityAer(HeaderAddress, HeadersBaseAddress);\r
+ break;\r
+ case PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_CONTROL_ID:\r
+ return PrintInterpretedExtendedCompatibilityLinkControl(HeaderAddress, HeadersBaseAddress);\r
+ break;\r
+ case PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_ID:\r
+ return PrintInterpretedExtendedCompatibilityLinkDeclaration(HeaderAddress, HeadersBaseAddress);\r
+ break;\r
+ case PCI_EXPRESS_EXTENDED_CAPABILITY_SERIAL_NUMBER_ID:\r
+ return PrintInterpretedExtendedCompatibilitySerialNumber(HeaderAddress, HeadersBaseAddress);\r
+ break;\r
+ case PCI_EXPRESS_EXTENDED_CAPABILITY_POWER_BUDGETING_ID:\r
+ return PrintInterpretedExtendedCompatibilityPowerBudgeting(HeaderAddress, HeadersBaseAddress);\r
+ break;\r
+ case PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_ID:\r
+ return PrintInterpretedExtendedCompatibilityAcs(HeaderAddress, HeadersBaseAddress);\r
+ break;\r
+ case PCI_EXPRESS_EXTENDED_CAPABILITY_LATENCE_TOLERANCE_REPORTING_ID:\r
+ return PrintInterpretedExtendedCompatibilityLatencyToleranceReporting(HeaderAddress, HeadersBaseAddress);\r
+ break;\r
+ case PCI_EXPRESS_EXTENDED_CAPABILITY_ARI_CAPABILITY_ID:\r
+ return PrintInterpretedExtendedCompatibilityAri(HeaderAddress, HeadersBaseAddress);\r
+ break;\r
+ case PCI_EXPRESS_EXTENDED_CAPABILITY_RCRB_HEADER_ID:\r
+ return PrintInterpretedExtendedCompatibilityRcrb(HeaderAddress, HeadersBaseAddress);\r
+ break;\r
+ case PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_ID:\r
+ return PrintInterpretedExtendedCompatibilityVendorSpecific(HeaderAddress, HeadersBaseAddress);\r
+ break;\r
+ case PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_ID:\r
+ return PrintInterpretedExtendedCompatibilityDynamicPowerAllocation(HeaderAddress, HeadersBaseAddress);\r
+ break;\r
+ case PCI_EXPRESS_EXTENDED_CAPABILITY_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION_ID:\r
+ return PrintInterpretedExtendedCompatibilityECEA(HeaderAddress, HeadersBaseAddress);\r
+ break;\r
+ case PCI_EXPRESS_EXTENDED_CAPABILITY_VIRTUAL_CHANNEL_ID:\r
+ case PCI_EXPRESS_EXTENDED_CAPABILITY_MULTI_FUNCTION_VIRTUAL_CHANNEL_ID:\r
+ return PrintInterpretedExtendedCompatibilityVirtualChannel(HeaderAddress, HeadersBaseAddress);\r
+ break;\r
+ case PCI_EXPRESS_EXTENDED_CAPABILITY_MULTICAST_ID: \r
+ //\r
+ // should only be present if PCIE_CAP_DEVICEPORT_TYPE(PciExpressCapPtr->PcieCapReg) == 0100b, 0101b, or 0110b\r
+ //\r
+ return PrintInterpretedExtendedCompatibilityMulticast(HeaderAddress, HeadersBaseAddress, PciExpressCapPtr);\r
+ break;\r
+ case PCI_EXPRESS_EXTENDED_CAPABILITY_RESIZABLE_BAR_ID:\r
+ return PrintInterpretedExtendedCompatibilityResizeableBar(HeaderAddress, HeadersBaseAddress);\r
+ break;\r
+ case PCI_EXPRESS_EXTENDED_CAPABILITY_TPH_ID:\r
+ return PrintInterpretedExtendedCompatibilityTph(HeaderAddress, HeadersBaseAddress);\r
+ break;\r
+ case PCI_EXPRESS_EXTENDED_CAPABILITY_SECONDARY_PCIE_ID:\r
+ return PrintInterpretedExtendedCompatibilitySecondary(HeaderAddress, HeadersBaseAddress, PciExpressCapPtr);\r
+ break;\r
+ default:\r
+ ShellPrintEx (-1, -1,\r
+ L"Unknown PCIe extended capability ID (%04xh). No interpretation available.\r\n",\r
+ HeaderAddress->CapabilityId\r
+ );\r
+ return EFI_SUCCESS;\r
+ break;\r
+ };\r
+\r
+}\r
+\r
+/**\r
+ Display Pcie device structure.\r
+\r
+ @param[in] IoDev The pointer to the root pci protocol.\r
+ @param[in] Address The Address to start at.\r
+ @param[in] CapabilityPtr The offset from the address to start.\r
+**/\r
EFI_STATUS\r
PciExplainPciExpress (\r
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r
IN UINT64 Address,\r
- IN UINT8 CapabilityPtr\r
+ IN UINT8 CapabilityPtr,\r
+ IN CONST UINT16 EnhancedDump\r
)\r
{\r
\r
UINTN Index;\r
UINT8 *RegAddr;\r
UINTN RegValue;\r
+ PCI_EXP_EXT_HDR *ExtHdr;\r
\r
CapRegAddress = Address + CapabilityPtr;\r
IoDev->Pci.Read (\r
\r
DevicePortType = (UINT8) PCIE_CAP_DEVICEPORT_TYPE (PciExpressCap.PcieCapReg);\r
\r
- Print (L"\nPci Express device capability structure:\n");\r
+ ShellPrintEx (-1, -1, L"\r\nPci Express device capability structure:\r\n");\r
\r
for (Index = 0; PcieExplainList[Index].Type < PcieExplainTypeMax; Index++) {\r
if (ShellGetExecutionBreakFlag()) {\r
Dev = (UINT8) (RShiftU64 (Address, 16));\r
Func = (UINT8) (RShiftU64 (Address, 8));\r
\r
- Pciex_Address = CALC_EFI_PCIEX_ADDRESS (Bus, Dev, Func, 0x100);\r
+ Pciex_Address = CALC_EFI_PCIEX_ADDRESS (Bus, Dev, Func, EFI_PCIE_CAPABILITY_BASE_OFFSET);\r
\r
- ExtendRegSize = 0x1000 - 0x100;\r
+ ExtendRegSize = 0x1000 - EFI_PCIE_CAPABILITY_BASE_OFFSET;\r
\r
- ExRegBuffer = (UINT8 *) AllocatePool (ExtendRegSize);\r
+ ExRegBuffer = (UINT8 *) AllocateZeroPool (ExtendRegSize);\r
\r
//\r
// PciRootBridgeIo protocol should support pci express extend space IO\r
- // (Begins at offset 0x100)\r
+ // (Begins at offset EFI_PCIE_CAPABILITY_BASE_OFFSET)\r
//\r
Status = IoDev->Pci.Read (\r
IoDev,\r
(ExtendRegSize) / sizeof (UINT32),\r
(VOID *) (ExRegBuffer)\r
);\r
- if (EFI_ERROR (Status)) {\r
- FreePool ((VOID *) ExRegBuffer);\r
+ if (EFI_ERROR (Status) || ExRegBuffer == NULL) {\r
+ SHELL_FREE_NON_NULL(ExRegBuffer);\r
return EFI_UNSUPPORTED;\r
}\r
- //\r
- // Start outputing PciEx extend space( 0xFF-0xFFF)\r
- //\r
- Print (L"\n%HStart dumping PCIex extended configuration space (0x100 - 0xFFF).%N\n\n");\r
\r
- PrivateDumpHex (\r
- 2,\r
- 0x100,\r
- ExtendRegSize,\r
- (VOID *) (ExRegBuffer)\r
- );\r
+ if (EnhancedDump == 0) {\r
+ //\r
+ // Print the PciEx extend space in raw bytes ( 0xFF-0xFFF)\r
+ //\r
+ ShellPrintEx (-1, -1, L"\r\n%HStart dumping PCIex extended configuration space (0x100 - 0xFFF).%N\r\n\r\n");\r
+\r
+ DumpHex (\r
+ 2,\r
+ EFI_PCIE_CAPABILITY_BASE_OFFSET,\r
+ ExtendRegSize,\r
+ (VOID *) (ExRegBuffer)\r
+ );\r
+ } else {\r
+ ExtHdr = (PCI_EXP_EXT_HDR*)ExRegBuffer;\r
+ while (ExtHdr->CapabilityId != 0 && ExtHdr->CapabilityVersion != 0) {\r
+ //\r
+ // Process this item\r
+ //\r
+ if (EnhancedDump == 0xFFFF || EnhancedDump == ExtHdr->CapabilityId) {\r
+ //\r
+ // Print this item\r
+ //\r
+ PrintPciExtendedCapabilityDetails((PCI_EXP_EXT_HDR*)ExRegBuffer, ExtHdr, &PciExpressCap);\r
+ }\r
\r
- FreePool ((VOID *) ExRegBuffer);\r
+ //\r
+ // Advance to the next item if it exists\r
+ //\r
+ if (ExtHdr->NextCapabilityOffset != 0) {\r
+ ExtHdr = (PCI_EXP_EXT_HDR*)((UINT8*)ExRegBuffer + ExtHdr->NextCapabilityOffset);\r
+ } else {\r
+ break;\r
+ }\r
+ }\r
+ }\r
+ SHELL_FREE_NON_NULL(ExRegBuffer);\r
\r
Done:\r
return EFI_SUCCESS;\r
projects / mirror_edk2.git / blobdiff