/** @file\r
IA32 register defintions needed by debug transfer protocol.\r
\r
- Copyright (c) 2010, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2010 - 2011, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
#ifndef _ARCH_REGISTERS_H_\r
#define _ARCH_REGISTERS_H_\r
\r
+#pragma pack(1)\r
+\r
///\r
/// FXSAVE_STATE\r
/// FP / MMX / XMM registers (see fxrstor instruction definition)\r
UINT32 TssBas;\r
} DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_SEGBASE_IA32;\r
\r
+#pragma pack()\r
+\r
#endif\r