+++ /dev/null
-/* $NetBSD: cpufunc.h,v 1.37.24.1 2007/02/21 18:36:02 snj Exp $ */\r
-\r
-/*\r
- * Copyright (c) 1997 Mark Brinicombe.\r
- * Copyright (c) 1997 Causality Limited\r
- * All rights reserved.\r
- *\r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions\r
- * are met:\r
- * 1. Redistributions of source code must retain the above copyright\r
- * notice, this list of conditions and the following disclaimer.\r
- * 2. Redistributions in binary form must reproduce the above copyright\r
- * notice, this list of conditions and the following disclaimer in the\r
- * documentation and/or other materials provided with the distribution.\r
- * 3. All advertising materials mentioning features or use of this software\r
- * must display the following acknowledgement:\r
- * This product includes software developed by Causality Limited.\r
- * 4. The name of Causality Limited may not be used to endorse or promote\r
- * products derived from this software without specific prior written\r
- * permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY CAUSALITY LIMITED ``AS IS'' AND ANY EXPRESS\r
- * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\r
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
- * DISCLAIMED. IN NO EVENT SHALL CAUSALITY LIMITED BE LIABLE FOR ANY DIRECT,\r
- * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\r
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\r
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\r
- * SUCH DAMAGE.\r
- *\r
- * RiscBSD kernel project\r
- *\r
- * cpufunc.h\r
- *\r
- * Prototypes for cpu, mmu and tlb related functions.\r
- */\r
-\r
-#ifndef _ARM32_CPUFUNC_H_\r
-#define _ARM32_CPUFUNC_H_\r
-\r
-#ifdef _KERNEL\r
-\r
-#include <sys/types.h>\r
-#include <arm/cpuconf.h>\r
-\r
-struct cpu_functions {\r
-\r
- /* CPU functions */\r
-\r
- u_int (*cf_id) __P((void));\r
- void (*cf_cpwait) __P((void));\r
-\r
- /* MMU functions */\r
-\r
- u_int (*cf_control) __P((u_int, u_int));\r
- void (*cf_domains) __P((u_int));\r
- void (*cf_setttb) __P((u_int));\r
- u_int (*cf_faultstatus) __P((void));\r
- u_int (*cf_faultaddress) __P((void));\r
-\r
- /* TLB functions */\r
-\r
- void (*cf_tlb_flushID) __P((void));\r
- void (*cf_tlb_flushID_SE) __P((u_int));\r
- void (*cf_tlb_flushI) __P((void));\r
- void (*cf_tlb_flushI_SE) __P((u_int));\r
- void (*cf_tlb_flushD) __P((void));\r
- void (*cf_tlb_flushD_SE) __P((u_int));\r
-\r
- /*\r
- * Cache operations:\r
- *\r
- * We define the following primitives:\r
- *\r
- * icache_sync_all Synchronize I-cache\r
- * icache_sync_range Synchronize I-cache range\r
- *\r
- * dcache_wbinv_all Write-back and Invalidate D-cache\r
- * dcache_wbinv_range Write-back and Invalidate D-cache range\r
- * dcache_inv_range Invalidate D-cache range\r
- * dcache_wb_range Write-back D-cache range\r
- *\r
- * idcache_wbinv_all Write-back and Invalidate D-cache,\r
- * Invalidate I-cache\r
- * idcache_wbinv_range Write-back and Invalidate D-cache,\r
- * Invalidate I-cache range\r
- *\r
- * Note that the ARM term for "write-back" is "clean". We use\r
- * the term "write-back" since it's a more common way to describe\r
- * the operation.\r
- *\r
- * There are some rules that must be followed:\r
- *\r
- * I-cache Synch (all or range):\r
- * The goal is to synchronize the instruction stream,\r
- * so you may beed to write-back dirty D-cache blocks\r
- * first. If a range is requested, and you can't\r
- * synchronize just a range, you have to hit the whole\r
- * thing.\r
- *\r
- * D-cache Write-Back and Invalidate range:\r
- * If you can't WB-Inv a range, you must WB-Inv the\r
- * entire D-cache.\r
- *\r
- * D-cache Invalidate:\r
- * If you can't Inv the D-cache, you must Write-Back\r
- * and Invalidate. Code that uses this operation\r
- * MUST NOT assume that the D-cache will not be written\r
- * back to memory.\r
- *\r
- * D-cache Write-Back:\r
- * If you can't Write-back without doing an Inv,\r
- * that's fine. Then treat this as a WB-Inv.\r
- * Skipping the invalidate is merely an optimization.\r
- *\r
- * All operations:\r
- * Valid virtual addresses must be passed to each\r
- * cache operation.\r
- */\r
- void (*cf_icache_sync_all) __P((void));\r
- void (*cf_icache_sync_range) __P((vaddr_t, vsize_t));\r
-\r
- void (*cf_dcache_wbinv_all) __P((void));\r
- void (*cf_dcache_wbinv_range) __P((vaddr_t, vsize_t));\r
- void (*cf_dcache_inv_range) __P((vaddr_t, vsize_t));\r
- void (*cf_dcache_wb_range) __P((vaddr_t, vsize_t));\r
-\r
- void (*cf_idcache_wbinv_all) __P((void));\r
- void (*cf_idcache_wbinv_range) __P((vaddr_t, vsize_t));\r
-\r
- /* Other functions */\r
-\r
- void (*cf_flush_prefetchbuf) __P((void));\r
- void (*cf_drain_writebuf) __P((void));\r
- void (*cf_flush_brnchtgt_C) __P((void));\r
- void (*cf_flush_brnchtgt_E) __P((u_int));\r
-\r
- void (*cf_sleep) __P((int mode));\r
-\r
- /* Soft functions */\r
-\r
- int (*cf_dataabt_fixup) __P((void *));\r
- int (*cf_prefetchabt_fixup) __P((void *));\r
-\r
- void (*cf_context_switch) __P((void));\r
-\r
- void (*cf_setup) __P((char *));\r
-};\r
-\r
-extern struct cpu_functions cpufuncs;\r
-extern u_int cputype;\r
-\r
-#define cpu_id() cpufuncs.cf_id()\r
-#define cpu_cpwait() cpufuncs.cf_cpwait()\r
-\r
-#define cpu_control(c, e) cpufuncs.cf_control(c, e)\r
-#define cpu_domains(d) cpufuncs.cf_domains(d)\r
-#define cpu_setttb(t) cpufuncs.cf_setttb(t)\r
-#define cpu_faultstatus() cpufuncs.cf_faultstatus()\r
-#define cpu_faultaddress() cpufuncs.cf_faultaddress()\r
-\r
-#define cpu_tlb_flushID() cpufuncs.cf_tlb_flushID()\r
-#define cpu_tlb_flushID_SE(e) cpufuncs.cf_tlb_flushID_SE(e)\r
-#define cpu_tlb_flushI() cpufuncs.cf_tlb_flushI()\r
-#define cpu_tlb_flushI_SE(e) cpufuncs.cf_tlb_flushI_SE(e)\r
-#define cpu_tlb_flushD() cpufuncs.cf_tlb_flushD()\r
-#define cpu_tlb_flushD_SE(e) cpufuncs.cf_tlb_flushD_SE(e)\r
-\r
-#define cpu_icache_sync_all() cpufuncs.cf_icache_sync_all()\r
-#define cpu_icache_sync_range(a, s) cpufuncs.cf_icache_sync_range((a), (s))\r
-\r
-#define cpu_dcache_wbinv_all() cpufuncs.cf_dcache_wbinv_all()\r
-#define cpu_dcache_wbinv_range(a, s) cpufuncs.cf_dcache_wbinv_range((a), (s))\r
-#define cpu_dcache_inv_range(a, s) cpufuncs.cf_dcache_inv_range((a), (s))\r
-#define cpu_dcache_wb_range(a, s) cpufuncs.cf_dcache_wb_range((a), (s))\r
-\r
-#define cpu_idcache_wbinv_all() cpufuncs.cf_idcache_wbinv_all()\r
-#define cpu_idcache_wbinv_range(a, s) cpufuncs.cf_idcache_wbinv_range((a), (s))\r
-\r
-#define cpu_flush_prefetchbuf() cpufuncs.cf_flush_prefetchbuf()\r
-#define cpu_drain_writebuf() cpufuncs.cf_drain_writebuf()\r
-#define cpu_flush_brnchtgt_C() cpufuncs.cf_flush_brnchtgt_C()\r
-#define cpu_flush_brnchtgt_E(e) cpufuncs.cf_flush_brnchtgt_E(e)\r
-\r
-#define cpu_sleep(m) cpufuncs.cf_sleep(m)\r
-\r
-#define cpu_dataabt_fixup(a) cpufuncs.cf_dataabt_fixup(a)\r
-#define cpu_prefetchabt_fixup(a) cpufuncs.cf_prefetchabt_fixup(a)\r
-#define ABORT_FIXUP_OK 0 /* fixup succeeded */\r
-#define ABORT_FIXUP_FAILED 1 /* fixup failed */\r
-#define ABORT_FIXUP_RETURN 2 /* abort handler should return */\r
-\r
-#define cpu_setup(a) cpufuncs.cf_setup(a)\r
-\r
-int set_cpufuncs __P((void));\r
-#define ARCHITECTURE_NOT_PRESENT 1 /* known but not configured */\r
-#define ARCHITECTURE_NOT_SUPPORTED 2 /* not known */\r
-\r
-void cpufunc_nullop __P((void));\r
-int cpufunc_null_fixup __P((void *));\r
-int early_abort_fixup __P((void *));\r
-int late_abort_fixup __P((void *));\r
-u_int cpufunc_id __P((void));\r
-u_int cpufunc_control __P((u_int, u_int));\r
-void cpufunc_domains __P((u_int));\r
-u_int cpufunc_faultstatus __P((void));\r
-u_int cpufunc_faultaddress __P((void));\r
-\r
-#ifdef CPU_ARM3\r
-u_int arm3_control __P((u_int, u_int));\r
-void arm3_cache_flush __P((void));\r
-#endif /* CPU_ARM3 */\r
-\r
-#if defined(CPU_ARM6) || defined(CPU_ARM7)\r
-void arm67_setttb __P((u_int));\r
-void arm67_tlb_flush __P((void));\r
-void arm67_tlb_purge __P((u_int));\r
-void arm67_cache_flush __P((void));\r
-void arm67_context_switch __P((void));\r
-#endif /* CPU_ARM6 || CPU_ARM7 */\r
-\r
-#ifdef CPU_ARM6\r
-void arm6_setup __P((char *));\r
-#endif /* CPU_ARM6 */\r
-\r
-#ifdef CPU_ARM7\r
-void arm7_setup __P((char *));\r
-#endif /* CPU_ARM7 */\r
-\r
-#ifdef CPU_ARM7TDMI\r
-int arm7_dataabt_fixup __P((void *));\r
-void arm7tdmi_setup __P((char *));\r
-void arm7tdmi_setttb __P((u_int));\r
-void arm7tdmi_tlb_flushID __P((void));\r
-void arm7tdmi_tlb_flushID_SE __P((u_int));\r
-void arm7tdmi_cache_flushID __P((void));\r
-void arm7tdmi_context_switch __P((void));\r
-#endif /* CPU_ARM7TDMI */\r
-\r
-#ifdef CPU_ARM8\r
-void arm8_setttb __P((u_int));\r
-void arm8_tlb_flushID __P((void));\r
-void arm8_tlb_flushID_SE __P((u_int));\r
-void arm8_cache_flushID __P((void));\r
-void arm8_cache_flushID_E __P((u_int));\r
-void arm8_cache_cleanID __P((void));\r
-void arm8_cache_cleanID_E __P((u_int));\r
-void arm8_cache_purgeID __P((void));\r
-void arm8_cache_purgeID_E __P((u_int entry));\r
-\r
-void arm8_cache_syncI __P((void));\r
-void arm8_cache_cleanID_rng __P((vaddr_t, vsize_t));\r
-void arm8_cache_cleanD_rng __P((vaddr_t, vsize_t));\r
-void arm8_cache_purgeID_rng __P((vaddr_t, vsize_t));\r
-void arm8_cache_purgeD_rng __P((vaddr_t, vsize_t));\r
-void arm8_cache_syncI_rng __P((vaddr_t, vsize_t));\r
-\r
-void arm8_context_switch __P((void));\r
-\r
-void arm8_setup __P((char *));\r
-\r
-u_int arm8_clock_config __P((u_int, u_int));\r
-#endif\r
-\r
-#ifdef CPU_SA110\r
-void sa110_setup __P((char *));\r
-void sa110_context_switch __P((void));\r
-#endif /* CPU_SA110 */\r
-\r
-#if defined(CPU_SA1100) || defined(CPU_SA1110)\r
-void sa11x0_drain_readbuf __P((void));\r
-\r
-void sa11x0_context_switch __P((void));\r
-void sa11x0_cpu_sleep __P((int));\r
-\r
-void sa11x0_setup __P((char *));\r
-#endif\r
-\r
-#if defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110)\r
-void sa1_setttb __P((u_int));\r
-\r
-void sa1_tlb_flushID_SE __P((u_int));\r
-\r
-void sa1_cache_flushID __P((void));\r
-void sa1_cache_flushI __P((void));\r
-void sa1_cache_flushD __P((void));\r
-void sa1_cache_flushD_SE __P((u_int));\r
-\r
-void sa1_cache_cleanID __P((void));\r
-void sa1_cache_cleanD __P((void));\r
-void sa1_cache_cleanD_E __P((u_int));\r
-\r
-void sa1_cache_purgeID __P((void));\r
-void sa1_cache_purgeID_E __P((u_int));\r
-void sa1_cache_purgeD __P((void));\r
-void sa1_cache_purgeD_E __P((u_int));\r
-\r
-void sa1_cache_syncI __P((void));\r
-void sa1_cache_cleanID_rng __P((vaddr_t, vsize_t));\r
-void sa1_cache_cleanD_rng __P((vaddr_t, vsize_t));\r
-void sa1_cache_purgeID_rng __P((vaddr_t, vsize_t));\r
-void sa1_cache_purgeD_rng __P((vaddr_t, vsize_t));\r
-void sa1_cache_syncI_rng __P((vaddr_t, vsize_t));\r
-\r
-#endif\r
-\r
-#ifdef CPU_ARM9\r
-void arm9_setttb __P((u_int));\r
-\r
-void arm9_tlb_flushID_SE __P((u_int));\r
-\r
-void arm9_icache_sync_all __P((void));\r
-void arm9_icache_sync_range __P((vaddr_t, vsize_t));\r
-\r
-void arm9_dcache_wbinv_all __P((void));\r
-void arm9_dcache_wbinv_range __P((vaddr_t, vsize_t));\r
-void arm9_dcache_inv_range __P((vaddr_t, vsize_t));\r
-void arm9_dcache_wb_range __P((vaddr_t, vsize_t));\r
-\r
-void arm9_idcache_wbinv_all __P((void));\r
-void arm9_idcache_wbinv_range __P((vaddr_t, vsize_t));\r
-\r
-void arm9_context_switch __P((void));\r
-\r
-void arm9_setup __P((char *));\r
-\r
-extern unsigned arm9_dcache_sets_max;\r
-extern unsigned arm9_dcache_sets_inc;\r
-extern unsigned arm9_dcache_index_max;\r
-extern unsigned arm9_dcache_index_inc;\r
-#endif\r
-\r
-#if defined(CPU_ARM9E) || defined(CPU_ARM10)\r
-void arm10_tlb_flushID_SE __P((u_int));\r
-void arm10_tlb_flushI_SE __P((u_int));\r
-\r
-void arm10_context_switch __P((void));\r
-\r
-void arm10_setup __P((char *));\r
-#endif\r
-\r
-#ifdef CPU_ARM11\r
-void arm11_setttb __P((u_int));\r
-\r
-void arm11_tlb_flushID_SE __P((u_int));\r
-void arm11_tlb_flushI_SE __P((u_int));\r
-\r
-void arm11_context_switch __P((void));\r
-\r
-void arm11_setup __P((char *string));\r
-void arm11_tlb_flushID __P((void));\r
-void arm11_tlb_flushI __P((void));\r
-void arm11_tlb_flushD __P((void));\r
-void arm11_tlb_flushD_SE __P((u_int va));\r
-\r
-void arm11_drain_writebuf __P((void));\r
-#endif\r
-\r
-#if defined(CPU_ARM9E) || defined (CPU_ARM10)\r
-void armv5_ec_setttb __P((u_int));\r
-\r
-void armv5_ec_icache_sync_all __P((void));\r
-void armv5_ec_icache_sync_range __P((vaddr_t, vsize_t));\r
-\r
-void armv5_ec_dcache_wbinv_all __P((void));\r
-void armv5_ec_dcache_wbinv_range __P((vaddr_t, vsize_t));\r
-void armv5_ec_dcache_inv_range __P((vaddr_t, vsize_t));\r
-void armv5_ec_dcache_wb_range __P((vaddr_t, vsize_t));\r
-\r
-void armv5_ec_idcache_wbinv_all __P((void));\r
-void armv5_ec_idcache_wbinv_range __P((vaddr_t, vsize_t));\r
-#endif\r
-\r
-#if defined (CPU_ARM10) || defined (CPU_ARM11)\r
-void armv5_setttb __P((u_int));\r
-\r
-void armv5_icache_sync_all __P((void));\r
-void armv5_icache_sync_range __P((vaddr_t, vsize_t));\r
-\r
-void armv5_dcache_wbinv_all __P((void));\r
-void armv5_dcache_wbinv_range __P((vaddr_t, vsize_t));\r
-void armv5_dcache_inv_range __P((vaddr_t, vsize_t));\r
-void armv5_dcache_wb_range __P((vaddr_t, vsize_t));\r
-\r
-void armv5_idcache_wbinv_all __P((void));\r
-void armv5_idcache_wbinv_range __P((vaddr_t, vsize_t));\r
-\r
-extern unsigned armv5_dcache_sets_max;\r
-extern unsigned armv5_dcache_sets_inc;\r
-extern unsigned armv5_dcache_index_max;\r
-extern unsigned armv5_dcache_index_inc;\r
-#endif\r
-\r
-#if defined(CPU_ARM9) || defined(CPU_ARM9E) || defined(CPU_ARM10) || \\r
- defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110) || \\r
- defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \\r
- defined(__CPU_XSCALE_PXA2XX) || defined(CPU_XSCALE_IXP425)\r
-\r
-void armv4_tlb_flushID __P((void));\r
-void armv4_tlb_flushI __P((void));\r
-void armv4_tlb_flushD __P((void));\r
-void armv4_tlb_flushD_SE __P((u_int));\r
-\r
-void armv4_drain_writebuf __P((void));\r
-#endif\r
-\r
-#if defined(CPU_IXP12X0)\r
-void ixp12x0_drain_readbuf __P((void));\r
-void ixp12x0_context_switch __P((void));\r
-void ixp12x0_setup __P((char *));\r
-#endif\r
-\r
-#if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \\r
- defined(__CPU_XSCALE_PXA2XX) || defined(CPU_XSCALE_IXP425)\r
-void xscale_cpwait __P((void));\r
-\r
-void xscale_cpu_sleep __P((int));\r
-\r
-u_int xscale_control __P((u_int, u_int));\r
-\r
-void xscale_setttb __P((u_int));\r
-\r
-void xscale_tlb_flushID_SE __P((u_int));\r
-\r
-void xscale_cache_flushID __P((void));\r
-void xscale_cache_flushI __P((void));\r
-void xscale_cache_flushD __P((void));\r
-void xscale_cache_flushD_SE __P((u_int));\r
-\r
-void xscale_cache_cleanID __P((void));\r
-void xscale_cache_cleanD __P((void));\r
-void xscale_cache_cleanD_E __P((u_int));\r
-\r
-void xscale_cache_clean_minidata __P((void));\r
-\r
-void xscale_cache_purgeID __P((void));\r
-void xscale_cache_purgeID_E __P((u_int));\r
-void xscale_cache_purgeD __P((void));\r
-void xscale_cache_purgeD_E __P((u_int));\r
-\r
-void xscale_cache_syncI __P((void));\r
-void xscale_cache_cleanID_rng __P((vaddr_t, vsize_t));\r
-void xscale_cache_cleanD_rng __P((vaddr_t, vsize_t));\r
-void xscale_cache_purgeID_rng __P((vaddr_t, vsize_t));\r
-void xscale_cache_purgeD_rng __P((vaddr_t, vsize_t));\r
-void xscale_cache_syncI_rng __P((vaddr_t, vsize_t));\r
-void xscale_cache_flushD_rng __P((vaddr_t, vsize_t));\r
-\r
-void xscale_context_switch __P((void));\r
-\r
-void xscale_setup __P((char *));\r
-#endif /* CPU_XSCALE_80200 || CPU_XSCALE_80321 || __CPU_XSCALE_PXA2XX || CPU_XSCALE_IXP425 */\r
-\r
-#define tlb_flush cpu_tlb_flushID\r
-#define setttb cpu_setttb\r
-#define drain_writebuf cpu_drain_writebuf\r
-\r
-/*\r
- * Macros for manipulating CPU interrupts\r
- */\r
-#ifdef __PROG32\r
-static __inline u_int32_t __set_cpsr_c(u_int bic, u_int eor) __attribute__((__unused__));\r
-\r
-static __inline u_int32_t\r
-__set_cpsr_c(u_int bic, u_int eor)\r
-{\r
- u_int32_t tmp, ret;\r
-\r
- __asm volatile(\r
- "mrs %0, cpsr\n" /* Get the CPSR */\r
- "bic %1, %0, %2\n" /* Clear bits */\r
- "eor %1, %1, %3\n" /* XOR bits */\r
- "msr cpsr_c, %1\n" /* Set the control field of CPSR */\r
- : "=&r" (ret), "=&r" (tmp)\r
- : "r" (bic), "r" (eor) : "memory");\r
-\r
- return ret;\r
-}\r
-\r
-#define disable_interrupts(mask) \\r
- (__set_cpsr_c((mask) & (I32_bit | F32_bit), \\r
- (mask) & (I32_bit | F32_bit)))\r
-\r
-#define enable_interrupts(mask) \\r
- (__set_cpsr_c((mask) & (I32_bit | F32_bit), 0))\r
-\r
-#define restore_interrupts(old_cpsr) \\r
- (__set_cpsr_c((I32_bit | F32_bit), (old_cpsr) & (I32_bit | F32_bit)))\r
-#else /* ! __PROG32 */\r
-#define disable_interrupts(mask) \\r
- (set_r15((mask) & (R15_IRQ_DISABLE | R15_FIQ_DISABLE), \\r
- (mask) & (R15_IRQ_DISABLE | R15_FIQ_DISABLE)))\r
-\r
-#define enable_interrupts(mask) \\r
- (set_r15((mask) & (R15_IRQ_DISABLE | R15_FIQ_DISABLE), 0))\r
-\r
-#define restore_interrupts(old_r15) \\r
- (set_r15((R15_IRQ_DISABLE | R15_FIQ_DISABLE), \\r
- (old_r15) & (R15_IRQ_DISABLE | R15_FIQ_DISABLE)))\r
-#endif /* __PROG32 */\r
-\r
-#ifdef __PROG32\r
-/* Functions to manipulate the CPSR. */\r
-u_int SetCPSR(u_int, u_int);\r
-u_int GetCPSR(void);\r
-#else\r
-/* Functions to manipulate the processor control bits in r15. */\r
-u_int set_r15(u_int, u_int);\r
-u_int get_r15(void);\r
-#endif /* __PROG32 */\r
-\r
-/*\r
- * Functions to manipulate cpu r13\r
- * (in arm/arm32/setstack.S)\r
- */\r
-\r
-void set_stackptr __P((u_int, u_int));\r
-u_int get_stackptr __P((u_int));\r
-\r
-/*\r
- * Miscellany\r
- */\r
-\r
-int get_pc_str_offset __P((void));\r
-\r
-/*\r
- * CPU functions from locore.S\r
- */\r
-\r
-void cpu_reset __P((void)) __attribute__((__noreturn__));\r
-\r
-/*\r
- * Cache info variables.\r
- */\r
-\r
-/* PRIMARY CACHE VARIABLES */\r
-extern int arm_picache_size;\r
-extern int arm_picache_line_size;\r
-extern int arm_picache_ways;\r
-\r
-extern int arm_pdcache_size; /* and unified */\r
-extern int arm_pdcache_line_size;\r
-extern int arm_pdcache_ways;\r
-\r
-extern int arm_pcache_type;\r
-extern int arm_pcache_unified;\r
-\r
-extern int arm_dcache_align;\r
-extern int arm_dcache_align_mask;\r
-\r
-#endif /* _KERNEL */\r
-#endif /* _ARM32_CPUFUNC_H_ */\r
-\r
-/* End of cpufunc.h */\r
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