/// Macro used to display the value of a bit field in a register returned by CPUID.\r
///\r
#define PRINT_BIT_FIELD(Variable, FieldName) \\r
- Print (L"%5a%42a: %x\n", #Variable, #FieldName, ##Variable.Bits.##FieldName);\r
+ Print (L"%5a%42a: %x\n", #Variable, #FieldName, Variable.Bits.FieldName);\r
\r
///\r
/// Macro used to display the value of a register returned by CPUID.\r
{ 0x56 , "TLB" , "Data TLB0: 4 MByte pages, 4-way set associative, 16 entries" },\r
{ 0x57 , "TLB" , "Data TLB0: 4 KByte pages, 4-way associative, 16 entries" },\r
{ 0x59 , "TLB" , "Data TLB0: 4 KByte pages, fully associative, 16 entries" },\r
- { 0x5A , "TLB" , "Data TLB0: 2-MByte or 4 MByte pages, 4-way set associative, 32 entries" },\r
+ { 0x5A , "TLB" , "Data TLB0: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries" },\r
{ 0x5B , "TLB" , "Data TLB: 4 KByte and 4 MByte pages, 64 entries" },\r
{ 0x5C , "TLB" , "Data TLB: 4 KByte and 4 MByte pages,128 entries" },\r
{ 0x5D , "TLB" , "Data TLB: 4 KByte and 4 MByte pages,256 entries" },\r
{ 0x60 , "Cache" , "1st-level data cache: 16 KByte, 8-way set associative, 64 byte line size" },\r
{ 0x61 , "TLB" , "Instruction TLB: 4 KByte pages, fully associative, 48 entries" },\r
- { 0x63 , "TLB" , "Data TLB: 1 GByte pages, 4-way set associative, 4 entries" },\r
+ { 0x63 , "TLB" , "Data TLB: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries and a separate array with 1 GByte pages, 4-way set associative, 4 entries" },\r
+ { 0x64 , "TLB" , "Data TLB: 4 KByte pages, 4-way set associative, 512 entries" },\r
{ 0x66 , "Cache" , "1st-level data cache: 8 KByte, 4-way set associative, 64 byte line size" },\r
{ 0x67 , "Cache" , "1st-level data cache: 16 KByte, 4-way set associative, 64 byte line size" },\r
{ 0x68 , "Cache" , "1st-level data cache: 32 KByte, 4-way set associative, 64 byte line size" },\r
{ 0xC1 , "STLB" , "Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative, 1024 entries" },\r
{ 0xC2 , "DTLB" , "DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries" },\r
{ 0xC3 , "STLB" , "Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative, 1536 entries. Also 1GBbyte pages, 4-way, 16 entries." },\r
+ { 0xC4 , "DTLB" , "DTLB: 2M/4M Byte pages, 4-way associative, 32 entries" },\r
{ 0xCA , "STLB" , "Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries" },\r
{ 0xD0 , "Cache" , "3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size" },\r
{ 0xD1 , "Cache" , "3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size" },\r
UINT32 Edx;\r
CHAR8 Signature[13];\r
\r
- if (CPUID_SIGNATURE > gMaximumBasicFunction) {\r
- return;\r
- }\r
-\r
AsmCpuid (CPUID_SIGNATURE, &Eax, &Ebx, &Ecx, &Edx);\r
\r
Print (L"CPUID_SIGNATURE (Leaf %08x)\n", CPUID_SIGNATURE);\r
CPUID_VERSION_INFO_EBX Ebx;\r
CPUID_VERSION_INFO_ECX Ecx;\r
CPUID_VERSION_INFO_EDX Edx;\r
- UINTN DisplayFamily;\r
- UINTN DisplayModel;\r
+ UINT32 DisplayFamily;\r
+ UINT32 DisplayModel;\r
\r
if (CPUID_VERSION_INFO > gMaximumBasicFunction) {\r
return;\r
Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, Ebx.Uint32, Ecx.Uint32, 0);\r
PRINT_BIT_FIELD (Ebx, FSGSBASE);\r
PRINT_BIT_FIELD (Ebx, IA32_TSC_ADJUST);\r
+ PRINT_BIT_FIELD (Ebx, SGX);\r
PRINT_BIT_FIELD (Ebx, BMI1);\r
PRINT_BIT_FIELD (Ebx, HLE);\r
PRINT_BIT_FIELD (Ebx, AVX2);\r
PRINT_BIT_FIELD (Ebx, EnhancedRepMovsbStosb);\r
PRINT_BIT_FIELD (Ebx, INVPCID);\r
PRINT_BIT_FIELD (Ebx, RTM);\r
- PRINT_BIT_FIELD (Ebx, PQM);\r
+ PRINT_BIT_FIELD (Ebx, RDT_M);\r
PRINT_BIT_FIELD (Ebx, DeprecateFpuCsDs);\r
PRINT_BIT_FIELD (Ebx, MPX);\r
- PRINT_BIT_FIELD (Ebx, PQE);\r
+ PRINT_BIT_FIELD (Ebx, RDT_A);\r
PRINT_BIT_FIELD (Ebx, RDSEED);\r
PRINT_BIT_FIELD (Ebx, ADX);\r
PRINT_BIT_FIELD (Ebx, SMAP);\r
PRINT_BIT_FIELD (Ebx, CLFLUSHOPT);\r
+ PRINT_BIT_FIELD (Ebx, CLWB);\r
PRINT_BIT_FIELD (Ebx, IntelProcessorTrace);\r
+ PRINT_BIT_FIELD (Ebx, SHA);\r
PRINT_BIT_FIELD (Ecx, PREFETCHWT1);\r
+ PRINT_BIT_FIELD (Ecx, UMIP);\r
PRINT_BIT_FIELD (Ecx, PKU);\r
PRINT_BIT_FIELD (Ecx, OSPKE);\r
+ PRINT_BIT_FIELD (Ecx, MAWAU);\r
+ PRINT_BIT_FIELD (Ecx, RDPID);\r
+ PRINT_BIT_FIELD (Ecx, SGX_LC);\r
}\r
- SubLeaf++;\r
- } while (SubLeaf <= Eax);\r
+ }\r
}\r
\r
/**\r
}\r
\r
/**\r
- Display CPUID_PLATFORM_QOS_MONITORING enumeration sub-leaf.\r
+ Display CPUID_INTEL_RDT_MONITORING enumeration sub-leaf.\r
\r
**/\r
VOID\r
-CpuidPlatformQosMonitoringEnumerationSubLeaf (\r
+CpuidIntelRdtMonitoringEnumerationSubLeaf (\r
VOID\r
)\r
{\r
UINT32 Ebx;\r
- CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF_EDX Edx;\r
+ CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF_EDX Edx;\r
\r
- if (CPUID_PLATFORM_QOS_MONITORING > gMaximumBasicFunction) {\r
+ if (CPUID_INTEL_RDT_MONITORING > gMaximumBasicFunction) {\r
return;\r
}\r
\r
AsmCpuidEx (\r
- CPUID_PLATFORM_QOS_MONITORING, CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF,\r
+ CPUID_INTEL_RDT_MONITORING, CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF,\r
NULL, &Ebx, NULL, &Edx.Uint32\r
);\r
- Print (L"CPUID_PLATFORM_QOS_MONITORING (Leaf %08x, Sub-Leaf %08x)\n", CPUID_PLATFORM_QOS_MONITORING, CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF);\r
+ Print (L"CPUID_INTEL_RDT_MONITORING (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_RDT_MONITORING, CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF);\r
Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", 0, Ebx, 0, Edx.Uint32);\r
PRINT_VALUE (Ebx, Maximum_RMID_Range);\r
- PRINT_BIT_FIELD (Edx, L3CacheQosEnforcement);\r
+ PRINT_BIT_FIELD (Edx, L3CacheRDT_M);\r
}\r
\r
/**\r
- Display CPUID_PLATFORM_QOS_MONITORING capability sub-leaf.\r
+ Display CPUID_INTEL_RDT_MONITORING L3 cache capability sub-leaf.\r
\r
**/\r
VOID\r
-CpuidPlatformQosMonitoringCapabilitySubLeaf (\r
+CpuidIntelRdtMonitoringL3CacheCapabilitySubLeaf (\r
VOID\r
)\r
{\r
UINT32 Ebx;\r
UINT32 Ecx;\r
- CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF_EDX Edx;\r
+ CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF_EDX Edx;\r
\r
- if (CPUID_PLATFORM_QOS_MONITORING > gMaximumBasicFunction) {\r
+ if (CPUID_INTEL_RDT_MONITORING > gMaximumBasicFunction) {\r
return;\r
}\r
\r
AsmCpuidEx (\r
- CPUID_PLATFORM_QOS_MONITORING, CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF,\r
+ CPUID_INTEL_RDT_MONITORING, CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF,\r
NULL, &Ebx, &Ecx, &Edx.Uint32\r
);\r
- Print (L"CPUID_PLATFORM_QOS_MONITORING (Leaf %08x, Sub-Leaf %08x)\n", CPUID_PLATFORM_QOS_MONITORING, CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF);\r
+ Print (L"CPUID_INTEL_RDT_MONITORING (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_RDT_MONITORING, CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF);\r
Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", 0, Ebx, Ecx, Edx.Uint32);\r
PRINT_VALUE (Ebx, OccupancyConversionFactor);\r
PRINT_VALUE (Ecx, Maximum_RMID_Range);\r
PRINT_BIT_FIELD (Edx, L3CacheOccupancyMonitoring);\r
+ PRINT_BIT_FIELD (Edx, L3CacheTotalBandwidthMonitoring);\r
+ PRINT_BIT_FIELD (Edx, L3CacheLocalBandwidthMonitoring);\r
}\r
\r
/**\r
- Display CPUID_PLATFORM_QOS_ENFORCEMENT sub-leaf.\r
+ Display CPUID_INTEL_RDT_ALLOCATION L3 cache allocation technology enumeration\r
+ sub-leaf.\r
\r
**/\r
VOID\r
-CpuidPlatformQosEnforcementResidSubLeaf (\r
+CpuidIntelRdtAllocationL3CacheSubLeaf (\r
VOID\r
)\r
{\r
- CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_EAX Eax;\r
+ CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EAX Eax;\r
UINT32 Ebx;\r
- CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_ECX Ecx;\r
- CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_EDX Edx;\r
+ CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_ECX Ecx;\r
+ CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EDX Edx;\r
\r
AsmCpuidEx (\r
- CPUID_PLATFORM_QOS_ENFORCEMENT, CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF,\r
+ CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF,\r
&Eax.Uint32, &Ebx, &Ecx.Uint32, &Edx.Uint32\r
);\r
- Print (L"CPUID_PLATFORM_QOS_ENFORCEMENT (Leaf %08x, Sub-Leaf %08x)\n", CPUID_PLATFORM_QOS_ENFORCEMENT, CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF);\r
+ Print (L"CPUID_INTEL_RDT_ALLOCATION (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF);\r
Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx, Ecx.Uint32, Edx.Uint32);\r
PRINT_BIT_FIELD (Eax, CapacityLength);\r
PRINT_VALUE (Ebx, AllocationUnitBitMap);\r
}\r
\r
/**\r
- Display CPUID_PLATFORM_QOS_ENFORCEMENT main leaf and sub-leaf.\r
+ Display CPUID_INTEL_RDT_ALLOCATION L2 cache allocation technology enumeration\r
+ sub-leaf.\r
+\r
+**/\r
+VOID\r
+CpuidIntelRdtAllocationL2CacheSubLeaf (\r
+ VOID\r
+ )\r
+{\r
+ CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EAX Eax;\r
+ UINT32 Ebx;\r
+ CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EDX Edx;\r
+\r
+ AsmCpuidEx (\r
+ CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF,\r
+ &Eax.Uint32, &Ebx, NULL, &Edx.Uint32\r
+ );\r
+ Print (L"CPUID_INTEL_RDT_ALLOCATION (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF);\r
+ Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx, 0, Edx.Uint32);\r
+ PRINT_BIT_FIELD (Eax, CapacityLength);\r
+ PRINT_VALUE (Ebx, AllocationUnitBitMap);\r
+ PRINT_BIT_FIELD (Edx, HighestCosNumber);\r
+}\r
+\r
+/**\r
+ Display CPUID_INTEL_RDT_ALLOCATION main leaf and sub-leaves.\r
\r
**/\r
VOID\r
-CpuidPlatformQosEnforcementMainLeaf (\r
+CpuidIntelRdtAllocationMainLeaf (\r
VOID\r
)\r
{\r
- CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF_EBX Ebx;\r
+ CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF_EBX Ebx;\r
\r
- if (CPUID_PLATFORM_QOS_ENFORCEMENT > gMaximumBasicFunction) {\r
+ if (CPUID_INTEL_RDT_ALLOCATION > gMaximumBasicFunction) {\r
return;\r
}\r
\r
AsmCpuidEx (\r
- CPUID_PLATFORM_QOS_ENFORCEMENT, CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF,\r
+ CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF,\r
NULL, &Ebx.Uint32, NULL, NULL\r
);\r
- Print (L"CPUID_PLATFORM_QOS_ENFORCEMENT (Leaf %08x, Sub-Leaf %08x)\n", CPUID_PLATFORM_QOS_ENFORCEMENT, CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF);\r
+ Print (L"CPUID_INTEL_RDT_ALLOCATION (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF);\r
Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", 0, Ebx.Uint32, 0, 0);\r
- PRINT_BIT_FIELD (Ebx, L3CacheQosEnforcement);\r
+ PRINT_BIT_FIELD (Ebx, L3CacheAllocation);\r
+ PRINT_BIT_FIELD (Ebx, L2CacheAllocation);\r
+\r
+ CpuidIntelRdtAllocationL3CacheSubLeaf ();\r
+ CpuidIntelRdtAllocationL2CacheSubLeaf ();\r
+}\r
+\r
+/**\r
+ Display Sub-Leaf 0 Enumeration of Intel SGX Capabilities.\r
+\r
+**/\r
+VOID\r
+CpuidEnumerationOfIntelSgxCapabilities0SubLeaf (\r
+ VOID\r
+ )\r
+{\r
+ CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EAX Eax;\r
+ UINT32 Ebx;\r
+ CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EDX Edx;\r
+\r
+ AsmCpuidEx (\r
+ CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF,\r
+ &Eax.Uint32, &Ebx, NULL, &Edx.Uint32\r
+ );\r
+ Print (L"CPUID_INTEL_SGX (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF);\r
+ Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx, 0, Edx.Uint32);\r
+ PRINT_BIT_FIELD (Eax, SGX1);\r
+ PRINT_BIT_FIELD (Eax, SGX2);\r
+ PRINT_BIT_FIELD (Edx, MaxEnclaveSize_Not64);\r
+ PRINT_BIT_FIELD (Edx, MaxEnclaveSize_64);\r
+}\r
+\r
+/**\r
+ Display Sub-Leaf 1 Enumeration of Intel SGX Capabilities.\r
+\r
+**/\r
+VOID\r
+CpuidEnumerationOfIntelSgxCapabilities1SubLeaf (\r
+ VOID\r
+ )\r
+{\r
+ UINT32 Eax;\r
+ UINT32 Ebx;\r
+ UINT32 Ecx;\r
+ UINT32 Edx;\r
+\r
+ AsmCpuidEx (\r
+ CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF,\r
+ &Eax, &Ebx, &Ecx, &Edx\r
+ );\r
+ Print (L"CPUID_INTEL_SGX (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF);\r
+ Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, Ebx, Ecx, Edx);\r
+}\r
+\r
+/**\r
+ Display Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources.\r
+\r
+**/\r
+VOID\r
+CpuidEnumerationOfIntelSgxResourcesSubLeaf (\r
+ VOID\r
+ )\r
+{\r
+ CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EAX Eax;\r
+ CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EBX Ebx;\r
+ CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_ECX Ecx;\r
+ CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EDX Edx;\r
+ UINT32 SubLeaf;\r
+ \r
+ SubLeaf = CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF;\r
+ do {\r
+ AsmCpuidEx (\r
+ CPUID_INTEL_SGX, SubLeaf,\r
+ &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32\r
+ );\r
+ if (Eax.Bits.SubLeafType == 0x1) {\r
+ Print (L"CPUID_INTEL_SGX (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_SGX, SubLeaf);\r
+ Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, Edx.Uint32);\r
+ PRINT_BIT_FIELD (Eax, SubLeafType);\r
+ PRINT_BIT_FIELD (Eax, LowAddressOfEpcSection);\r
+ PRINT_BIT_FIELD (Ebx, HighAddressOfEpcSection);\r
+ PRINT_BIT_FIELD (Ecx, EpcSection);\r
+ PRINT_BIT_FIELD (Ecx, LowSizeOfEpcSection);\r
+ PRINT_BIT_FIELD (Edx, HighSizeOfEpcSection);\r
+ }\r
+ SubLeaf++;\r
+ } while (Eax.Bits.SubLeafType == 0x1);\r
+}\r
\r
- CpuidPlatformQosEnforcementResidSubLeaf ();\r
+/**\r
+ Display Intel SGX Resource Enumeration.\r
+\r
+**/\r
+VOID\r
+CpuidEnumerationOfIntelSgx (\r
+ VOID\r
+ )\r
+{\r
+ CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX Ebx;\r
+\r
+ if (CPUID_INTEL_SGX > gMaximumBasicFunction) {\r
+ return;\r
+ }\r
+\r
+ AsmCpuidEx (\r
+ CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS,\r
+ CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO,\r
+ NULL, &Ebx.Uint32, NULL, NULL\r
+ );\r
+ if (Ebx.Bits.SGX != 1) {\r
+ //\r
+ // Only if CPUID.(EAX=07H, ECX=0H):EBX.SGX = 1, the processor has support\r
+ // for Intel SGX.\r
+ //\r
+ return;\r
+ }\r
+ \r
+ CpuidEnumerationOfIntelSgxCapabilities0SubLeaf ();\r
+ CpuidEnumerationOfIntelSgxCapabilities1SubLeaf ();\r
+ CpuidEnumerationOfIntelSgxResourcesSubLeaf ();\r
}\r
\r
/**\r
PRINT_BIT_FIELD (Ebx, ConfigurablePsb);\r
PRINT_BIT_FIELD (Ebx, IpTraceStopFiltering);\r
PRINT_BIT_FIELD (Ebx, Mtc);\r
+ PRINT_BIT_FIELD (Ebx, PTWrite);\r
+ PRINT_BIT_FIELD (Ebx, PowerEventTrace);\r
PRINT_BIT_FIELD (Ecx, RTIT);\r
PRINT_BIT_FIELD (Ecx, ToPA);\r
PRINT_BIT_FIELD (Ecx, SingleRangeOutput);\r
{\r
UINT32 Eax;\r
UINT32 Ebx;\r
+ UINT32 Ecx;\r
\r
if (CPUID_TIME_STAMP_COUNTER > gMaximumBasicFunction) {\r
return;\r
}\r
\r
- AsmCpuid (CPUID_TIME_STAMP_COUNTER, &Eax, &Ebx, NULL, NULL);\r
+ AsmCpuid (CPUID_TIME_STAMP_COUNTER, &Eax, &Ebx, &Ecx, NULL);\r
Print (L"CPUID_TIME_STAMP_COUNTER (Leaf %08x)\n", CPUID_TIME_STAMP_COUNTER);\r
- Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, Ebx, 0, 0);\r
+ Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, Ebx, Ecx, 0);\r
}\r
\r
/**\r
CpuidArchitecturalPerformanceMonitoring ();\r
CpuidExtendedTopology ();\r
CpuidExtendedStateMainLeaf ();\r
- CpuidPlatformQosMonitoringEnumerationSubLeaf ();\r
- CpuidPlatformQosMonitoringCapabilitySubLeaf ();\r
- CpuidPlatformQosEnforcementMainLeaf ();\r
+ CpuidIntelRdtMonitoringEnumerationSubLeaf ();\r
+ CpuidIntelRdtMonitoringL3CacheCapabilitySubLeaf ();\r
+ CpuidIntelRdtAllocationMainLeaf ();\r
+ CpuidEnumerationOfIntelSgx ();\r
CpuidIntelProcessorTraceMainLeaf ();\r
CpuidTimeStampCounter ();\r
CpuidProcessorFrequency ();\r
projects / mirror_edk2.git / blobdiff