UEFI Application to display CPUID leaf information.\r
\r
Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>\r
- This program and the accompanying materials\r
- are licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+ SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
#include <Uefi.h>\r
#include <Library/BaseLib.h>\r
#include <Library/UefiLib.h>\r
-#include <Register/Cpuid.h>\r
+#include <Register/Intel/Cpuid.h>\r
\r
///\r
/// Macro used to display the value of a bit field in a register returned by CPUID.\r
/// Structure for cache description lookup table\r
///\r
typedef struct {\r
- UINT8 CacheDescriptor;\r
- CHAR8 *Type;\r
- CHAR8 *Description;\r
+ UINT8 CacheDescriptor;\r
+ CHAR8 *Type;\r
+ CHAR8 *Description;\r
} CPUID_CACHE_INFO_DESCRIPTION;\r
\r
///\r
/// Cache description lookup table\r
///\r
CPUID_CACHE_INFO_DESCRIPTION mCpuidCacheInfoDescription[] = {\r
- { 0x00 , "General" , "Null descriptor, this byte contains no information" },\r
- { 0x01 , "TLB" , "Instruction TLB: 4 KByte pages, 4-way set associative, 32 entries" },\r
- { 0x02 , "TLB" , "Instruction TLB: 4 MByte pages, fully associative, 2 entries" },\r
- { 0x03 , "TLB" , "Data TLB: 4 KByte pages, 4-way set associative, 64 entries" },\r
- { 0x04 , "TLB" , "Data TLB: 4 MByte pages, 4-way set associative, 8 entries" },\r
- { 0x05 , "TLB" , "Data TLB1: 4 MByte pages, 4-way set associative, 32 entries" },\r
- { 0x06 , "Cache" , "1st-level instruction cache: 8 KBytes, 4-way set associative, 32 byte line size" },\r
- { 0x08 , "Cache" , "1st-level instruction cache: 16 KBytes, 4-way set associative, 32 byte line size" },\r
- { 0x09 , "Cache" , "1st-level instruction cache: 32KBytes, 4-way set associative, 64 byte line size" },\r
- { 0x0A , "Cache" , "1st-level data cache: 8 KBytes, 2-way set associative, 32 byte line size" },\r
- { 0x0B , "TLB" , "Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries" },\r
- { 0x0C , "Cache" , "1st-level data cache: 16 KBytes, 4-way set associative, 32 byte line size" },\r
- { 0x0D , "Cache" , "1st-level data cache: 16 KBytes, 4-way set associative, 64 byte line size" },\r
- { 0x0E , "Cache" , "1st-level data cache: 24 KBytes, 6-way set associative, 64 byte line size" },\r
- { 0x1D , "Cache" , "2nd-level cache: 128 KBytes, 2-way set associative, 64 byte line size" },\r
- { 0x21 , "Cache" , "2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size" },\r
- { 0x22 , "Cache" , "3rd-level cache: 512 KBytes, 4-way set associative, 64 byte line size, 2 lines per sector" },\r
- { 0x23 , "Cache" , "3rd-level cache: 1 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector" },\r
- { 0x24 , "Cache" , "2nd-level cache: 1 MBytes, 16-way set associative, 64 byte line size" },\r
- { 0x25 , "Cache" , "3rd-level cache: 2 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector" },\r
- { 0x29 , "Cache" , "3rd-level cache: 4 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector" },\r
- { 0x2C , "Cache" , "1st-level data cache: 32 KBytes, 8-way set associative, 64 byte line size" },\r
- { 0x30 , "Cache" , "1st-level instruction cache: 32 KBytes, 8-way set associative, 64 byte line size" },\r
- { 0x40 , "Cache" , "No 2nd-level cache or, if processor contains a valid 2nd-level cache, no 3rd-level cache" },\r
- { 0x41 , "Cache" , "2nd-level cache: 128 KBytes, 4-way set associative, 32 byte line size" },\r
- { 0x42 , "Cache" , "2nd-level cache: 256 KBytes, 4-way set associative, 32 byte line size" },\r
- { 0x43 , "Cache" , "2nd-level cache: 512 KBytes, 4-way set associative, 32 byte line size" },\r
- { 0x44 , "Cache" , "2nd-level cache: 1 MByte, 4-way set associative, 32 byte line size" },\r
- { 0x45 , "Cache" , "2nd-level cache: 2 MByte, 4-way set associative, 32 byte line size" },\r
- { 0x46 , "Cache" , "3rd-level cache: 4 MByte, 4-way set associative, 64 byte line size" },\r
- { 0x47 , "Cache" , "3rd-level cache: 8 MByte, 8-way set associative, 64 byte line size" },\r
- { 0x48 , "Cache" , "2nd-level cache: 3MByte, 12-way set associative, 64 byte line size" },\r
- { 0x49 , "Cache" , "3rd-level cache: 4MB, 16-way set associative, 64-byte line size (Intel Xeon processor MP, Family 0FH, Model 06H). 2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size" },\r
- { 0x4A , "Cache" , "3rd-level cache: 6MByte, 12-way set associative, 64 byte line size" },\r
- { 0x4B , "Cache" , "3rd-level cache: 8MByte, 16-way set associative, 64 byte line size" },\r
- { 0x4C , "Cache" , "3rd-level cache: 12MByte, 12-way set associative, 64 byte line size" },\r
- { 0x4D , "Cache" , "3rd-level cache: 16MByte, 16-way set associative, 64 byte line size" },\r
- { 0x4E , "Cache" , "2nd-level cache: 6MByte, 24-way set associative, 64 byte line size" },\r
- { 0x4F , "TLB" , "Instruction TLB: 4 KByte pages, 32 entries" },\r
- { 0x50 , "TLB" , "Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 64 entries" },\r
- { 0x51 , "TLB" , "Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 128 entries" },\r
- { 0x52 , "TLB" , "Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 256 entries" },\r
- { 0x55 , "TLB" , "Instruction TLB: 2-MByte or 4-MByte pages, fully associative, 7 entries" },\r
- { 0x56 , "TLB" , "Data TLB0: 4 MByte pages, 4-way set associative, 16 entries" },\r
- { 0x57 , "TLB" , "Data TLB0: 4 KByte pages, 4-way associative, 16 entries" },\r
- { 0x59 , "TLB" , "Data TLB0: 4 KByte pages, fully associative, 16 entries" },\r
- { 0x5A , "TLB" , "Data TLB0: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries" },\r
- { 0x5B , "TLB" , "Data TLB: 4 KByte and 4 MByte pages, 64 entries" },\r
- { 0x5C , "TLB" , "Data TLB: 4 KByte and 4 MByte pages,128 entries" },\r
- { 0x5D , "TLB" , "Data TLB: 4 KByte and 4 MByte pages,256 entries" },\r
- { 0x60 , "Cache" , "1st-level data cache: 16 KByte, 8-way set associative, 64 byte line size" },\r
- { 0x61 , "TLB" , "Instruction TLB: 4 KByte pages, fully associative, 48 entries" },\r
- { 0x63 , "TLB" , "Data TLB: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries and a separate array with 1 GByte pages, 4-way set associative, 4 entries" },\r
- { 0x64 , "TLB" , "Data TLB: 4 KByte pages, 4-way set associative, 512 entries" },\r
- { 0x66 , "Cache" , "1st-level data cache: 8 KByte, 4-way set associative, 64 byte line size" },\r
- { 0x67 , "Cache" , "1st-level data cache: 16 KByte, 4-way set associative, 64 byte line size" },\r
- { 0x68 , "Cache" , "1st-level data cache: 32 KByte, 4-way set associative, 64 byte line size" },\r
- { 0x6A , "Cache" , "uTLB: 4 KByte pages, 8-way set associative, 64 entries" },\r
- { 0x6B , "Cache" , "DTLB: 4 KByte pages, 8-way set associative, 256 entries" },\r
- { 0x6C , "Cache" , "DTLB: 2M/4M pages, 8-way set associative, 128 entries" },\r
- { 0x6D , "Cache" , "DTLB: 1 GByte pages, fully associative, 16 entries" },\r
- { 0x70 , "Cache" , "Trace cache: 12 K-uop, 8-way set associative" },\r
- { 0x71 , "Cache" , "Trace cache: 16 K-uop, 8-way set associative" },\r
- { 0x72 , "Cache" , "Trace cache: 32 K-uop, 8-way set associative" },\r
- { 0x76 , "TLB" , "Instruction TLB: 2M/4M pages, fully associative, 8 entries" },\r
- { 0x78 , "Cache" , "2nd-level cache: 1 MByte, 4-way set associative, 64byte line size" },\r
- { 0x79 , "Cache" , "2nd-level cache: 128 KByte, 8-way set associative, 64 byte line size, 2 lines per sector" },\r
- { 0x7A , "Cache" , "2nd-level cache: 256 KByte, 8-way set associative, 64 byte line size, 2 lines per sector" },\r
- { 0x7B , "Cache" , "2nd-level cache: 512 KByte, 8-way set associative, 64 byte line size, 2 lines per sector" },\r
- { 0x7C , "Cache" , "2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size, 2 lines per sector" },\r
- { 0x7D , "Cache" , "2nd-level cache: 2 MByte, 8-way set associative, 64byte line size" },\r
- { 0x7F , "Cache" , "2nd-level cache: 512 KByte, 2-way set associative, 64-byte line size" },\r
- { 0x80 , "Cache" , "2nd-level cache: 512 KByte, 8-way set associative, 64-byte line size" },\r
- { 0x82 , "Cache" , "2nd-level cache: 256 KByte, 8-way set associative, 32 byte line size" },\r
- { 0x83 , "Cache" , "2nd-level cache: 512 KByte, 8-way set associative, 32 byte line size" },\r
- { 0x84 , "Cache" , "2nd-level cache: 1 MByte, 8-way set associative, 32 byte line size" },\r
- { 0x85 , "Cache" , "2nd-level cache: 2 MByte, 8-way set associative, 32 byte line size" },\r
- { 0x86 , "Cache" , "2nd-level cache: 512 KByte, 4-way set associative, 64 byte line size" },\r
- { 0x87 , "Cache" , "2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size" },\r
- { 0xA0 , "DTLB" , "DTLB: 4k pages, fully associative, 32 entries" },\r
- { 0xB0 , "TLB" , "Instruction TLB: 4 KByte pages, 4-way set associative, 128 entries" },\r
- { 0xB1 , "TLB" , "Instruction TLB: 2M pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries" },\r
- { 0xB2 , "TLB" , "Instruction TLB: 4KByte pages, 4-way set associative, 64 entries" },\r
- { 0xB3 , "TLB" , "Data TLB: 4 KByte pages, 4-way set associative, 128 entries" },\r
- { 0xB4 , "TLB" , "Data TLB1: 4 KByte pages, 4-way associative, 256 entries" },\r
- { 0xB5 , "TLB" , "Instruction TLB: 4KByte pages, 8-way set associative, 64 entries" },\r
- { 0xB6 , "TLB" , "Instruction TLB: 4KByte pages, 8-way set associative, 128 entries" },\r
- { 0xBA , "TLB" , "Data TLB1: 4 KByte pages, 4-way associative, 64 entries" },\r
- { 0xC0 , "TLB" , "Data TLB: 4 KByte and 4 MByte pages, 4-way associative, 8 entries" },\r
- { 0xC1 , "STLB" , "Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative, 1024 entries" },\r
- { 0xC2 , "DTLB" , "DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries" },\r
- { 0xC3 , "STLB" , "Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative, 1536 entries. Also 1GBbyte pages, 4-way, 16 entries." },\r
- { 0xC4 , "DTLB" , "DTLB: 2M/4M Byte pages, 4-way associative, 32 entries" },\r
- { 0xCA , "STLB" , "Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries" },\r
- { 0xD0 , "Cache" , "3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size" },\r
- { 0xD1 , "Cache" , "3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size" },\r
- { 0xD2 , "Cache" , "3rd-level cache: 2 MByte, 4-way set associative, 64 byte line size" },\r
- { 0xD6 , "Cache" , "3rd-level cache: 1 MByte, 8-way set associative, 64 byte line size" },\r
- { 0xD7 , "Cache" , "3rd-level cache: 2 MByte, 8-way set associative, 64 byte line size" },\r
- { 0xD8 , "Cache" , "3rd-level cache: 4 MByte, 8-way set associative, 64 byte line size" },\r
- { 0xDC , "Cache" , "3rd-level cache: 1.5 MByte, 12-way set associative, 64 byte line size" },\r
- { 0xDD , "Cache" , "3rd-level cache: 3 MByte, 12-way set associative, 64 byte line size" },\r
- { 0xDE , "Cache" , "3rd-level cache: 6 MByte, 12-way set associative, 64 byte line size" },\r
- { 0xE2 , "Cache" , "3rd-level cache: 2 MByte, 16-way set associative, 64 byte line size" },\r
- { 0xE3 , "Cache" , "3rd-level cache: 4 MByte, 16-way set associative, 64 byte line size" },\r
- { 0xE4 , "Cache" , "3rd-level cache: 8 MByte, 16-way set associative, 64 byte line size" },\r
- { 0xEA , "Cache" , "3rd-level cache: 12MByte, 24-way set associative, 64 byte line size" },\r
- { 0xEB , "Cache" , "3rd-level cache: 18MByte, 24-way set associative, 64 byte line size" },\r
- { 0xEC , "Cache" , "3rd-level cache: 24MByte, 24-way set associative, 64 byte line size" },\r
- { 0xF0 , "Prefetch" , "64-Byte prefetching" },\r
- { 0xF1 , "Prefetch" , "128-Byte prefetching" },\r
- { 0xFE , "General" , "CPUID leaf 2 does not report TLB descriptor information; use CPUID leaf 18H to query TLB and other address translation parameters." },\r
- { 0xFF , "General" , "CPUID leaf 2 does not report cache descriptor information, use CPUID leaf 4 to query cache parameters" }\r
+ { 0x00, "General", "Null descriptor, this byte contains no information" },\r
+ { 0x01, "TLB", "Instruction TLB: 4 KByte pages, 4-way set associative, 32 entries" },\r
+ { 0x02, "TLB", "Instruction TLB: 4 MByte pages, fully associative, 2 entries" },\r
+ { 0x03, "TLB", "Data TLB: 4 KByte pages, 4-way set associative, 64 entries" },\r
+ { 0x04, "TLB", "Data TLB: 4 MByte pages, 4-way set associative, 8 entries" },\r
+ { 0x05, "TLB", "Data TLB1: 4 MByte pages, 4-way set associative, 32 entries" },\r
+ { 0x06, "Cache", "1st-level instruction cache: 8 KBytes, 4-way set associative, 32 byte line size" },\r
+ { 0x08, "Cache", "1st-level instruction cache: 16 KBytes, 4-way set associative, 32 byte line size" },\r
+ { 0x09, "Cache", "1st-level instruction cache: 32KBytes, 4-way set associative, 64 byte line size" },\r
+ { 0x0A, "Cache", "1st-level data cache: 8 KBytes, 2-way set associative, 32 byte line size" },\r
+ { 0x0B, "TLB", "Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries" },\r
+ { 0x0C, "Cache", "1st-level data cache: 16 KBytes, 4-way set associative, 32 byte line size" },\r
+ { 0x0D, "Cache", "1st-level data cache: 16 KBytes, 4-way set associative, 64 byte line size" },\r
+ { 0x0E, "Cache", "1st-level data cache: 24 KBytes, 6-way set associative, 64 byte line size" },\r
+ { 0x1D, "Cache", "2nd-level cache: 128 KBytes, 2-way set associative, 64 byte line size" },\r
+ { 0x21, "Cache", "2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size" },\r
+ { 0x22, "Cache", "3rd-level cache: 512 KBytes, 4-way set associative, 64 byte line size, 2 lines per sector" },\r
+ { 0x23, "Cache", "3rd-level cache: 1 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector" },\r
+ { 0x24, "Cache", "2nd-level cache: 1 MBytes, 16-way set associative, 64 byte line size" },\r
+ { 0x25, "Cache", "3rd-level cache: 2 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector" },\r
+ { 0x29, "Cache", "3rd-level cache: 4 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector" },\r
+ { 0x2C, "Cache", "1st-level data cache: 32 KBytes, 8-way set associative, 64 byte line size" },\r
+ { 0x30, "Cache", "1st-level instruction cache: 32 KBytes, 8-way set associative, 64 byte line size" },\r
+ { 0x40, "Cache", "No 2nd-level cache or, if processor contains a valid 2nd-level cache, no 3rd-level cache" },\r
+ { 0x41, "Cache", "2nd-level cache: 128 KBytes, 4-way set associative, 32 byte line size" },\r
+ { 0x42, "Cache", "2nd-level cache: 256 KBytes, 4-way set associative, 32 byte line size" },\r
+ { 0x43, "Cache", "2nd-level cache: 512 KBytes, 4-way set associative, 32 byte line size" },\r
+ { 0x44, "Cache", "2nd-level cache: 1 MByte, 4-way set associative, 32 byte line size" },\r
+ { 0x45, "Cache", "2nd-level cache: 2 MByte, 4-way set associative, 32 byte line size" },\r
+ { 0x46, "Cache", "3rd-level cache: 4 MByte, 4-way set associative, 64 byte line size" },\r
+ { 0x47, "Cache", "3rd-level cache: 8 MByte, 8-way set associative, 64 byte line size" },\r
+ { 0x48, "Cache", "2nd-level cache: 3MByte, 12-way set associative, 64 byte line size" },\r
+ { 0x49, "Cache", "3rd-level cache: 4MB, 16-way set associative, 64-byte line size (Intel Xeon processor MP, Family 0FH, Model 06H). 2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size" },\r
+ { 0x4A, "Cache", "3rd-level cache: 6MByte, 12-way set associative, 64 byte line size" },\r
+ { 0x4B, "Cache", "3rd-level cache: 8MByte, 16-way set associative, 64 byte line size" },\r
+ { 0x4C, "Cache", "3rd-level cache: 12MByte, 12-way set associative, 64 byte line size" },\r
+ { 0x4D, "Cache", "3rd-level cache: 16MByte, 16-way set associative, 64 byte line size" },\r
+ { 0x4E, "Cache", "2nd-level cache: 6MByte, 24-way set associative, 64 byte line size" },\r
+ { 0x4F, "TLB", "Instruction TLB: 4 KByte pages, 32 entries" },\r
+ { 0x50, "TLB", "Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 64 entries" },\r
+ { 0x51, "TLB", "Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 128 entries" },\r
+ { 0x52, "TLB", "Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 256 entries" },\r
+ { 0x55, "TLB", "Instruction TLB: 2-MByte or 4-MByte pages, fully associative, 7 entries" },\r
+ { 0x56, "TLB", "Data TLB0: 4 MByte pages, 4-way set associative, 16 entries" },\r
+ { 0x57, "TLB", "Data TLB0: 4 KByte pages, 4-way associative, 16 entries" },\r
+ { 0x59, "TLB", "Data TLB0: 4 KByte pages, fully associative, 16 entries" },\r
+ { 0x5A, "TLB", "Data TLB0: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries" },\r
+ { 0x5B, "TLB", "Data TLB: 4 KByte and 4 MByte pages, 64 entries" },\r
+ { 0x5C, "TLB", "Data TLB: 4 KByte and 4 MByte pages,128 entries" },\r
+ { 0x5D, "TLB", "Data TLB: 4 KByte and 4 MByte pages,256 entries" },\r
+ { 0x60, "Cache", "1st-level data cache: 16 KByte, 8-way set associative, 64 byte line size" },\r
+ { 0x61, "TLB", "Instruction TLB: 4 KByte pages, fully associative, 48 entries" },\r
+ { 0x63, "TLB", "Data TLB: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries and a separate array with 1 GByte pages, 4-way set associative, 4 entries" },\r
+ { 0x64, "TLB", "Data TLB: 4 KByte pages, 4-way set associative, 512 entries" },\r
+ { 0x66, "Cache", "1st-level data cache: 8 KByte, 4-way set associative, 64 byte line size" },\r
+ { 0x67, "Cache", "1st-level data cache: 16 KByte, 4-way set associative, 64 byte line size" },\r
+ { 0x68, "Cache", "1st-level data cache: 32 KByte, 4-way set associative, 64 byte line size" },\r
+ { 0x6A, "Cache", "uTLB: 4 KByte pages, 8-way set associative, 64 entries" },\r
+ { 0x6B, "Cache", "DTLB: 4 KByte pages, 8-way set associative, 256 entries" },\r
+ { 0x6C, "Cache", "DTLB: 2M/4M pages, 8-way set associative, 128 entries" },\r
+ { 0x6D, "Cache", "DTLB: 1 GByte pages, fully associative, 16 entries" },\r
+ { 0x70, "Cache", "Trace cache: 12 K-uop, 8-way set associative" },\r
+ { 0x71, "Cache", "Trace cache: 16 K-uop, 8-way set associative" },\r
+ { 0x72, "Cache", "Trace cache: 32 K-uop, 8-way set associative" },\r
+ { 0x76, "TLB", "Instruction TLB: 2M/4M pages, fully associative, 8 entries" },\r
+ { 0x78, "Cache", "2nd-level cache: 1 MByte, 4-way set associative, 64byte line size" },\r
+ { 0x79, "Cache", "2nd-level cache: 128 KByte, 8-way set associative, 64 byte line size, 2 lines per sector" },\r
+ { 0x7A, "Cache", "2nd-level cache: 256 KByte, 8-way set associative, 64 byte line size, 2 lines per sector" },\r
+ { 0x7B, "Cache", "2nd-level cache: 512 KByte, 8-way set associative, 64 byte line size, 2 lines per sector" },\r
+ { 0x7C, "Cache", "2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size, 2 lines per sector" },\r
+ { 0x7D, "Cache", "2nd-level cache: 2 MByte, 8-way set associative, 64byte line size" },\r
+ { 0x7F, "Cache", "2nd-level cache: 512 KByte, 2-way set associative, 64-byte line size" },\r
+ { 0x80, "Cache", "2nd-level cache: 512 KByte, 8-way set associative, 64-byte line size" },\r
+ { 0x82, "Cache", "2nd-level cache: 256 KByte, 8-way set associative, 32 byte line size" },\r
+ { 0x83, "Cache", "2nd-level cache: 512 KByte, 8-way set associative, 32 byte line size" },\r
+ { 0x84, "Cache", "2nd-level cache: 1 MByte, 8-way set associative, 32 byte line size" },\r
+ { 0x85, "Cache", "2nd-level cache: 2 MByte, 8-way set associative, 32 byte line size" },\r
+ { 0x86, "Cache", "2nd-level cache: 512 KByte, 4-way set associative, 64 byte line size" },\r
+ { 0x87, "Cache", "2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size" },\r
+ { 0xA0, "DTLB", "DTLB: 4k pages, fully associative, 32 entries" },\r
+ { 0xB0, "TLB", "Instruction TLB: 4 KByte pages, 4-way set associative, 128 entries" },\r
+ { 0xB1, "TLB", "Instruction TLB: 2M pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries" },\r
+ { 0xB2, "TLB", "Instruction TLB: 4KByte pages, 4-way set associative, 64 entries" },\r
+ { 0xB3, "TLB", "Data TLB: 4 KByte pages, 4-way set associative, 128 entries" },\r
+ { 0xB4, "TLB", "Data TLB1: 4 KByte pages, 4-way associative, 256 entries" },\r
+ { 0xB5, "TLB", "Instruction TLB: 4KByte pages, 8-way set associative, 64 entries" },\r
+ { 0xB6, "TLB", "Instruction TLB: 4KByte pages, 8-way set associative, 128 entries" },\r
+ { 0xBA, "TLB", "Data TLB1: 4 KByte pages, 4-way associative, 64 entries" },\r
+ { 0xC0, "TLB", "Data TLB: 4 KByte and 4 MByte pages, 4-way associative, 8 entries" },\r
+ { 0xC1, "STLB", "Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative, 1024 entries" },\r
+ { 0xC2, "DTLB", "DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries" },\r
+ { 0xC3, "STLB", "Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative, 1536 entries. Also 1GBbyte pages, 4-way, 16 entries." },\r
+ { 0xC4, "DTLB", "DTLB: 2M/4M Byte pages, 4-way associative, 32 entries" },\r
+ { 0xCA, "STLB", "Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries" },\r
+ { 0xD0, "Cache", "3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size" },\r
+ { 0xD1, "Cache", "3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size" },\r
+ { 0xD2, "Cache", "3rd-level cache: 2 MByte, 4-way set associative, 64 byte line size" },\r
+ { 0xD6, "Cache", "3rd-level cache: 1 MByte, 8-way set associative, 64 byte line size" },\r
+ { 0xD7, "Cache", "3rd-level cache: 2 MByte, 8-way set associative, 64 byte line size" },\r
+ { 0xD8, "Cache", "3rd-level cache: 4 MByte, 8-way set associative, 64 byte line size" },\r
+ { 0xDC, "Cache", "3rd-level cache: 1.5 MByte, 12-way set associative, 64 byte line size" },\r
+ { 0xDD, "Cache", "3rd-level cache: 3 MByte, 12-way set associative, 64 byte line size" },\r
+ { 0xDE, "Cache", "3rd-level cache: 6 MByte, 12-way set associative, 64 byte line size" },\r
+ { 0xE2, "Cache", "3rd-level cache: 2 MByte, 16-way set associative, 64 byte line size" },\r
+ { 0xE3, "Cache", "3rd-level cache: 4 MByte, 16-way set associative, 64 byte line size" },\r
+ { 0xE4, "Cache", "3rd-level cache: 8 MByte, 16-way set associative, 64 byte line size" },\r
+ { 0xEA, "Cache", "3rd-level cache: 12MByte, 24-way set associative, 64 byte line size" },\r
+ { 0xEB, "Cache", "3rd-level cache: 18MByte, 24-way set associative, 64 byte line size" },\r
+ { 0xEC, "Cache", "3rd-level cache: 24MByte, 24-way set associative, 64 byte line size" },\r
+ { 0xF0, "Prefetch", "64-Byte prefetching" },\r
+ { 0xF1, "Prefetch", "128-Byte prefetching" },\r
+ { 0xFE, "General", "CPUID leaf 2 does not report TLB descriptor information; use CPUID leaf 18H to query TLB and other address translation parameters." },\r
+ { 0xFF, "General", "CPUID leaf 2 does not report cache descriptor information, use CPUID leaf 4 to query cache parameters" }\r
};\r
\r
///\r
/// The maximum supported CPUID leaf index starting from leaf 0x00000000.\r
///\r
-UINT32 gMaximumBasicFunction = CPUID_SIGNATURE;\r
+UINT32 gMaximumBasicFunction = CPUID_SIGNATURE;\r
\r
///\r
/// The maximum supported CPUID leaf index starting from leaf 0x80000000.\r
VOID\r
)\r
{\r
- UINT32 Eax;\r
- UINT32 Ebx;\r
- UINT32 Ecx;\r
- UINT32 Edx;\r
- CHAR8 Signature[13];\r
+ UINT32 Eax;\r
+ UINT32 Ebx;\r
+ UINT32 Ecx;\r
+ UINT32 Edx;\r
+ CHAR8 Signature[13];\r
\r
AsmCpuid (CPUID_SIGNATURE, &Eax, &Ebx, &Ecx, &Edx);\r
\r
*(UINT32 *)(Signature + 0) = Ebx;\r
*(UINT32 *)(Signature + 4) = Edx;\r
*(UINT32 *)(Signature + 8) = Ecx;\r
- Signature [12] = 0;\r
+ Signature[12] = 0;\r
Print (L" Signature = %a\n", Signature);\r
\r
gMaximumBasicFunction = Eax;\r
}\r
\r
DisplayModel = Eax.Bits.Model;\r
- if (Eax.Bits.FamilyId == 0x06 || Eax.Bits.FamilyId == 0x0f) {\r
+ if ((Eax.Bits.FamilyId == 0x06) || (Eax.Bits.FamilyId == 0x0f)) {\r
DisplayModel |= (Eax.Bits.ExtendedModelId << 4);\r
}\r
\r
if (CacheDescriptor == 0x00) {\r
return NULL;\r
}\r
+\r
NumDescriptors = sizeof (mCpuidCacheInfoDescription)/sizeof (mCpuidCacheInfoDescription[0]);\r
for (Descriptor = 0; Descriptor < NumDescriptors; Descriptor++) {\r
if (CacheDescriptor == mCpuidCacheInfoDescription[Descriptor].CacheDescriptor) {\r
return &mCpuidCacheInfoDescription[Descriptor];\r
}\r
}\r
+\r
return NULL;\r
}\r
\r
for (Index = 1; Index < 4; Index++) {\r
CacheDescription = LookupCacheDescription (Eax.CacheDescriptor[Index]);\r
if (CacheDescription != NULL) {\r
- Print (L" %-8a %a\n",\r
+ Print (\r
+ L" %-8a %a\n",\r
CacheDescription->Type,\r
CacheDescription->Description\r
);\r
}\r
}\r
}\r
+\r
if (Ebx.Bits.NotValid == 0) {\r
//\r
// Process Ebx.CacheDescriptor[0..3]\r
for (Index = 0; Index < 4; Index++) {\r
CacheDescription = LookupCacheDescription (Ebx.CacheDescriptor[Index]);\r
if (CacheDescription != NULL) {\r
- Print (L" %-8a %a\n",\r
+ Print (\r
+ L" %-8a %a\n",\r
CacheDescription->Type,\r
CacheDescription->Description\r
);\r
}\r
}\r
}\r
+\r
if (Ecx.Bits.NotValid == 0) {\r
//\r
// Process Ecx.CacheDescriptor[0..3]\r
for (Index = 0; Index < 4; Index++) {\r
CacheDescription = LookupCacheDescription (Ecx.CacheDescriptor[Index]);\r
if (CacheDescription != NULL) {\r
- Print (L" %-8a %a\n",\r
+ Print (\r
+ L" %-8a %a\n",\r
CacheDescription->Type,\r
CacheDescription->Description\r
);\r
}\r
}\r
}\r
+\r
if (Edx.Bits.NotValid == 0) {\r
//\r
// Process Edx.CacheDescriptor[0..3]\r
for (Index = 0; Index < 4; Index++) {\r
CacheDescription = LookupCacheDescription (Edx.CacheDescriptor[Index]);\r
if (CacheDescription != NULL) {\r
- Print (L" %-8a %a\n",\r
+ Print (\r
+ L" %-8a %a\n",\r
CacheDescription->Type,\r
CacheDescription->Description\r
);\r
CacheLevel = 0;\r
do {\r
AsmCpuidEx (\r
- CPUID_CACHE_PARAMS, CacheLevel,\r
- &Eax.Uint32, &Ebx.Uint32, &Ecx, &Edx.Uint32\r
+ CPUID_CACHE_PARAMS,\r
+ CacheLevel,\r
+ &Eax.Uint32,\r
+ &Ebx.Uint32,\r
+ &Ecx,\r
+ &Edx.Uint32\r
);\r
if (Eax.Bits.CacheType != CPUID_CACHE_PARAMS_CACHE_TYPE_NULL) {\r
Print (L"CPUID_CACHE_PARAMS (Leaf %08x, Sub-Leaf %08x)\n", CPUID_CACHE_PARAMS, CacheLevel);\r
PRINT_BIT_FIELD (Ebx, LineSize);\r
PRINT_BIT_FIELD (Ebx, LinePartitions);\r
PRINT_BIT_FIELD (Ebx, Ways);\r
- PRINT_VALUE (Ecx, NumberOfSets);\r
+ PRINT_VALUE (Ecx, NumberOfSets);\r
PRINT_BIT_FIELD (Edx, Invalidate);\r
PRINT_BIT_FIELD (Edx, CacheInclusiveness);\r
PRINT_BIT_FIELD (Edx, ComplexCacheIndexing);\r
}\r
+\r
CacheLevel++;\r
} while (Eax.Bits.CacheType != CPUID_CACHE_PARAMS_CACHE_TYPE_NULL);\r
}\r
AsmCpuidEx (\r
CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS,\r
CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO,\r
- &Eax, NULL, NULL, NULL\r
+ &Eax,\r
+ NULL,\r
+ NULL,\r
+ NULL\r
);\r
for (SubLeaf = 0; SubLeaf <= Eax; SubLeaf++) {\r
AsmCpuidEx (\r
CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS,\r
SubLeaf,\r
- NULL, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32\r
+ NULL,\r
+ &Ebx.Uint32,\r
+ &Ecx.Uint32,\r
+ &Edx.Uint32\r
);\r
- if (Ebx.Uint32 != 0 || Ecx.Uint32 != 0 || Edx.Uint32 != 0) {\r
+ if ((Ebx.Uint32 != 0) || (Ecx.Uint32 != 0) || (Edx.Uint32 != 0)) {\r
Print (L"CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS (Leaf %08x, Sub-Leaf %08x)\n", CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS, SubLeaf);\r
Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, Ebx.Uint32, Ecx.Uint32, Edx.Uint32);\r
PRINT_BIT_FIELD (Ebx, FSGSBASE);\r
/**\r
Display CPUID_EXTENDED_TOPOLOGY leafs for all supported levels.\r
\r
+ @param[in] LeafFunction Leaf function index for CPUID_EXTENDED_TOPOLOGY.\r
+\r
**/\r
VOID\r
CpuidExtendedTopology (\r
- UINT32 LeafFunction\r
+ UINT32 LeafFunction\r
)\r
{\r
CPUID_EXTENDED_TOPOLOGY_EAX Eax;\r
if (LeafFunction > gMaximumBasicFunction) {\r
return;\r
}\r
+\r
if ((LeafFunction != CPUID_EXTENDED_TOPOLOGY) && (LeafFunction != CPUID_V2_EXTENDED_TOPOLOGY)) {\r
return;\r
}\r
LevelNumber = 0;\r
for (LevelNumber = 0; ; LevelNumber++) {\r
AsmCpuidEx (\r
- LeafFunction, LevelNumber,\r
- &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx\r
+ LeafFunction,\r
+ LevelNumber,\r
+ &Eax.Uint32,\r
+ &Ebx.Uint32,\r
+ &Ecx.Uint32,\r
+ &Edx\r
);\r
if (Ecx.Bits.LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID) {\r
break;\r
}\r
+\r
Print (\r
L"%a (Leaf %08x, Sub-Leaf %08x)\n",\r
LeafFunction == CPUID_EXTENDED_TOPOLOGY ? "CPUID_EXTENDED_TOPOLOGY" : "CPUID_V2_EXTENDED_TOPOLOGY",\r
- LeafFunction, LevelNumber\r
+ LeafFunction,\r
+ LevelNumber\r
);\r
Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, Edx);\r
PRINT_BIT_FIELD (Eax, ApicIdShift);\r
PRINT_BIT_FIELD (Ebx, LogicalProcessors);\r
PRINT_BIT_FIELD (Ecx, LevelNumber);\r
PRINT_BIT_FIELD (Ecx, LevelType);\r
- PRINT_VALUE (Edx, x2APIC_ID);\r
+ PRINT_VALUE (Edx, x2APIC_ID);\r
}\r
}\r
\r
UINT32 Edx;\r
\r
AsmCpuidEx (\r
- CPUID_EXTENDED_STATE, CPUID_EXTENDED_STATE_SUB_LEAF,\r
- &Eax.Uint32, &Ebx, &Ecx.Uint32, &Edx\r
+ CPUID_EXTENDED_STATE,\r
+ CPUID_EXTENDED_STATE_SUB_LEAF,\r
+ &Eax.Uint32,\r
+ &Ebx,\r
+ &Ecx.Uint32,\r
+ &Edx\r
);\r
Print (L"CPUID_EXTENDED_STATE (Leaf %08x, Sub-Leaf %08x)\n", CPUID_EXTENDED_STATE, CPUID_EXTENDED_STATE_SUB_LEAF);\r
Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx, Ecx.Uint32, Edx);\r
PRINT_BIT_FIELD (Eax, XSAVEC);\r
PRINT_BIT_FIELD (Eax, XGETBV);\r
PRINT_BIT_FIELD (Eax, XSAVES);\r
- PRINT_VALUE (Ebx, EnabledSaveStateSize_XCR0_IA32_XSS);\r
+ PRINT_VALUE (Ebx, EnabledSaveStateSize_XCR0_IA32_XSS);\r
PRINT_BIT_FIELD (Ecx, XCR0);\r
PRINT_BIT_FIELD (Ecx, HWPState);\r
PRINT_BIT_FIELD (Ecx, PT);\r
PRINT_BIT_FIELD (Ecx, XCR0_1);\r
- PRINT_VALUE (Edx, IA32_XSS_Supported_32_63);\r
+ PRINT_VALUE (Edx, IA32_XSS_Supported_32_63);\r
}\r
\r
/**\r
\r
for (SubLeaf = CPUID_EXTENDED_STATE_SIZE_OFFSET; SubLeaf < 32; SubLeaf++) {\r
AsmCpuidEx (\r
- CPUID_EXTENDED_STATE, SubLeaf,\r
- &Eax, &Ebx, &Ecx.Uint32, &Edx\r
+ CPUID_EXTENDED_STATE,\r
+ SubLeaf,\r
+ &Eax,\r
+ &Ebx,\r
+ &Ecx.Uint32,\r
+ &Edx\r
);\r
if (Edx != 0) {\r
Print (L"CPUID_EXTENDED_STATE (Leaf %08x, Sub-Leaf %08x)\n", CPUID_EXTENDED_STATE, SubLeaf);\r
Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, Ebx, Ecx.Uint32, Edx);\r
- PRINT_VALUE (Eax, FeatureSaveStateSize);\r
- PRINT_VALUE (Ebx, FeatureSaveStateOffset);\r
+ PRINT_VALUE (Eax, FeatureSaveStateSize);\r
+ PRINT_VALUE (Ebx, FeatureSaveStateOffset);\r
PRINT_BIT_FIELD (Ecx, XSS);\r
PRINT_BIT_FIELD (Ecx, Compacted);\r
}\r
}\r
\r
AsmCpuidEx (\r
- CPUID_EXTENDED_STATE, CPUID_EXTENDED_STATE_MAIN_LEAF,\r
- &Eax.Uint32, &Ebx, &Ecx, &Edx\r
+ CPUID_EXTENDED_STATE,\r
+ CPUID_EXTENDED_STATE_MAIN_LEAF,\r
+ &Eax.Uint32,\r
+ &Ebx,\r
+ &Ecx,\r
+ &Edx\r
);\r
Print (L"CPUID_EXTENDED_STATE (Leaf %08x, Sub-Leaf %08x)\n", CPUID_EXTENDED_STATE, CPUID_EXTENDED_STATE_MAIN_LEAF);\r
Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx, Ecx, Edx);\r
PRINT_BIT_FIELD (Eax, IA32_XSS);\r
PRINT_BIT_FIELD (Eax, PKRU);\r
PRINT_BIT_FIELD (Eax, IA32_XSS_2);\r
- PRINT_VALUE (Ebx, EnabledSaveStateSize);\r
- PRINT_VALUE (Ecx, SupportedSaveStateSize);\r
- PRINT_VALUE (Edx, XCR0_Supported_32_63);\r
+ PRINT_VALUE (Ebx, EnabledSaveStateSize);\r
+ PRINT_VALUE (Ecx, SupportedSaveStateSize);\r
+ PRINT_VALUE (Edx, XCR0_Supported_32_63);\r
\r
CpuidExtendedStateSubLeaf ();\r
CpuidExtendedStateSizeOffset ();\r
VOID\r
)\r
{\r
- UINT32 Ebx;\r
- CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF_EDX Edx;\r
+ UINT32 Ebx;\r
+ CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF_EDX Edx;\r
\r
if (CPUID_INTEL_RDT_MONITORING > gMaximumBasicFunction) {\r
return;\r
}\r
\r
AsmCpuidEx (\r
- CPUID_INTEL_RDT_MONITORING, CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF,\r
- NULL, &Ebx, NULL, &Edx.Uint32\r
+ CPUID_INTEL_RDT_MONITORING,\r
+ CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF,\r
+ NULL,\r
+ &Ebx,\r
+ NULL,\r
+ &Edx.Uint32\r
);\r
Print (L"CPUID_INTEL_RDT_MONITORING (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_RDT_MONITORING, CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF);\r
Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", 0, Ebx, 0, Edx.Uint32);\r
- PRINT_VALUE (Ebx, Maximum_RMID_Range);\r
+ PRINT_VALUE (Ebx, Maximum_RMID_Range);\r
PRINT_BIT_FIELD (Edx, L3CacheRDT_M);\r
}\r
\r
VOID\r
)\r
{\r
- UINT32 Ebx;\r
- UINT32 Ecx;\r
- CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF_EDX Edx;\r
+ UINT32 Ebx;\r
+ UINT32 Ecx;\r
+ CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF_EDX Edx;\r
\r
if (CPUID_INTEL_RDT_MONITORING > gMaximumBasicFunction) {\r
return;\r
}\r
\r
AsmCpuidEx (\r
- CPUID_INTEL_RDT_MONITORING, CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF,\r
- NULL, &Ebx, &Ecx, &Edx.Uint32\r
+ CPUID_INTEL_RDT_MONITORING,\r
+ CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF,\r
+ NULL,\r
+ &Ebx,\r
+ &Ecx,\r
+ &Edx.Uint32\r
);\r
Print (L"CPUID_INTEL_RDT_MONITORING (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_RDT_MONITORING, CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF);\r
Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", 0, Ebx, Ecx, Edx.Uint32);\r
- PRINT_VALUE (Ebx, OccupancyConversionFactor);\r
- PRINT_VALUE (Ecx, Maximum_RMID_Range);\r
+ PRINT_VALUE (Ebx, OccupancyConversionFactor);\r
+ PRINT_VALUE (Ecx, Maximum_RMID_Range);\r
PRINT_BIT_FIELD (Edx, L3CacheOccupancyMonitoring);\r
PRINT_BIT_FIELD (Edx, L3CacheTotalBandwidthMonitoring);\r
PRINT_BIT_FIELD (Edx, L3CacheLocalBandwidthMonitoring);\r
CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_EDX Edx;\r
\r
AsmCpuidEx (\r
- CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF,\r
- &Eax.Uint32, &Ebx, &Ecx.Uint32, &Edx.Uint32\r
+ CPUID_INTEL_RDT_ALLOCATION,\r
+ CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF,\r
+ &Eax.Uint32,\r
+ &Ebx,\r
+ &Ecx.Uint32,\r
+ &Edx.Uint32\r
);\r
Print (L"CPUID_INTEL_RDT_ALLOCATION (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF);\r
Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx, Ecx.Uint32, Edx.Uint32);\r
PRINT_BIT_FIELD (Eax, MaximumMBAThrottling);\r
- PRINT_VALUE (Ebx, AllocationUnitBitMap);\r
+ PRINT_VALUE (Ebx, AllocationUnitBitMap);\r
PRINT_BIT_FIELD (Ecx, Liner);\r
PRINT_BIT_FIELD (Edx, HighestCosNumber);\r
}\r
CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EDX Edx;\r
\r
AsmCpuidEx (\r
- CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF,\r
- &Eax.Uint32, &Ebx, &Ecx.Uint32, &Edx.Uint32\r
+ CPUID_INTEL_RDT_ALLOCATION,\r
+ CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF,\r
+ &Eax.Uint32,\r
+ &Ebx,\r
+ &Ecx.Uint32,\r
+ &Edx.Uint32\r
);\r
Print (L"CPUID_INTEL_RDT_ALLOCATION (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF);\r
Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx, Ecx.Uint32, Edx.Uint32);\r
PRINT_BIT_FIELD (Eax, CapacityLength);\r
- PRINT_VALUE (Ebx, AllocationUnitBitMap);\r
+ PRINT_VALUE (Ebx, AllocationUnitBitMap);\r
PRINT_BIT_FIELD (Ecx, CodeDataPrioritization);\r
PRINT_BIT_FIELD (Edx, HighestCosNumber);\r
}\r
CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EDX Edx;\r
\r
AsmCpuidEx (\r
- CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF,\r
- &Eax.Uint32, &Ebx, NULL, &Edx.Uint32\r
+ CPUID_INTEL_RDT_ALLOCATION,\r
+ CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF,\r
+ &Eax.Uint32,\r
+ &Ebx,\r
+ NULL,\r
+ &Edx.Uint32\r
);\r
Print (L"CPUID_INTEL_RDT_ALLOCATION (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF);\r
Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx, 0, Edx.Uint32);\r
PRINT_BIT_FIELD (Eax, CapacityLength);\r
- PRINT_VALUE (Ebx, AllocationUnitBitMap);\r
+ PRINT_VALUE (Ebx, AllocationUnitBitMap);\r
PRINT_BIT_FIELD (Edx, HighestCosNumber);\r
}\r
\r
}\r
\r
AsmCpuidEx (\r
- CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF,\r
- NULL, &Ebx.Uint32, NULL, NULL\r
+ CPUID_INTEL_RDT_ALLOCATION,\r
+ CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF,\r
+ NULL,\r
+ &Ebx.Uint32,\r
+ NULL,\r
+ NULL\r
);\r
Print (L"CPUID_INTEL_RDT_ALLOCATION (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF);\r
Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", 0, Ebx.Uint32, 0, 0);\r
CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EDX Edx;\r
\r
AsmCpuidEx (\r
- CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF,\r
- &Eax.Uint32, &Ebx, NULL, &Edx.Uint32\r
+ CPUID_INTEL_SGX,\r
+ CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF,\r
+ &Eax.Uint32,\r
+ &Ebx,\r
+ NULL,\r
+ &Edx.Uint32\r
);\r
Print (L"CPUID_INTEL_SGX (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF);\r
Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx, 0, Edx.Uint32);\r
VOID\r
)\r
{\r
- UINT32 Eax;\r
- UINT32 Ebx;\r
- UINT32 Ecx;\r
- UINT32 Edx;\r
+ UINT32 Eax;\r
+ UINT32 Ebx;\r
+ UINT32 Ecx;\r
+ UINT32 Edx;\r
\r
AsmCpuidEx (\r
- CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF,\r
- &Eax, &Ebx, &Ecx, &Edx\r
+ CPUID_INTEL_SGX,\r
+ CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF,\r
+ &Eax,\r
+ &Ebx,\r
+ &Ecx,\r
+ &Edx\r
);\r
Print (L"CPUID_INTEL_SGX (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF);\r
Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, Ebx, Ecx, Edx);\r
SubLeaf = CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF;\r
do {\r
AsmCpuidEx (\r
- CPUID_INTEL_SGX, SubLeaf,\r
- &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32\r
+ CPUID_INTEL_SGX,\r
+ SubLeaf,\r
+ &Eax.Uint32,\r
+ &Ebx.Uint32,\r
+ &Ecx.Uint32,\r
+ &Edx.Uint32\r
);\r
if (Eax.Bits.SubLeafType == 0x1) {\r
Print (L"CPUID_INTEL_SGX (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_SGX, SubLeaf);\r
PRINT_BIT_FIELD (Ecx, LowSizeOfEpcSection);\r
PRINT_BIT_FIELD (Edx, HighSizeOfEpcSection);\r
}\r
+\r
SubLeaf++;\r
} while (Eax.Bits.SubLeafType == 0x1);\r
}\r
AsmCpuidEx (\r
CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS,\r
CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO,\r
- NULL, &Ebx.Uint32, NULL, NULL\r
+ NULL,\r
+ &Ebx.Uint32,\r
+ NULL,\r
+ NULL\r
);\r
if (Ebx.Bits.SGX != 1) {\r
//\r
\r
for (SubLeaf = CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF; SubLeaf <= MaximumSubLeaf; SubLeaf++) {\r
AsmCpuidEx (\r
- CPUID_INTEL_PROCESSOR_TRACE, SubLeaf,\r
- &Eax.Uint32, &Ebx.Uint32, NULL, NULL\r
+ CPUID_INTEL_PROCESSOR_TRACE,\r
+ SubLeaf,\r
+ &Eax.Uint32,\r
+ &Ebx.Uint32,\r
+ NULL,\r
+ NULL\r
);\r
Print (L"CPUID_INTEL_PROCESSOR_TRACE (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_PROCESSOR_TRACE, SubLeaf);\r
Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, 0, 0);\r
}\r
\r
AsmCpuidEx (\r
- CPUID_INTEL_PROCESSOR_TRACE, CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF,\r
- &Eax, &Ebx.Uint32, &Ecx.Uint32, NULL\r
+ CPUID_INTEL_PROCESSOR_TRACE,\r
+ CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF,\r
+ &Eax,\r
+ &Ebx.Uint32,\r
+ &Ecx.Uint32,\r
+ NULL\r
);\r
Print (L"CPUID_INTEL_PROCESSOR_TRACE (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_PROCESSOR_TRACE, CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF);\r
Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, Ebx.Uint32, Ecx.Uint32, 0);\r
- PRINT_VALUE (Eax, MaximumSubLeaf);\r
+ PRINT_VALUE (Eax, MaximumSubLeaf);\r
PRINT_BIT_FIELD (Ebx, Cr3Filter);\r
PRINT_BIT_FIELD (Ebx, ConfigurablePsb);\r
PRINT_BIT_FIELD (Ebx, IpTraceStopFiltering);\r
// 4 32-bit brand string values per leaf and an extra value to\r
// null terminate the string.\r
//\r
- UINT32 BrandString[3 * 4 + 1];\r
+ UINT32 BrandString[3 * 4 + 1];\r
\r
AsmCpuidEx (\r
- CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING1,\r
- &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32\r
+ CPUID_SOC_VENDOR,\r
+ CPUID_SOC_VENDOR_BRAND_STRING1,\r
+ &Eax.Uint32,\r
+ &Ebx.Uint32,\r
+ &Ecx.Uint32,\r
+ &Edx.Uint32\r
);\r
Print (L"CPUID_SOC_VENDOR (Leaf %08x, Sub-Leaf %08x)\n", CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING1);\r
Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, Edx.Uint32);\r
BrandString[3] = Edx.Uint32;\r
\r
AsmCpuidEx (\r
- CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING2,\r
- &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32\r
+ CPUID_SOC_VENDOR,\r
+ CPUID_SOC_VENDOR_BRAND_STRING2,\r
+ &Eax.Uint32,\r
+ &Ebx.Uint32,\r
+ &Ecx.Uint32,\r
+ &Edx.Uint32\r
);\r
Print (L"CPUID_SOC_VENDOR (Leaf %08x, Sub-Leaf %08x)\n", CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING2);\r
Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, Edx.Uint32);\r
BrandString[7] = Edx.Uint32;\r
\r
AsmCpuidEx (\r
- CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING3,\r
- &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32\r
+ CPUID_SOC_VENDOR,\r
+ CPUID_SOC_VENDOR_BRAND_STRING3,\r
+ &Eax.Uint32,\r
+ &Ebx.Uint32,\r
+ &Ecx.Uint32,\r
+ &Edx.Uint32\r
);\r
Print (L"CPUID_SOC_VENDOR (Leaf %08x, Sub-Leaf %08x)\n", CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING3);\r
Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, Edx.Uint32);\r
}\r
\r
AsmCpuidEx (\r
- CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_MAIN_LEAF,\r
- &Eax, &Ebx.Uint32, &Ecx, &Edx\r
+ CPUID_SOC_VENDOR,\r
+ CPUID_SOC_VENDOR_MAIN_LEAF,\r
+ &Eax,\r
+ &Ebx.Uint32,\r
+ &Ecx,\r
+ &Edx\r
);\r
Print (L"CPUID_SOC_VENDOR (Leaf %08x, Sub-Leaf %08x)\n", CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_MAIN_LEAF);\r
Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, Ebx.Uint32, Ecx, Edx);\r
Print (L" Not Supported\n");\r
return;\r
}\r
- PRINT_VALUE (Eax, MaxSOCID_Index);\r
+\r
+ PRINT_VALUE (Eax, MaxSOCID_Index);\r
PRINT_BIT_FIELD (Ebx, SocVendorId);\r
PRINT_BIT_FIELD (Ebx, IsVendorScheme);\r
- PRINT_VALUE (Ecx, ProjectID);\r
- PRINT_VALUE (Edx, SteppingID);\r
+ PRINT_VALUE (Ecx, ProjectID);\r
+ PRINT_VALUE (Edx, SteppingID);\r
CpuidSocVendorBrandString ();\r
}\r
\r
AsmCpuidEx (\r
CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS,\r
CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_MAIN_LEAF,\r
- &Eax, &Ebx.Uint32, &Ecx, &Edx.Uint32\r
+ &Eax,\r
+ &Ebx.Uint32,\r
+ &Ecx,\r
+ &Edx.Uint32\r
);\r
Print (L"CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS (Leaf %08x, Sub-Leaf %08x)\n", CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS, CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_MAIN_LEAF);\r
Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, Ebx.Uint32, Ecx, Edx.Uint32);\r
\r
- PRINT_VALUE (Eax, MaxID_Index);\r
+ PRINT_VALUE (Eax, MaxID_Index);\r
PRINT_BIT_FIELD (Ebx, Page4K);\r
PRINT_BIT_FIELD (Ebx, Page2M);\r
PRINT_BIT_FIELD (Ebx, Page4M);\r
PRINT_BIT_FIELD (Ebx, Partitioning);\r
PRINT_BIT_FIELD (Ebx, Way);\r
\r
- PRINT_VALUE (Ecx, NumberOfSets);\r
+ PRINT_VALUE (Ecx, NumberOfSets);\r
\r
PRINT_BIT_FIELD (Edx, TranslationCacheType);\r
PRINT_BIT_FIELD (Edx, TranslationCacheLevel);\r
AsmCpuid (CPUID_EXTENDED_FUNCTION, &Eax, NULL, NULL, NULL);\r
Print (L"CPUID_EXTENDED_FUNCTION (Leaf %08x)\n", CPUID_EXTENDED_FUNCTION);\r
Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, 0, 0, 0);\r
- PRINT_VALUE (Eax, MaximumExtendedFunction);\r
+ PRINT_VALUE (Eax, MaximumExtendedFunction);\r
\r
gMaximumExtendedFunction = Eax;\r
}\r
// 4 32-bit brand string values per leaf and an extra value to\r
// null terminate the string.\r
//\r
- UINT32 BrandString[3 * 4 + 1];\r
+ UINT32 BrandString[3 * 4 + 1];\r
\r
if (CPUID_BRAND_STRING1 <= gMaximumExtendedFunction) {\r
AsmCpuid (CPUID_BRAND_STRING1, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);\r
CpuidVersionInfo ();\r
CpuidCacheInfo ();\r
CpuidSerialNumber ();\r
- CpuidCacheParams();\r
+ CpuidCacheParams ();\r
CpuidMonitorMwait ();\r
CpuidThermalPowerManagement ();\r
CpuidStructuredExtendedFeatureFlags ();\r
- CpuidDirectCacheAccessInfo();\r
+ CpuidDirectCacheAccessInfo ();\r
CpuidArchitecturalPerformanceMonitoring ();\r
CpuidExtendedTopology (CPUID_EXTENDED_TOPOLOGY);\r
CpuidExtendedStateMainLeaf ();\r
projects / mirror_edk2.git / blobdiff