UefiCpuPkg/CpuDxe: Enable protection for newly added page table

[mirror_edk2.git] / UefiCpuPkg / CpuDxe / CpuDxe.c

diff --git a/UefiCpuPkg/CpuDxe/CpuDxe.c b/UefiCpuPkg/CpuDxe/CpuDxe.c
index 86806568a98b660cab2ddc9142f012ac4aac2073..6ae2dcd1c71136bd6fa364ba906dd80a6befcde6 100644 (file)
--- a/UefiCpuPkg/CpuDxe/CpuDxe.c
+++ b/UefiCpuPkg/CpuDxe/CpuDxe.c
@@ -25,63 +25,64 @@
 BOOLEAN                   InterruptState = FALSE;\r
 EFI_HANDLE                mCpuHandle = NULL;\r
 BOOLEAN                   mIsFlushingGCD;\r
-UINT64                    mValidMtrrAddressMask = MTRR_LIB_CACHE_VALID_ADDRESS;\r
-UINT64                    mValidMtrrBitsMask    = MTRR_LIB_MSR_VALID_MASK;\r
+BOOLEAN                   mIsAllocatingPageTable = FALSE;\r
+UINT64                    mValidMtrrAddressMask;\r
+UINT64                    mValidMtrrBitsMask;\r
 UINT64                    mTimerPeriod = 0;\r
 \r
 FIXED_MTRR    mFixedMtrrTable[] = {\r
   {\r
-    MTRR_LIB_IA32_MTRR_FIX64K_00000,\r
+    MSR_IA32_MTRR_FIX64K_00000,\r
     0,\r
     0x10000\r
   },\r
   {\r
-    MTRR_LIB_IA32_MTRR_FIX16K_80000,\r
+    MSR_IA32_MTRR_FIX16K_80000,\r
     0x80000,\r
     0x4000\r
   },\r
   {\r
-    MTRR_LIB_IA32_MTRR_FIX16K_A0000,\r
+    MSR_IA32_MTRR_FIX16K_A0000,\r
     0xA0000,\r
     0x4000\r
   },\r
   {\r
-    MTRR_LIB_IA32_MTRR_FIX4K_C0000,\r
+    MSR_IA32_MTRR_FIX4K_C0000,\r
     0xC0000,\r
     0x1000\r
   },\r
   {\r
-    MTRR_LIB_IA32_MTRR_FIX4K_C8000,\r
+    MSR_IA32_MTRR_FIX4K_C8000,\r
     0xC8000,\r
     0x1000\r
   },\r
   {\r
-    MTRR_LIB_IA32_MTRR_FIX4K_D0000,\r
+    MSR_IA32_MTRR_FIX4K_D0000,\r
     0xD0000,\r
     0x1000\r
   },\r
   {\r
-    MTRR_LIB_IA32_MTRR_FIX4K_D8000,\r
+    MSR_IA32_MTRR_FIX4K_D8000,\r
     0xD8000,\r
     0x1000\r
   },\r
   {\r
-    MTRR_LIB_IA32_MTRR_FIX4K_E0000,\r
+    MSR_IA32_MTRR_FIX4K_E0000,\r
     0xE0000,\r
     0x1000\r
   },\r
   {\r
-    MTRR_LIB_IA32_MTRR_FIX4K_E8000,\r
+    MSR_IA32_MTRR_FIX4K_E8000,\r
     0xE8000,\r
     0x1000\r
   },\r
   {\r
-    MTRR_LIB_IA32_MTRR_FIX4K_F0000,\r
+    MSR_IA32_MTRR_FIX4K_F0000,\r
     0xF0000,\r
     0x1000\r
   },\r
   {\r
-    MTRR_LIB_IA32_MTRR_FIX4K_F8000,\r
+    MSR_IA32_MTRR_FIX4K_F8000,\r
     0xF8000,\r
     0x1000\r
   },\r
@@ -407,6 +408,20 @@ CpuSetMemoryAttributes (
     return EFI_SUCCESS;\r
   }\r
 \r
+  //\r
+  // During memory attributes updating, new pages may be allocated to setup\r
+  // smaller granularity of page table. Page allocation action might then cause\r
+  // another calling of CpuSetMemoryAttributes() recursively, due to memory\r
+  // protection policy configured (such as PcdDxeNxMemoryProtectionPolicy).\r
+  // Since this driver will always protect memory used as page table by itself,\r
+  // there's no need to apply protection policy requested from memory service.\r
+  // So it's safe to just return EFI_SUCCESS if this time of calling is caused\r
+  // by page table memory allocation.\r
+  //\r
+  if (mIsAllocatingPageTable) {\r
+    DEBUG((DEBUG_VERBOSE, "  Allocating page table memory\n"));\r
+    return EFI_SUCCESS;\r
+  }\r
 \r
   CacheAttributes = Attributes & CACHE_ATTRIBUTE_MASK;\r
   MemoryAttributes = Attributes & MEMORY_ATTRIBUTE_MASK;\r
@@ -487,7 +502,7 @@ CpuSetMemoryAttributes (
   //\r
   // Set memory attribute by page table\r
   //\r
-  return AssignMemoryPageAttributes (NULL, BaseAddress, Length, MemoryAttributes, AllocatePages);\r
+  return AssignMemoryPageAttributes (NULL, BaseAddress, Length, MemoryAttributes, NULL);\r
 }\r
 \r
 /**\r
@@ -510,13 +525,12 @@ InitializeMtrrMask (
     AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);\r
 \r
     PhysicalAddressBits = (UINT8) RegEax;\r
-\r
-    mValidMtrrBitsMask    = LShiftU64 (1, PhysicalAddressBits) - 1;\r
-    mValidMtrrAddressMask = mValidMtrrBitsMask & 0xfffffffffffff000ULL;\r
   } else {\r
-    mValidMtrrBitsMask    = MTRR_LIB_MSR_VALID_MASK;\r
-    mValidMtrrAddressMask = MTRR_LIB_CACHE_VALID_ADDRESS;\r
+    PhysicalAddressBits = 36;\r
   }\r
+\r
+  mValidMtrrBitsMask    = LShiftU64 (1, PhysicalAddressBits) - 1;\r
+  mValidMtrrAddressMask = mValidMtrrBitsMask & 0xfffffffffffff000ULL;\r
 }\r
 \r
 /**\r
@@ -684,7 +698,7 @@ SetGcdMemorySpaceAttributes (
 \r
 **/\r
 VOID\r
-RefreshGcdMemoryAttributes (\r
+RefreshMemoryAttributesFromMtrr (\r
   VOID\r
   )\r
 {\r
@@ -705,14 +719,9 @@ RefreshGcdMemoryAttributes (
   UINT32                              FirmwareVariableMtrrCount;\r
   UINT8                               DefaultMemoryType;\r
 \r
-  if (!IsMtrrSupported ()) {\r
-    return;\r
-  }\r
-\r
   FirmwareVariableMtrrCount = GetFirmwareVariableMtrrCount ();\r
   ASSERT (FirmwareVariableMtrrCount <= MTRR_NUMBER_OF_VARIABLE_MTRR);\r
 \r
-  mIsFlushingGCD = TRUE;\r
   MemorySpaceMap = NULL;\r
 \r
   //\r
@@ -863,6 +872,46 @@ RefreshGcdMemoryAttributes (
   if (MemorySpaceMap != NULL) {\r
     FreePool (MemorySpaceMap);\r
   }\r
+}\r
+\r
+/**\r
+ Check if paging is enabled or not.\r
+**/\r
+BOOLEAN\r
+IsPagingAndPageAddressExtensionsEnabled (\r
+  VOID\r
+  )\r
+{\r
+  IA32_CR0  Cr0;\r
+  IA32_CR4  Cr4;\r
+\r
+  Cr0.UintN = AsmReadCr0 ();\r
+  Cr4.UintN = AsmReadCr4 ();\r
+\r
+  return ((Cr0.Bits.PG != 0) && (Cr4.Bits.PAE != 0));\r
+}\r
+\r
+/**\r
+  Refreshes the GCD Memory Space attributes according to MTRRs and Paging.\r
+\r
+  This function refreshes the GCD Memory Space attributes according to MTRRs\r
+  and page tables.\r
+\r
+**/\r
+VOID\r
+RefreshGcdMemoryAttributes (\r
+  VOID\r
+  )\r
+{\r
+  mIsFlushingGCD = TRUE;\r
+\r
+  if (IsMtrrSupported ()) {\r
+    RefreshMemoryAttributesFromMtrr ();\r
+  }\r
+\r
+  if (IsPagingAndPageAddressExtensionsEnabled ()) {\r
+    RefreshGcdMemoryAttributesFromPaging ();\r
+  }\r
 \r
   mIsFlushingGCD = FALSE;\r
 }\r