UefiCpuPkg/ArchitecturalMsr.h: Add RTIT TOPA table entry definition.

[mirror_edk2.git] / UefiCpuPkg / Include / Register / ArchitecturalMsr.h

diff --git a/UefiCpuPkg/Include/Register/ArchitecturalMsr.h b/UefiCpuPkg/Include/Register/ArchitecturalMsr.h
index 4f9c1033f32da803f3ebf5ea5591029d03ef9979..34fdf5be3aec05428b7552c53430c14799d9dfb2 100644 (file)
--- a/UefiCpuPkg/Include/Register/ArchitecturalMsr.h
+++ b/UefiCpuPkg/Include/Register/ArchitecturalMsr.h
@@ -6,7 +6,7 @@
   returned is a single 32-bit or 64-bit value, then a data structure is not\r
   provided for that MSR.\r
 \r
-  Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
+  Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>\r
   This program and the accompanying materials\r
   are licensed and made available under the terms and conditions of the BSD License\r
   which accompanies this distribution.  The full text of the license may be found at\r
@@ -4534,6 +4534,83 @@ typedef union {
   UINT64  Uint64;\r
 } MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER;\r
 \r
+/**\r
+  Format of ToPA table entries.\r
+**/\r
+typedef union {\r
+  ///\r
+  /// Individual bit fields\r
+  ///\r
+  struct {\r
+    ///\r
+    /// [Bit 0] END. See Section 35.2.6.2, "Table of Physical Addresses (ToPA)".\r
+    ///\r
+    UINT32  END:1;\r
+    UINT32  Reserved1:1;\r
+    ///\r
+    /// [Bit 2] INT. See Section 35.2.6.2, "Table of Physical Addresses (ToPA)".\r
+    ///\r
+    UINT32  INT:1;\r
+    UINT32  Reserved2:1;\r
+    ///\r
+    /// [Bit 4] STOP. See Section 35.2.6.2, "Table of Physical Addresses (ToPA)".\r
+    ///\r
+    UINT32  STOP:1;\r
+    UINT32  Reserved3:1;\r
+    ///\r
+    /// [Bit 6:9] Indicates the size of the associated output region. See Section\r
+    /// 35.2.6.2, "Table of Physical Addresses (ToPA)".\r
+    ///\r
+    UINT32  Size:4;\r
+    UINT32  Reserved4:2;\r
+    ///\r
+    /// [Bit 12:31] Output Region Base Physical Address low part.\r
+    /// [Bit 12:31] Output Region Base Physical Address [12:63] value to match.\r
+    /// ATTENTION: The size of the address field is determined by the processor's\r
+    /// physical-address width (MAXPHYADDR) in bits, as reported in\r
+    /// CPUID.80000008H:EAX[7:0]. the above part of address reserved.\r
+    /// True address field is [12:MAXPHYADDR-1], [MAXPHYADDR:63] is reserved part.\r
+    /// Detail see Section 35.2.6.2, "Table of Physical Addresses (ToPA)".\r
+    ///\r
+    UINT32  Base:20;\r
+    ///\r
+    /// [Bit 32:63] Output Region Base Physical Address high part.\r
+    /// [Bit 32:63] Output Region Base Physical Address [12:63] value to match.\r
+    /// ATTENTION: The size of the address field is determined by the processor's\r
+    /// physical-address width (MAXPHYADDR) in bits, as reported in\r
+    /// CPUID.80000008H:EAX[7:0]. the above part of address reserved.\r
+    /// True address field is [12:MAXPHYADDR-1], [MAXPHYADDR:63] is reserved part.\r
+    /// Detail see Section 35.2.6.2, "Table of Physical Addresses (ToPA)".\r
+    ///\r
+    UINT32  BaseHi:32;\r
+  } Bits;\r
+  ///\r
+  /// All bit fields as a 64-bit value\r
+  ///\r
+  UINT64  Uint64;\r
+} RTIT_TOPA_TABLE_ENTRY;\r
+\r
+///\r
+/// The size of the associated output region usd by Topa.\r
+///\r
+typedef enum {\r
+  RtitTopaMemorySize4K = 0,\r
+  RtitTopaMemorySize8K,\r
+  RtitTopaMemorySize16K,\r
+  RtitTopaMemorySize32K,\r
+  RtitTopaMemorySize64K,\r
+  RtitTopaMemorySize128K,\r
+  RtitTopaMemorySize256K,\r
+  RtitTopaMemorySize512K,\r
+  RtitTopaMemorySize1M,\r
+  RtitTopaMemorySize2M,\r
+  RtitTopaMemorySize4M,\r
+  RtitTopaMemorySize8M,\r
+  RtitTopaMemorySize16M,\r
+  RtitTopaMemorySize32M,\r
+  RtitTopaMemorySize64M,\r
+  RtitTopaMemorySize128M\r
+} RTIT_TOPA_MEMORY_SIZE;\r
 \r
 /**\r
   Trace Control Register (R/W). If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1).\r