\r
@par Specification Reference:\r
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 2A,\r
- December 2015, CPUID instruction.\r
+ September 2016, CPUID instruction.\r
\r
**/\r
\r
///\r
UINT32 PGE:1;\r
///\r
- /// [Bit 14] Machine Check Architecture. The Machine Check Architecture,\r
- /// which provides a compatible mechanism for error reporting in P6 family,\r
- /// Pentium 4, Intel Xeon processors, and future processors, is supported.\r
- /// The MCG_CAP MSR contains feature bits describing how many banks of error\r
- /// reporting MSRs are supported.\r
+ /// [Bit 14] Machine Check Architecture. A value of 1 indicates the Machine\r
+ /// Check Architecture of reporting machine errors is supported. The MCG_CAP\r
+ /// MSR contains feature bits describing how many banks of error reporting\r
+ /// MSRs are supported.\r
///\r
UINT32 MCA:1;\r
///\r
<tr><td> 0x56 </td><td> TLB </td><td> Data TLB0: 4 MByte pages, 4-way set associative, 16 entries</td></tr>\r
<tr><td> 0x57 </td><td> TLB </td><td> Data TLB0: 4 KByte pages, 4-way associative, 16 entries</td></tr>\r
<tr><td> 0x59 </td><td> TLB </td><td> Data TLB0: 4 KByte pages, fully associative, 16 entries</td></tr>\r
- <tr><td> 0x5A </td><td> TLB </td><td> Data TLB0: 2-MByte or 4 MByte pages, 4-way set associative, 32 entries</td></tr>\r
+ <tr><td> 0x5A </td><td> TLB </td><td> Data TLB0: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries</td></tr>\r
<tr><td> 0x5B </td><td> TLB </td><td> Data TLB: 4 KByte and 4 MByte pages, 64 entries</td></tr>\r
<tr><td> 0x5C </td><td> TLB </td><td> Data TLB: 4 KByte and 4 MByte pages,128 entries</td></tr>\r
<tr><td> 0x5D </td><td> TLB </td><td> Data TLB: 4 KByte and 4 MByte pages,256 entries</td></tr>\r
<tr><td> 0x60 </td><td> Cache </td><td> 1st-level data cache: 16 KByte, 8-way set associative, 64 byte line size</td></tr>\r
<tr><td> 0x61 </td><td> TLB </td><td> Instruction TLB: 4 KByte pages, fully associative, 48 entries</td></tr>\r
- <tr><td> 0x63 </td><td> TLB </td><td> Data TLB: 1 GByte pages, 4-way set associative, 4 entries</td></tr>\r
+ <tr><td> 0x63 </td><td> TLB </td><td> Data TLB: 2 MByte or 4 MByte pages, 4-way set associative,\r
+ 32 entries and a separate array with 1 GByte pages, 4-way set associative,\r
+ 4 entries</td></tr>\r
+ <tr><td> 0x64 </td><td> TLB </td><td> Data TLB: 4 KByte pages, 4-way set associative, 512 entries</td></tr>\r
<tr><td> 0x66 </td><td> Cache </td><td> 1st-level data cache: 8 KByte, 4-way set associative, 64 byte line size</td></tr>\r
<tr><td> 0x67 </td><td> Cache </td><td> 1st-level data cache: 16 KByte, 4-way set associative, 64 byte line size</td></tr>\r
<tr><td> 0x68 </td><td> Cache </td><td> 1st-level data cache: 32 KByte, 4-way set associative, 64 byte line size</td></tr>\r
<tr><td> 0xC2 </td><td> DTLB </td><td> DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries</td></tr>\r
<tr><td> 0xC3 </td><td> STLB </td><td> Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative,\r
1536 entries. Also 1GBbyte pages, 4-way, 16 entries.</td></tr>\r
+ <tr><td> 0xC4 </td><td> DTLB </td><td> DTLB: 2M/4M Byte pages, 4-way associative, 32 entries</td></tr>\r
<tr><td> 0xCA </td><td> STLB </td><td> Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries</td></tr>\r
<tr><td> 0xD0 </td><td> Cache </td><td> 3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size</td></tr>\r
<tr><td> 0xD1 </td><td> Cache </td><td> 3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size</td></tr>\r
SubLeaf,\r
NULL, &Ebx.Uint32, &Ecx.Uint32, NULL\r
);\r
- SubLeaf++;\r
- } while (SubLeaf <= Eax);\r
+ }\r
@endcode\r
**/\r
#define CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS 0x07\r
/// [Bit 1] IA32_TSC_ADJUST MSR is supported if 1.\r
///\r
UINT32 IA32_TSC_ADJUST:1;\r
- UINT32 Reserved1:1;\r
+ ///\r
+ /// [Bit 2] Intel SGX is supported if 1. See section 37.7 "DISCOVERING SUPPORT\r
+ /// FOR INTEL(R) SGX AND ENABLING ENCLAVE INSTRUCTIONS".\r
+ ///\r
+ UINT32 SGX:1;\r
///\r
/// [Bit 3] If 1 indicates the processor supports the first group of advanced\r
/// bit manipulation extensions (ANDN, BEXTR, BLSI, BLSMSK, BLSR, TZCNT)\r
///\r
UINT32 RTM:1;\r
///\r
- /// [Bit 12] Supports Platform Quality of Service Monitoring (PQM)\r
- /// capability if 1.\r
+ /// [Bit 12] Supports Intel(R) Resource Director Technology (Intel(R) RDT)\r
+ /// Monitoring capability if 1.\r
///\r
- UINT32 PQM:1;\r
+ UINT32 RDT_M:1;\r
///\r
/// [Bit 13] Deprecates FPU CS and FPU DS values if 1.\r
///\r
///\r
UINT32 MPX:1;\r
///\r
- /// [Bit 15] Supports Platform Quality of Service Enforcement (PQE)\r
- /// capability if 1.\r
+ /// [Bit 15] Supports Intel(R) Resource Director Technology (Intel(R) RDT)\r
+ /// Allocation capability if 1.\r
///\r
- UINT32 PQE:1;\r
+ UINT32 RDT_A:1;\r
UINT32 Reserved2:2;\r
///\r
/// [Bit 18] If 1 indicates the processor supports the RDSEED instruction.\r
/// [Bit 23] If 1 indicates the processor supports the CLFLUSHOPT instruction.\r
///\r
UINT32 CLFLUSHOPT:1;\r
- UINT32 Reserved4:1;\r
+ ///\r
+ /// [Bit 24] If 1 indicates the processor supports the CLWB instruction.\r
+ ///\r
+ UINT32 CLWB:1;\r
///\r
/// [Bit 25] If 1 indicates the processor supports the Intel Processor Trace\r
/// extensions.\r
///\r
UINT32 IntelProcessorTrace:1;\r
- UINT32 Reserved5:6;\r
+ UINT32 Reserved4:3;\r
+ ///\r
+ /// [Bit 29] Supports Intel(R) Secure Hash Algorithm Extensions (Intel(R)\r
+ /// SHA Extensions) if 1.\r
+ ///\r
+ UINT32 SHA:1;\r
+ UINT32 Reserved5:2;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
/// [Bit 0] If 1 indicates the processor supports the PREFETCHWT1 instruction.\r
///\r
UINT32 PREFETCHWT1:1;\r
- UINT32 Reserved1:2;\r
+ UINT32 Reserved1:1;\r
+ ///\r
+ /// [Bit 2] Supports user-mode instruction prevention if 1.\r
+ ///\r
+ UINT32 UMIP:1;\r
///\r
/// [Bit 3] Supports protection keys for user-mode pages if 1.\r
///\r
/// RDPKRU/WRPKRU instructions).\r
///\r
UINT32 OSPKE:1;\r
- UINT32 Reserved2:27;\r
+ UINT32 Reserved2:12;\r
+ ///\r
+ /// [Bits 21:17] The value of MAWAU used by the BNDLDX and BNDSTX instructions\r
+ /// in 64-bit mode.\r
+ ///\r
+ UINT32 MAWAU:5;\r
+ ///\r
+ /// [Bit 22] Supports Read Processor ID if 1.\r
+ ///\r
+ UINT32 RDPID:1;\r
+ UINT32 Reserved3:7;\r
+ ///\r
+ /// [Bit 30] Supports SGX Launch Configuration if 1.\r
+ ///\r
+ UINT32 SGX_LC:1;\r
+ UINT32 Reserved4:1;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
enabled.\r
@retval ECX Maximum size (bytes, from the beginning of the XSAVE/XRSTOR save\r
area) of the XSAVE/XRSTOR save area required by all supported\r
- features in the processor, i.e all the valid bit fields in XCR0.\r
+ features in the processor, i.e., all the valid bit fields in XCR0.\r
@retval EDX Reports the supported bits of the upper 32 bits of XCR0.\r
XCR0[n+32] can be set to 1 only if EDX[n] is 1.\r
\r
\r
\r
/**\r
- CPUID Platform QoS Monitoring Information\r
+ CPUID Intel Resource Director Technology (Intel RDT) Monitoring Information\r
\r
- @param EAX CPUID_PLATFORM_QOS_MONITORING (0x0F)\r
- @param ECX CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF (0x00).\r
- CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF (0x01).\r
+ @param EAX CPUID_INTEL_RDT_MONITORING (0x0F)\r
+ @param ECX CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF (0x00).\r
+ CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF (0x01).\r
\r
**/\r
-#define CPUID_PLATFORM_QOS_MONITORING 0x0F\r
+#define CPUID_INTEL_RDT_MONITORING 0x0F\r
\r
/**\r
- CPUID Platform QoS Monitoring Information Enumeration Sub-leaf\r
+ CPUID Intel Resource Director Technology (Intel RDT) Monitoring Information\r
+ Enumeration Sub-leaf\r
\r
- @param EAX CPUID_PLATFORM_QOS_MONITORING (0x0F)\r
- @param ECX CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF (0x00)\r
+ @param EAX CPUID_INTEL_RDT_MONITORING (0x0F)\r
+ @param ECX CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF (0x00)\r
\r
@retval EAX Reserved.\r
@retval EBX Maximum range (zero-based) of RMID within this physical\r
processor of all types.\r
@retval ECX Reserved.\r
- @retval EDX L3 Cache QoS Monitoring Information Enumeration described by the\r
- type CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF_EDX.\r
+ @retval EDX L3 Cache Intel RDT Monitoring Information Enumeration described by\r
+ the type CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF_EDX.\r
\r
<b>Example usage</b>\r
@code\r
UINT32 Ebx;\r
- CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF_EDX Edx;\r
+ CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF_EDX Edx;\r
\r
AsmCpuidEx (\r
- CPUID_PLATFORM_QOS_MONITORING, CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF,\r
+ CPUID_INTEL_RDT_MONITORING, CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF,\r
NULL, &Ebx, NULL, &Edx.Uint32\r
);\r
@endcode\r
**/\r
-#define CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF 0x00\r
+#define CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF 0x00\r
\r
/**\r
- CPUID Platform QoS Monitoring Information EDX for CPUID leaf\r
- #CPUID_PLATFORM_QOS_MONITORING, sub-leaf\r
- #CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF.\r
+ CPUID Intel RDT Monitoring Information EDX for CPUID leaf\r
+ #CPUID_INTEL_RDT_MONITORING, sub-leaf\r
+ #CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF.\r
**/\r
typedef union {\r
///\r
struct {\r
UINT32 Reserved1:1;\r
///\r
- /// [Bit 1] Supports L3 Cache QoS Monitoring if 1.\r
+ /// [Bit 1] Supports L3 Cache Intel RDT Monitoring if 1.\r
///\r
- UINT32 L3CacheQosEnforcement:1;\r
+ UINT32 L3CacheRDT_M:1;\r
UINT32 Reserved2:30;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
UINT32 Uint32;\r
-} CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF_EDX;\r
+} CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF_EDX;\r
\r
/**\r
- CPUID Platform QoS Monitoring Information Capability Sub-leaf\r
+ CPUID L3 Cache Intel RDT Monitoring Capability Enumeration Sub-leaf\r
\r
- @param EAX CPUID_PLATFORM_QOS_MONITORING (0x0F)\r
- @param ECX CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF (0x01)\r
+ @param EAX CPUID_INTEL_RDT_MONITORING (0x0F)\r
+ @param ECX CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF (0x01)\r
\r
@retval EAX Reserved.\r
@retval EBX Conversion factor from reported IA32_QM_CTR value to occupancy metric (bytes).\r
@retval ECX Maximum range (zero-based) of RMID of this resource type.\r
- @retval EDX L3 Cache QoS Monitoring Capability information described by the\r
- type CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF_EDX.\r
+ @retval EDX L3 Cache Intel RDT Monitoring Capability information described by the\r
+ type CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF_EDX.\r
\r
<b>Example usage</b>\r
@code\r
- UINT32 Ebx;\r
- UINT32 Ecx;\r
- CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF_EDX Edx;\r
+ UINT32 Ebx;\r
+ UINT32 Ecx;\r
+ CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF_EDX Edx;\r
\r
AsmCpuidEx (\r
- CPUID_PLATFORM_QOS_MONITORING, CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF,\r
+ CPUID_INTEL_RDT_MONITORING, CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF,\r
NULL, &Ebx, &Ecx, &Edx.Uint32\r
);\r
@endcode\r
**/\r
-#define CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF 0x01\r
+#define CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF 0x01\r
\r
/**\r
- CPUID Platform QoS Monitoring Information Capability EDX for CPUID leaf\r
- #CPUID_PLATFORM_QOS_MONITORING, sub-leaf\r
- #CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF.\r
+ CPUID L3 Cache Intel RDT Monitoring Capability Information EDX for CPUID leaf\r
+ #CPUID_INTEL_RDT_MONITORING, sub-leaf\r
+ #CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF.\r
**/\r
typedef union {\r
///\r
/// [Bit 0] Supports L3 occupancy monitoring if 1.\r
///\r
UINT32 L3CacheOccupancyMonitoring:1;\r
- UINT32 Reserved:31;\r
+ ///\r
+ /// [Bit 1] Supports L3 Total Bandwidth monitoring if 1.\r
+ ///\r
+ UINT32 L3CacheTotalBandwidthMonitoring:1;\r
+ ///\r
+ /// [Bit 2] Supports L3 Local Bandwidth monitoring if 1.\r
+ ///\r
+ UINT32 L3CacheLocalBandwidthMonitoring:1;\r
+ UINT32 Reserved:29;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
UINT32 Uint32;\r
-} CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF_EDX;\r
+} CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF_EDX;\r
\r
\r
/**\r
- CPUID Platform QoS Enforcement Information\r
+ CPUID Intel Resource Director Technology (Intel RDT) Allocation Information\r
\r
- @param EAX CPUID_PLATFORM_QOS_ENFORCEMENT (0x10).\r
- @param ECX CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF (0x00).\r
- CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF (0x01).\r
- Additional sub leafs 1..n based in RESID from sub leaf 0x00.\r
+ @param EAX CPUID_INTEL_RDT_ALLOCATION (0x10).\r
+ @param ECX CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF (0x00).\r
+ CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF (0x01).\r
+ CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF (0x02).\r
**/\r
-#define CPUID_PLATFORM_QOS_ENFORCEMENT 0x10\r
+#define CPUID_INTEL_RDT_ALLOCATION 0x10\r
\r
/**\r
- CPUID Platform QoS Enforcement Information\r
+ Intel Resource Director Technology (Intel RDT) Allocation Enumeration Sub-leaf\r
\r
- @param EAX CPUID_PLATFORM_QOS_ENFORCEMENT (0x10)\r
- @param ECX CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF (0x00).\r
+ @param EAX CPUID_INTEL_RDT_ALLOCATION (0x10)\r
+ @param ECX CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF (0x00).\r
\r
@retval EAX Reserved.\r
- @retval EBX L3 Cache QoS Enforcement information described by the\r
- type CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF_EBX.\r
+ @retval EBX L3 and L2 Cache Allocation Technology information described by\r
+ the type CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF_EBX.\r
@retval ECX Reserved.\r
@retval EDX Reserved.\r
\r
<b>Example usage</b>\r
@code\r
- CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF_EBX Ebx;\r
+ CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF_EBX Ebx;\r
\r
AsmCpuidEx (\r
- CPUID_PLATFORM_QOS_ENFORCEMENT, CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF,\r
+ CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF,\r
NULL, &Ebx.Uint32, NULL, NULL\r
);\r
@endcode\r
**/\r
-#define CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF 0x00\r
+#define CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF 0x00\r
\r
/**\r
- CPUID Platform QoS Enforcement Information EBX for CPUID leaf\r
- #CPUID_PLATFORM_QOS_ENFORCEMENT, sub-leaf\r
- #CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF.\r
+ CPUID L3 and L2 Cache Allocation Support Information EBX for CPUID leaf\r
+ #CPUID_INTEL_RDT_ALLOCATION, sub-leaf\r
+ #CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF.\r
**/\r
typedef union {\r
///\r
struct {\r
UINT32 Reserved1:1;\r
///\r
- /// [Bit 1] Supports L3 Cache QoS Enforcement if 1.\r
+ /// [Bit 1] Supports L3 Cache Allocation Technology if 1.\r
///\r
- UINT32 L3CacheQosEnforcement:1;\r
- UINT32 Reserved2:30;\r
+ UINT32 L3CacheAllocation:1;\r
+ ///\r
+ /// [Bit 2] Supports L2 Cache Allocation Technology if 1.\r
+ ///\r
+ UINT32 L2CacheAllocation:1;\r
+ UINT32 Reserved2:29;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
UINT32 Uint32;\r
-} CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF_EBX;\r
+} CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF_EBX;\r
\r
\r
/**\r
- CPUID Platform QoS Enforcement Information\r
+ L3 Cache Allocation Technology Enumeration Sub-leaf\r
\r
- @param EAX CPUID_PLATFORM_QOS_ENFORCEMENT (0x10)\r
- @param ECX CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF (0x00)\r
- Additional sub leafs 1..n based in RESID from sub leaf 0x00.\r
+ @param EAX CPUID_INTEL_RDT_ALLOCATION (0x10)\r
+ @param ECX CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF (0x01)\r
\r
- @retval EAX RESID L3 Cache3 QoS Enforcement information described by the\r
- type CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_EAX.\r
+ @retval EAX RESID L3 Cache Allocation Technology information described by\r
+ the type CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EAX.\r
@retval EBX Bit-granular map of isolation/contention of allocation units.\r
- @retval ECX RESID L3 Cache3 QoS Enforcement information described by the\r
- type CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_ECX.\r
- @retval EDX RESID L3 Cache3 QoS Enforcement information described by the\r
- type CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_EDX.\r
+ @retval ECX RESID L3 Cache Allocation Technology information described by\r
+ the type CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_ECX.\r
+ @retval EDX RESID L3 Cache Allocation Technology information described by\r
+ the type CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EDX.\r
\r
<b>Example usage</b>\r
@code\r
- CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_EAX Eax;\r
+ CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EAX Eax;\r
UINT32 Ebx;\r
- CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_ECX Ecx;\r
- CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_EDX Edx;\r
+ CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_ECX Ecx;\r
+ CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EDX Edx;\r
\r
AsmCpuidEx (\r
- CPUID_PLATFORM_QOS_ENFORCEMENT, CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF,\r
+ CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF,\r
&Eax.Uint32, &Ebx, &Ecx.Uint32, &Edx.Uint32\r
);\r
@endcode\r
**/\r
-#define CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF 0x01\r
+#define CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF 0x01\r
\r
/**\r
- CPUID Platform QoS Enforcement Information EAX for CPUID leaf\r
- #CPUID_PLATFORM_QOS_ENFORCEMENT, sub-leaf\r
- #CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF.\r
+ CPUID L3 Cache Allocation Technology Information EAX for CPUID leaf\r
+ #CPUID_INTEL_RDT_ALLOCATION, sub-leaf\r
+ #CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF.\r
**/\r
typedef union {\r
///\r
///\r
struct {\r
///\r
- /// [Bits 3:0] Length of the capacity bit mask for the corresponding ResID.\r
+ /// [Bits 4:0] Length of the capacity bit mask for the corresponding ResID\r
+ /// using minus-one notation.\r
///\r
- UINT32 CapacityLength:4;\r
- UINT32 Reserved:28;\r
+ UINT32 CapacityLength:5;\r
+ UINT32 Reserved:27;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
UINT32 Uint32;\r
-} CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_EAX;\r
+} CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EAX;\r
\r
/**\r
- CPUID Platform QoS Enforcement Information ECX for CPUID leaf\r
- #CPUID_PLATFORM_QOS_ENFORCEMENT, sub-leaf\r
- #CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF.\r
+ CPUID L3 Cache Allocation Technology Information ECX for CPUID leaf\r
+ #CPUID_INTEL_RDT_ALLOCATION, sub-leaf\r
+ #CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF.\r
**/\r
typedef union {\r
///\r
/// All bit fields as a 32-bit value\r
///\r
UINT32 Uint32;\r
-} CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_ECX;\r
+} CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_ECX;\r
\r
/**\r
- CPUID Platform QoS Enforcement Information EDX for CPUID leaf\r
- #CPUID_PLATFORM_QOS_ENFORCEMENT, sub-leaf\r
- #CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF.\r
+ CPUID L3 Cache Allocation Technology Information EDX for CPUID leaf\r
+ #CPUID_INTEL_RDT_ALLOCATION, sub-leaf\r
+ #CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF.\r
**/\r
typedef union {\r
///\r
/// All bit fields as a 32-bit value\r
///\r
UINT32 Uint32;\r
-} CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_EDX;\r
+} CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EDX;\r
+\r
+/**\r
+ L2 Cache Allocation Technology Enumeration Sub-leaf\r
+\r
+ @param EAX CPUID_INTEL_RDT_ALLOCATION (0x10)\r
+ @param ECX CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF (0x02)\r
+\r
+ @retval EAX RESID L2 Cache Allocation Technology information described by\r
+ the type CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EAX.\r
+ @retval EBX Bit-granular map of isolation/contention of allocation units.\r
+ @retval ECX Reserved.\r
+ @retval EDX RESID L2 Cache Allocation Technology information described by\r
+ the type CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EDX.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EAX Eax;\r
+ UINT32 Ebx;\r
+ CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EDX Edx;\r
+\r
+ AsmCpuidEx (\r
+ CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF,\r
+ &Eax.Uint32, &Ebx, NULL, &Edx.Uint32\r
+ );\r
+ @endcode\r
+**/\r
+#define CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF 0x02\r
+\r
+/**\r
+ CPUID L2 Cache Allocation Technology Information EAX for CPUID leaf\r
+ #CPUID_INTEL_RDT_ALLOCATION, sub-leaf\r
+ #CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 4:0] Length of the capacity bit mask for the corresponding ResID\r
+ /// using minus-one notation.\r
+ ///\r
+ UINT32 CapacityLength:5;\r
+ UINT32 Reserved:27;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EAX;\r
+\r
+/**\r
+ CPUID L2 Cache Allocation Technology Information EDX for CPUID leaf\r
+ #CPUID_INTEL_RDT_ALLOCATION, sub-leaf\r
+ #CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 15:0] Highest COS number supported for this ResID.\r
+ ///\r
+ UINT32 HighestCosNumber:16;\r
+ UINT32 Reserved:16;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EDX;\r
+\r
+\r
+/**\r
+ Intel SGX resource capability and configuration.\r
+ See Section 37.7.2 "Intel(R) SGX Resource Enumeration Leaves".\r
+\r
+ If CPUID.(EAX=07H, ECX=0H):EBX.SGX = 1, the processor also supports querying\r
+ CPUID with EAX=12H on Intel SGX resource capability and configuration.\r
+\r
+ @param EAX CPUID_INTEL_SGX (0x12)\r
+ @param ECX CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF (0x00).\r
+ CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF (0x01).\r
+ CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF (0x02).\r
+ Sub leafs 2..n based on the sub-leaf-type encoding (returned in EAX[3:0])\r
+ until the sub-leaf type is invalid.\r
+\r
+**/\r
+#define CPUID_INTEL_SGX 0x12\r
+\r
+/**\r
+ Sub-Leaf 0 Enumeration of Intel SGX Capabilities.\r
+ Enumerates Intel SGX capability, including enclave instruction opcode support.\r
+\r
+ @param EAX CPUID_INTEL_SGX (0x12)\r
+ @param ECX CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF (0x00)\r
+\r
+ @retval EAX The format of Sub-Leaf 0 Enumeration of Intel SGX Capabilities is\r
+ described by the type CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EAX.\r
+ @retval EBX MISCSELECT: Reports the bit vector of supported extended features\r
+ that can be written to the MISC region of the SSA.\r
+ @retval ECX Reserved.\r
+ @retval EDX The format of Sub-Leaf 0 Enumeration of Intel SGX Capabilities is\r
+ described by the type CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EDX.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EAX Eax;\r
+ UINT32 Ebx;\r
+ CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EDX Edx;\r
+\r
+ AsmCpuidEx (\r
+ CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF,\r
+ &Eax.Uint32, &Ebx, NULL, &Edx.Uint32\r
+ );\r
+ @endcode\r
+**/\r
+#define CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF 0x00\r
+\r
+/**\r
+ Sub-Leaf 0 Enumeration of Intel SGX Capabilities EAX for CPUID leaf #CPUID_INTEL_SGX,\r
+ sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] If 1, indicates leaf functions of SGX1 instruction are supported.\r
+ ///\r
+ UINT32 SGX1:1;\r
+ ///\r
+ /// [Bit 1] If 1, indicates leaf functions of SGX2 instruction are supported.\r
+ ///\r
+ UINT32 SGX2:1;\r
+ UINT32 Reserved:30;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EAX;\r
+\r
+/**\r
+ Sub-Leaf 0 Enumeration of Intel SGX Capabilities EDX for CPUID leaf #CPUID_INTEL_SGX,\r
+ sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 7:0] The maximum supported enclave size is 2^(EDX[7:0]) bytes\r
+ /// when not in 64-bit mode.\r
+ ///\r
+ UINT32 MaxEnclaveSize_Not64:8;\r
+ ///\r
+ /// [Bit 15:8] The maximum supported enclave size is 2^(EDX[15:8]) bytes\r
+ /// when operating in 64-bit mode.\r
+ ///\r
+ UINT32 MaxEnclaveSize_64:8;\r
+ UINT32 Reserved:16;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EDX;\r
+\r
+\r
+/**\r
+ Sub-Leaf 1 Enumeration of Intel SGX Capabilities.\r
+ Enumerates Intel SGX capability of processor state configuration and enclave\r
+ configuration in the SECS structure.\r
+\r
+ @param EAX CPUID_INTEL_SGX (0x12)\r
+ @param ECX CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF (0x01)\r
+\r
+ @retval EAX Report the valid bits of SECS.ATTRIBUTES[31:0] that software can\r
+ set with ECREATE. SECS.ATTRIBUTES[n] can be set to 1 using ECREATE\r
+ only if EAX[n] is 1, where n < 32.\r
+ @retval EBX Report the valid bits of SECS.ATTRIBUTES[63:32] that software can\r
+ set with ECREATE. SECS.ATTRIBUTES[n+32] can be set to 1 using ECREATE\r
+ only if EBX[n] is 1, where n < 32.\r
+ @retval ECX Report the valid bits of SECS.ATTRIBUTES[95:64] that software can\r
+ set with ECREATE. SECS.ATTRIBUTES[n+64] can be set to 1 using ECREATE\r
+ only if ECX[n] is 1, where n < 32.\r
+ @retval EDX Report the valid bits of SECS.ATTRIBUTES[127:96] that software can\r
+ set with ECREATE. SECS.ATTRIBUTES[n+96] can be set to 1 using ECREATE\r
+ only if EDX[n] is 1, where n < 32.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT32 Eax;\r
+ UINT32 Ebx;\r
+ UINT32 Ecx;\r
+ UINT32 Edx;\r
+\r
+ AsmCpuidEx (\r
+ CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF,\r
+ &Eax, &Ebx, &Ecx, &Edx\r
+ );\r
+ @endcode\r
+**/\r
+#define CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF 0x01\r
+\r
+\r
+/**\r
+ Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources.\r
+ Enumerates available EPC resources.\r
+\r
+ @param EAX CPUID_INTEL_SGX (0x12)\r
+ @param ECX CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF (0x02)\r
+\r
+ @retval EAX The format of Sub-Leaf Index 2 or Higher Enumeration of Intel SGX\r
+ Resources is described by the type\r
+ CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EAX.\r
+ @retval EBX The format of Sub-Leaf Index 2 or Higher Enumeration of Intel SGX\r
+ Resources is described by the type\r
+ CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EBX.\r
+ @retval EDX The format of Sub-Leaf Index 2 or Higher Enumeration of Intel SGX\r
+ Resources is described by the type\r
+ CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_ECX.\r
+ @retval EDX The format of Sub-Leaf Index 2 or Higher Enumeration of Intel SGX\r
+ Resources is described by the type\r
+ CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EDX.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EAX Eax;\r
+ CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EBX Ebx;\r
+ CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_ECX Ecx;\r
+ CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EDX Edx;\r
+\r
+ AsmCpuidEx (\r
+ CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF,\r
+ &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32\r
+ );\r
+ @endcode\r
+**/\r
+#define CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF 0x02\r
+\r
+/**\r
+ Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources EAX for CPUID\r
+ leaf #CPUID_INTEL_SGX, sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 3:0] Sub-leaf-type encoding.\r
+ /// 0000b: This sub-leaf is invalid, EBX:EAX and EDX:ECX report 0.\r
+ /// 0001b: This sub-leaf provides information on the Enclave Page Cache (EPC)\r
+ /// in EBX:EAX and EDX:ECX.\r
+ /// All other encoding are reserved.\r
+ ///\r
+ UINT32 SubLeafType:4;\r
+ UINT32 Reserved:8;\r
+ ///\r
+ /// [Bit 31:12] If EAX[3:0] = 0001b, these are bits 31:12 of the physical address of\r
+ /// the base of the EPC section.\r
+ ///\r
+ UINT32 LowAddressOfEpcSection:20;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EAX;\r
+\r
+/**\r
+ Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources EBX for CPUID\r
+ leaf #CPUID_INTEL_SGX, sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 19:0] If EAX[3:0] = 0001b, these are bits 51:32 of the physical address of\r
+ /// the base of the EPC section.\r
+ ///\r
+ UINT32 HighAddressOfEpcSection:20;\r
+ UINT32 Reserved:12;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EBX;\r
+\r
+/**\r
+ Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources ECX for CPUID\r
+ leaf #CPUID_INTEL_SGX, sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 3:0] The EPC section encoding.\r
+ /// 0000b: Not valid.\r
+ /// 0001b: The EPC section is confidentiality, integrity and replay protected.\r
+ /// All other encoding are reserved.\r
+ ///\r
+ UINT32 EpcSection:4;\r
+ UINT32 Reserved:8;\r
+ ///\r
+ /// [Bit 31:12] If EAX[3:0] = 0001b, these are bits 31:12 of the size of the\r
+ /// corresponding EPC section within the Processor Reserved Memory.\r
+ ///\r
+ UINT32 LowSizeOfEpcSection:20;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_ECX;\r
+\r
+/**\r
+ Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources EDX for CPUID\r
+ leaf #CPUID_INTEL_SGX, sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 19:0] If EAX[3:0] = 0001b, these are bits 51:32 of the size of the\r
+ /// corresponding EPC section within the Processor Reserved Memory.\r
+ ///\r
+ UINT32 HighSizeOfEpcSection:20;\r
+ UINT32 Reserved:12;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EDX;\r
\r
\r
/**\r
///\r
struct {\r
///\r
- /// [Bit 0] If 1, Indicates that IA32_RTIT_CTL.CR3Filter can be set to 1,\r
+ /// [Bit 0] If 1, indicates that IA32_RTIT_CTL.CR3Filter can be set to 1,\r
/// and that IA32_RTIT_CR3_MATCH MSR can be accessed.\r
///\r
UINT32 Cr3Filter:1;\r
///\r
- /// [Bit 1] If 1, Indicates support of Configurable PSB and Cycle-Accurate\r
+ /// [Bit 1] If 1, indicates support of Configurable PSB and Cycle-Accurate\r
/// Mode.\r
///\r
UINT32 ConfigurablePsb:1;\r
///\r
- /// [Bit 2] If 1, Indicates support of IP Filtering, TraceStop filtering,\r
+ /// [Bit 2] If 1, indicates support of IP Filtering, TraceStop filtering,\r
/// and preservation of Intel PT MSRs across warm reset.\r
///\r
UINT32 IpTraceStopFiltering:1;\r
///\r
- /// [Bit 3] If 1, Indicates support of MTC timing packet and suppression of\r
+ /// [Bit 3] If 1, indicates support of MTC timing packet and suppression of\r
/// COFI-based packets.\r
///\r
UINT32 Mtc:1;\r
- UINT32 Reserved:28;\r
+ ///\r
+ /// [Bit 4] If 1, indicates support of PTWRITE. Writes can set\r
+ /// IA32_RTIT_CTL[12] (PTWEn) and IA32_RTIT_CTL[5] (FUPonPTW), and PTWRITE\r
+ /// can generate packets.\r
+ ///\r
+ UINT32 PTWrite:1;\r
+ ///\r
+ /// [Bit 5] If 1, indicates support of Power Event Trace. Writes can set\r
+ /// IA32_RTIT_CTL[4] (PwrEvtEn), enabling Power Event Trace packet\r
+ /// generation.\r
+ ///\r
+ UINT32 PowerEventTrace:1;\r
+ UINT32 Reserved:26;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
UINT32 ToPA:1;\r
///\r
- /// [Bit 2] If 1, Indicates support of Single-Range Output scheme.\r
+ /// [Bit 2] If 1, indicates support of Single-Range Output scheme.\r
///\r
UINT32 SingleRangeOutput:1;\r
///\r
- /// [Bit 3] If 1, Indicates support of output to Trace Transport subsystem.\r
+ /// [Bit 3] If 1, indicates support of output to Trace Transport subsystem.\r
///\r
UINT32 TraceTransportSubsystem:1;\r
UINT32 Reserved:27;\r
///\r
- /// [Bit 31] If 1, Generated packets which contain IP payloads have LIP\r
+ /// [Bit 31] If 1, generated packets which contain IP payloads have LIP\r
/// values, which include the CS base component.\r
///\r
UINT32 LIP:1;\r
\r
\r
/**\r
- CPUID Time Stamp Counter Information\r
+ CPUID Time Stamp Counter and Nominal Core Crystal Clock Information\r
\r
@note\r
If EBX[31:0] is 0, the TSC/"core crystal clock" ratio is not enumerated.\r
EBX[31:0]/EAX[31:0] indicates the ratio of the TSC frequency and the core\r
crystal clock frequency.\r
- "TSC frequency" = "core crystal clock frequency" * EBX/EAX.\r
+ If ECX is 0, the nominal core crystal clock frequency is not enumerated.\r
+ "TSC frequency" = "core crystal clock frequency" * EBX/EAX.\r
The core crystal clock may differ from the reference clock, bus clock, or core\r
clock frequencies.\r
\r
TSC/"core crystal clock" ratio\r
@retval EBX An unsigned integer which is the numerator of the\r
TSC/"core crystal clock" ratio.\r
- @retval ECX Reserved.\r
+ @retval ECX An unsigned integer which is the nominal frequency\r
+ of the core crystal clock in Hz.\r
@retval EDX Reserved.\r
\r
<b>Example usage</b>\r
@code\r
UINT32 Eax;\r
UINT32 Ebx;\r
+ UINT32 Ecx;\r
\r
- AsmCpuid (CPUID_TIME_STAMP_COUNTER, &Eax, &Ebx, NULL, NULL);\r
+ AsmCpuid (CPUID_TIME_STAMP_COUNTER, &Eax, &Ebx, &Ecx, NULL);\r
@endcode\r
**/\r
#define CPUID_TIME_STAMP_COUNTER 0x15\r
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