If a register returned is a single 32-bit value, then a data structure is\r
not provided for that register.\r
\r
- Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials are licensed and made available under\r
the terms and conditions of the BSD License which accompanies this distribution.\r
The full text of the license may be found at\r
\r
@par Specification Reference:\r
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 2A,\r
- December 2015, CPUID instruction.\r
+ November 2018, CPUID instruction.\r
\r
**/\r
\r
///\r
UINT32 PGE:1;\r
///\r
- /// [Bit 14] Machine Check Architecture. The Machine Check Architecture,\r
- /// which provides a compatible mechanism for error reporting in P6 family,\r
- /// Pentium 4, Intel Xeon processors, and future processors, is supported.\r
- /// The MCG_CAP MSR contains feature bits describing how many banks of error\r
- /// reporting MSRs are supported.\r
+ /// [Bit 14] Machine Check Architecture. A value of 1 indicates the Machine\r
+ /// Check Architecture of reporting machine errors is supported. The MCG_CAP\r
+ /// MSR contains feature bits describing how many banks of error reporting\r
+ /// MSRs are supported.\r
///\r
UINT32 MCA:1;\r
///\r
<tr><td> 0x56 </td><td> TLB </td><td> Data TLB0: 4 MByte pages, 4-way set associative, 16 entries</td></tr>\r
<tr><td> 0x57 </td><td> TLB </td><td> Data TLB0: 4 KByte pages, 4-way associative, 16 entries</td></tr>\r
<tr><td> 0x59 </td><td> TLB </td><td> Data TLB0: 4 KByte pages, fully associative, 16 entries</td></tr>\r
- <tr><td> 0x5A </td><td> TLB </td><td> Data TLB0: 2-MByte or 4 MByte pages, 4-way set associative, 32 entries</td></tr>\r
+ <tr><td> 0x5A </td><td> TLB </td><td> Data TLB0: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries</td></tr>\r
<tr><td> 0x5B </td><td> TLB </td><td> Data TLB: 4 KByte and 4 MByte pages, 64 entries</td></tr>\r
<tr><td> 0x5C </td><td> TLB </td><td> Data TLB: 4 KByte and 4 MByte pages,128 entries</td></tr>\r
<tr><td> 0x5D </td><td> TLB </td><td> Data TLB: 4 KByte and 4 MByte pages,256 entries</td></tr>\r
<tr><td> 0x60 </td><td> Cache </td><td> 1st-level data cache: 16 KByte, 8-way set associative, 64 byte line size</td></tr>\r
<tr><td> 0x61 </td><td> TLB </td><td> Instruction TLB: 4 KByte pages, fully associative, 48 entries</td></tr>\r
- <tr><td> 0x63 </td><td> TLB </td><td> Data TLB: 1 GByte pages, 4-way set associative, 4 entries</td></tr>\r
+ <tr><td> 0x63 </td><td> TLB </td><td> Data TLB: 2 MByte or 4 MByte pages, 4-way set associative,\r
+ 32 entries and a separate array with 1 GByte pages, 4-way set associative,\r
+ 4 entries</td></tr>\r
+ <tr><td> 0x64 </td><td> TLB </td><td> Data TLB: 4 KByte pages, 4-way set associative, 512 entries</td></tr>\r
<tr><td> 0x66 </td><td> Cache </td><td> 1st-level data cache: 8 KByte, 4-way set associative, 64 byte line size</td></tr>\r
<tr><td> 0x67 </td><td> Cache </td><td> 1st-level data cache: 16 KByte, 4-way set associative, 64 byte line size</td></tr>\r
<tr><td> 0x68 </td><td> Cache </td><td> 1st-level data cache: 32 KByte, 4-way set associative, 64 byte line size</td></tr>\r
<tr><td> 0xC2 </td><td> DTLB </td><td> DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries</td></tr>\r
<tr><td> 0xC3 </td><td> STLB </td><td> Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative,\r
1536 entries. Also 1GBbyte pages, 4-way, 16 entries.</td></tr>\r
+ <tr><td> 0xC4 </td><td> DTLB </td><td> DTLB: 2M/4M Byte pages, 4-way associative, 32 entries</td></tr>\r
<tr><td> 0xCA </td><td> STLB </td><td> Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries</td></tr>\r
<tr><td> 0xD0 </td><td> Cache </td><td> 3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size</td></tr>\r
<tr><td> 0xD1 </td><td> Cache </td><td> 3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size</td></tr>\r
<tr><td> 0xEC </td><td> Cache </td><td> 3rd-level cache: 24MByte, 24-way set associative, 64 byte line size</td></tr>\r
<tr><td> 0xF0 </td><td> Prefetch</td><td> 64-Byte prefetching</td></tr>\r
<tr><td> 0xF1 </td><td> Prefetch</td><td> 128-Byte prefetching</td></tr>\r
+ <tr><td> 0xFE </td><td> General </td><td> CPUID leaf 2 does not report TLB descriptor information; use CPUID\r
+ leaf 18H to query TLB and other address translation parameters.</td></tr>\r
<tr><td> 0xFF </td><td> General </td><td> CPUID leaf 2 does not report cache descriptor information,\r
use CPUID leaf 4 to query cache parameters</td></tr>\r
</table>\r
/// IA32_THREAD_STALL MSRs are supported if set.\r
///\r
UINT32 HDC:1;\r
- UINT32 Reserved3:18;\r
+ ///\r
+ /// [Bit 14] Intel Turbo Boost Max Technology 3.0 available.\r
+ ///\r
+ UINT32 TurboBoostMaxTechnology30:1;\r
+ ///\r
+ /// [Bit 15] HWP Capabilities.\r
+ /// Highest Performance change is supported if set.\r
+ ///\r
+ UINT32 HWPCapabilities:1;\r
+ ///\r
+ /// [Bit 16] HWP PECI override is supported if set.\r
+ ///\r
+ UINT32 HWPPECIOverride:1;\r
+ ///\r
+ /// [Bit 17] Flexible HWP is supported if set.\r
+ ///\r
+ UINT32 FlexibleHWP:1;\r
+ ///\r
+ /// [Bit 18] Fast access mode for the IA32_HWP_REQUEST MSR is supported if set.\r
+ ///\r
+ UINT32 FastAccessMode:1;\r
+ UINT32 Reserved4:1;\r
+ ///\r
+ /// [Bit 20] Ignoring Idle Logical Processor HWP request is supported if set.\r
+ ///\r
+ UINT32 IgnoringIdleLogicalProcessorHWPRequest:1;\r
+ UINT32 Reserved5:11;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
SubLeaf,\r
NULL, &Ebx.Uint32, &Ecx.Uint32, NULL\r
);\r
- SubLeaf++;\r
- } while (SubLeaf <= Eax);\r
+ }\r
@endcode\r
**/\r
#define CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS 0x07\r
///\r
UINT32 RTM:1;\r
///\r
- /// [Bit 12] Supports Platform Quality of Service Monitoring (PQM)\r
- /// capability if 1.\r
+ /// [Bit 12] Supports Intel(R) Resource Director Technology (Intel(R) RDT)\r
+ /// Monitoring capability if 1.\r
///\r
- UINT32 PQM:1;\r
+ UINT32 RDT_M:1;\r
///\r
/// [Bit 13] Deprecates FPU CS and FPU DS values if 1.\r
///\r
///\r
UINT32 MPX:1;\r
///\r
- /// [Bit 15] Supports Platform Quality of Service Enforcement (PQE)\r
- /// capability if 1.\r
+ /// [Bit 15] Supports Intel(R) Resource Director Technology (Intel(R) RDT)\r
+ /// Allocation capability if 1.\r
///\r
- UINT32 PQE:1;\r
- UINT32 Reserved2:2;\r
+ UINT32 RDT_A:1;\r
+ ///\r
+ /// [Bit 16] AVX512F.\r
+ ///\r
+ UINT32 AVX512F:1;\r
+ ///\r
+ /// [Bit 17] AVX512DQ.\r
+ ///\r
+ UINT32 AVX512DQ:1;\r
///\r
/// [Bit 18] If 1 indicates the processor supports the RDSEED instruction.\r
///\r
/// instructions) if 1.\r
///\r
UINT32 SMAP:1;\r
- UINT32 Reserved3:2;\r
+ ///\r
+ /// [Bit 21] AVX512_IFMA.\r
+ ///\r
+ UINT32 AVX512_IFMA:1;\r
+ UINT32 Reserved6:1;\r
///\r
/// [Bit 23] If 1 indicates the processor supports the CLFLUSHOPT instruction.\r
///\r
UINT32 CLFLUSHOPT:1;\r
- UINT32 Reserved4:1;\r
+ ///\r
+ /// [Bit 24] If 1 indicates the processor supports the CLWB instruction.\r
+ ///\r
+ UINT32 CLWB:1;\r
///\r
/// [Bit 25] If 1 indicates the processor supports the Intel Processor Trace\r
/// extensions.\r
///\r
UINT32 IntelProcessorTrace:1;\r
- UINT32 Reserved5:6;\r
+ ///\r
+ /// [Bit 26] AVX512PF. (Intel Xeon Phi only.).\r
+ ///\r
+ UINT32 AVX512PF:1;\r
+ ///\r
+ /// [Bit 27] AVX512ER. (Intel Xeon Phi only.).\r
+ ///\r
+ UINT32 AVX512ER:1;\r
+ ///\r
+ /// [Bit 28] AVX512CD.\r
+ ///\r
+ UINT32 AVX512CD:1;\r
+ ///\r
+ /// [Bit 29] Supports Intel(R) Secure Hash Algorithm Extensions (Intel(R)\r
+ /// SHA Extensions) if 1.\r
+ ///\r
+ UINT32 SHA:1;\r
+ ///\r
+ /// [Bit 30] AVX512BW.\r
+ ///\r
+ UINT32 AVX512BW:1;\r
+ ///\r
+ /// [Bit 31] AVX512VL.\r
+ ///\r
+ UINT32 AVX512VL:1;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
struct {\r
///\r
/// [Bit 0] If 1 indicates the processor supports the PREFETCHWT1 instruction.\r
+ /// (Intel Xeon Phi only.)\r
///\r
UINT32 PREFETCHWT1:1;\r
- UINT32 Reserved1:2;\r
+ ///\r
+ /// [Bit 1] AVX512_VBMI.\r
+ ///\r
+ UINT32 AVX512_VBMI:1;\r
+ ///\r
+ /// [Bit 2] Supports user-mode instruction prevention if 1.\r
+ ///\r
+ UINT32 UMIP:1;\r
///\r
/// [Bit 3] Supports protection keys for user-mode pages if 1.\r
///\r
/// RDPKRU/WRPKRU instructions).\r
///\r
UINT32 OSPKE:1;\r
- UINT32 Reserved2:27;\r
+ UINT32 Reserved5:9;\r
+ ///\r
+ /// [Bits 14] AVX512_VPOPCNTDQ. (Intel Xeon Phi only.).\r
+ ///\r
+ UINT32 AVX512_VPOPCNTDQ:1;\r
+ UINT32 Reserved7:1;\r
+ ///\r
+ /// [Bits 16] Supports 5-level paging if 1.\r
+ ///\r
+ UINT32 FiveLevelPage:1;\r
+ ///\r
+ /// [Bits 21:17] The value of MAWAU used by the BNDLDX and BNDSTX instructions\r
+ /// in 64-bit mode.\r
+ ///\r
+ UINT32 MAWAU:5;\r
+ ///\r
+ /// [Bit 22] RDPID and IA32_TSC_AUX are available if 1.\r
+ ///\r
+ UINT32 RDPID:1;\r
+ UINT32 Reserved3:7;\r
+ ///\r
+ /// [Bit 30] Supports SGX Launch Configuration if 1.\r
+ ///\r
+ UINT32 SGX_LC:1;\r
+ UINT32 Reserved4:1;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
UINT32 Uint32;\r
} CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX;\r
\r
+/**\r
+ CPUID Structured Extended Feature Flags Enumeration in EDX for CPUID leaf\r
+ #CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS sub leaf\r
+ #CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 1:0] Reserved.\r
+ ///\r
+ UINT32 Reserved1:2;\r
+ ///\r
+ /// [Bit 2] AVX512_4VNNIW. (Intel Xeon Phi only.)\r
+ ///\r
+ UINT32 AVX512_4VNNIW:1;\r
+ ///\r
+ /// [Bit 3] AVX512_4FMAPS. (Intel Xeon Phi only.)\r
+ ///\r
+ UINT32 AVX512_4FMAPS:1;\r
+ ///\r
+ /// [Bit 25:4] Reserved.\r
+ ///\r
+ UINT32 Reserved2:22;\r
+ ///\r
+ /// [Bit 26] Enumerates support for indirect branch restricted speculation\r
+ /// (IBRS) and the indirect branch pre-dictor barrier (IBPB). Processors\r
+ /// that set this bit support the IA32_SPEC_CTRL MSR and the IA32_PRED_CMD\r
+ /// MSR. They allow software to set IA32_SPEC_CTRL[0] (IBRS) and\r
+ /// IA32_PRED_CMD[0] (IBPB).\r
+ ///\r
+ UINT32 EnumeratesSupportForIBRSAndIBPB:1;\r
+ ///\r
+ /// [Bit 27] Enumerates support for single thread indirect branch\r
+ /// predictors (STIBP). Processors that set this bit support the\r
+ /// IA32_SPEC_CTRL MSR. They allow software to set IA32_SPEC_CTRL[1]\r
+ /// (STIBP).\r
+ ///\r
+ UINT32 EnumeratesSupportForSTIBP:1;\r
+ ///\r
+ /// [Bit 28] Enumerates support for L1D_FLUSH. Processors that set this bit\r
+ /// support the IA32_FLUSH_CMD MSR. They allow software to set\r
+ /// IA32_FLUSH_CMD[0] (L1D_FLUSH).\r
+ ///\r
+ UINT32 EnumeratesSupportForL1D_FLUSH:1;\r
+ ///\r
+ /// [Bit 29] Enumerates support for the IA32_ARCH_CAPABILITIES MSR.\r
+ ///\r
+ UINT32 EnumeratesSupportForCapability:1;\r
+ ///\r
+ /// [Bit 30] Reserved.\r
+ ///\r
+ UINT32 Reserved3:1;\r
+ ///\r
+ /// [Bit 31] Enumerates support for Speculative Store Bypass Disable (SSBD).\r
+ /// Processors that set this bit sup-port the IA32_SPEC_CTRL MSR. They allow\r
+ /// software to set IA32_SPEC_CTRL[2] (SSBD).\r
+ ///\r
+ UINT32 EnumeratesSupportForSSBD:1;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EDX;\r
\r
/**\r
CPUID Direct Cache Access Information\r
/// (if Version ID > 1).\r
///\r
UINT32 FixedFunctionPerformanceCounterWidth:8;\r
- UINT32 Reserved:19;\r
+ UINT32 Reserved1:2;\r
+ ///\r
+ /// [Bits 15] AnyThread deprecation.\r
+ ///\r
+ UINT32 AnyThreadDeprecation:1;\r
+ UINT32 Reserved2:16;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
CPUID Extended Topology Information\r
\r
@note\r
+ CPUID leaf 1FH is a preferred superset to leaf 0BH. Intel recommends first\r
+ checking for the existence of Leaf 1FH before using leaf 0BH.\r
Most of Leaf 0BH output depends on the initial value in ECX. The EDX output\r
of leaf 0BH is always valid and does not vary with input value in ECX. Output\r
- value in ECX[7:0] always equals input value in ECX[7:0]. For sub-leaves that\r
- return an invalid level-type of 0 in ECX[15:8]; EAX and EBX will return 0. If\r
- an input value n in ECX returns the invalid level-type of 0 in ECX[15:8],\r
+ value in ECX[7:0] always equals input value in ECX[7:0].\r
+ Sub-leaf index 0 enumerates SMT level. Each subsequent higher sub-leaf index\r
+ enumerates a higher-level topological entity in hierarchical order.\r
+ For sub-leaves that return an invalid level-type of 0 in ECX[15:8]; EAX and\r
+ EBX will return 0.\r
+ If an input value n in ECX returns the invalid level-type of 0 in ECX[15:8],\r
other input values with ECX > n also return 0 in ECX[15:8].\r
\r
@param EAX CPUID_EXTENDED_TOPOLOGY (0x0B)\r
enabled.\r
@retval ECX Maximum size (bytes, from the beginning of the XSAVE/XRSTOR save\r
area) of the XSAVE/XRSTOR save area required by all supported\r
- features in the processor, i.e all the valid bit fields in XCR0.\r
+ features in the processor, i.e., all the valid bit fields in XCR0.\r
@retval EDX Reports the supported bits of the upper 32 bits of XCR0.\r
XCR0[n+32] can be set to 1 only if EDX[n] is 1.\r
\r
/// [Bit 9] PKRU state.\r
///\r
UINT32 PKRU:1;\r
- UINT32 Reserved:22;\r
+ UINT32 Reserved1:3;\r
+ ///\r
+ /// [Bit 13] Used for IA32_XSS, part 2.\r
+ ///\r
+ UINT32 IA32_XSS_2:1;\r
+ UINT32 Reserved2:18;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
/// [Bit 9] Used for XCR0.\r
///\r
UINT32 XCR0_1:1;\r
- UINT32 Reserved:22;\r
+ UINT32 Reserved1:3;\r
+ ///\r
+ /// [Bit 13] HWP state.\r
+ ///\r
+ UINT32 HWPState:1;\r
+ UINT32 Reserved8:18;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
\r
\r
/**\r
- CPUID Platform QoS Monitoring Information\r
+ CPUID Intel Resource Director Technology (Intel RDT) Monitoring Information\r
\r
- @param EAX CPUID_PLATFORM_QOS_MONITORING (0x0F)\r
- @param ECX CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF (0x00).\r
- CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF (0x01).\r
+ @param EAX CPUID_INTEL_RDT_MONITORING (0x0F)\r
+ @param ECX CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF (0x00).\r
+ CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF (0x01).\r
\r
**/\r
-#define CPUID_PLATFORM_QOS_MONITORING 0x0F\r
+#define CPUID_INTEL_RDT_MONITORING 0x0F\r
\r
/**\r
- CPUID Platform QoS Monitoring Information Enumeration Sub-leaf\r
+ CPUID Intel Resource Director Technology (Intel RDT) Monitoring Information\r
+ Enumeration Sub-leaf\r
\r
- @param EAX CPUID_PLATFORM_QOS_MONITORING (0x0F)\r
- @param ECX CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF (0x00)\r
+ @param EAX CPUID_INTEL_RDT_MONITORING (0x0F)\r
+ @param ECX CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF (0x00)\r
\r
@retval EAX Reserved.\r
@retval EBX Maximum range (zero-based) of RMID within this physical\r
processor of all types.\r
@retval ECX Reserved.\r
- @retval EDX L3 Cache QoS Monitoring Information Enumeration described by the\r
- type CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF_EDX.\r
+ @retval EDX L3 Cache Intel RDT Monitoring Information Enumeration described by\r
+ the type CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF_EDX.\r
\r
<b>Example usage</b>\r
@code\r
UINT32 Ebx;\r
- CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF_EDX Edx;\r
+ CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF_EDX Edx;\r
\r
AsmCpuidEx (\r
- CPUID_PLATFORM_QOS_MONITORING, CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF,\r
+ CPUID_INTEL_RDT_MONITORING, CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF,\r
NULL, &Ebx, NULL, &Edx.Uint32\r
);\r
@endcode\r
**/\r
-#define CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF 0x00\r
+#define CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF 0x00\r
\r
/**\r
- CPUID Platform QoS Monitoring Information EDX for CPUID leaf\r
- #CPUID_PLATFORM_QOS_MONITORING, sub-leaf\r
- #CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF.\r
+ CPUID Intel RDT Monitoring Information EDX for CPUID leaf\r
+ #CPUID_INTEL_RDT_MONITORING, sub-leaf\r
+ #CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF.\r
**/\r
typedef union {\r
///\r
struct {\r
UINT32 Reserved1:1;\r
///\r
- /// [Bit 1] Supports L3 Cache QoS Monitoring if 1.\r
+ /// [Bit 1] Supports L3 Cache Intel RDT Monitoring if 1.\r
///\r
- UINT32 L3CacheQosEnforcement:1;\r
+ UINT32 L3CacheRDT_M:1;\r
UINT32 Reserved2:30;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
UINT32 Uint32;\r
-} CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF_EDX;\r
+} CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF_EDX;\r
\r
/**\r
- CPUID Platform QoS Monitoring Information Capability Sub-leaf\r
+ CPUID L3 Cache Intel RDT Monitoring Capability Enumeration Sub-leaf\r
\r
- @param EAX CPUID_PLATFORM_QOS_MONITORING (0x0F)\r
- @param ECX CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF (0x01)\r
+ @param EAX CPUID_INTEL_RDT_MONITORING (0x0F)\r
+ @param ECX CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF (0x01)\r
\r
@retval EAX Reserved.\r
@retval EBX Conversion factor from reported IA32_QM_CTR value to occupancy metric (bytes).\r
@retval ECX Maximum range (zero-based) of RMID of this resource type.\r
- @retval EDX L3 Cache QoS Monitoring Capability information described by the\r
- type CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF_EDX.\r
+ @retval EDX L3 Cache Intel RDT Monitoring Capability information described by the\r
+ type CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF_EDX.\r
\r
<b>Example usage</b>\r
@code\r
- UINT32 Ebx;\r
- UINT32 Ecx;\r
- CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF_EDX Edx;\r
+ UINT32 Ebx;\r
+ UINT32 Ecx;\r
+ CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF_EDX Edx;\r
\r
AsmCpuidEx (\r
- CPUID_PLATFORM_QOS_MONITORING, CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF,\r
+ CPUID_INTEL_RDT_MONITORING, CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF,\r
NULL, &Ebx, &Ecx, &Edx.Uint32\r
);\r
@endcode\r
**/\r
-#define CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF 0x01\r
+#define CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF 0x01\r
\r
/**\r
- CPUID Platform QoS Monitoring Information Capability EDX for CPUID leaf\r
- #CPUID_PLATFORM_QOS_MONITORING, sub-leaf\r
- #CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF.\r
+ CPUID L3 Cache Intel RDT Monitoring Capability Information EDX for CPUID leaf\r
+ #CPUID_INTEL_RDT_MONITORING, sub-leaf\r
+ #CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF.\r
**/\r
typedef union {\r
///\r
/// [Bit 0] Supports L3 occupancy monitoring if 1.\r
///\r
UINT32 L3CacheOccupancyMonitoring:1;\r
- UINT32 Reserved:31;\r
+ ///\r
+ /// [Bit 1] Supports L3 Total Bandwidth monitoring if 1.\r
+ ///\r
+ UINT32 L3CacheTotalBandwidthMonitoring:1;\r
+ ///\r
+ /// [Bit 2] Supports L3 Local Bandwidth monitoring if 1.\r
+ ///\r
+ UINT32 L3CacheLocalBandwidthMonitoring:1;\r
+ UINT32 Reserved:29;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
UINT32 Uint32;\r
-} CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF_EDX;\r
+} CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF_EDX;\r
\r
\r
/**\r
- CPUID Platform QoS Enforcement Information\r
+ CPUID Intel Resource Director Technology (Intel RDT) Allocation Information\r
\r
- @param EAX CPUID_PLATFORM_QOS_ENFORCEMENT (0x10).\r
- @param ECX CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF (0x00).\r
- CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF (0x01).\r
- Additional sub leafs 1..n based in RESID from sub leaf 0x00.\r
+ @param EAX CPUID_INTEL_RDT_ALLOCATION (0x10).\r
+ @param ECX CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF (0x00).\r
+ CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF (0x01).\r
+ CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF (0x02).\r
**/\r
-#define CPUID_PLATFORM_QOS_ENFORCEMENT 0x10\r
+#define CPUID_INTEL_RDT_ALLOCATION 0x10\r
\r
/**\r
- CPUID Platform QoS Enforcement Information\r
+ Intel Resource Director Technology (Intel RDT) Allocation Enumeration Sub-leaf\r
\r
- @param EAX CPUID_PLATFORM_QOS_ENFORCEMENT (0x10)\r
- @param ECX CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF (0x00).\r
+ @param EAX CPUID_INTEL_RDT_ALLOCATION (0x10)\r
+ @param ECX CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF (0x00).\r
\r
@retval EAX Reserved.\r
- @retval EBX L3 Cache QoS Enforcement information described by the\r
- type CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF_EBX.\r
+ @retval EBX L3 and L2 Cache Allocation Technology information described by\r
+ the type CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF_EBX.\r
@retval ECX Reserved.\r
@retval EDX Reserved.\r
\r
<b>Example usage</b>\r
@code\r
- CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF_EBX Ebx;\r
+ CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF_EBX Ebx;\r
\r
AsmCpuidEx (\r
- CPUID_PLATFORM_QOS_ENFORCEMENT, CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF,\r
+ CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF,\r
NULL, &Ebx.Uint32, NULL, NULL\r
);\r
@endcode\r
**/\r
-#define CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF 0x00\r
+#define CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF 0x00\r
\r
/**\r
- CPUID Platform QoS Enforcement Information EBX for CPUID leaf\r
- #CPUID_PLATFORM_QOS_ENFORCEMENT, sub-leaf\r
- #CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF.\r
+ CPUID L3 and L2 Cache Allocation Support Information EBX for CPUID leaf\r
+ #CPUID_INTEL_RDT_ALLOCATION, sub-leaf\r
+ #CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF.\r
**/\r
typedef union {\r
///\r
struct {\r
UINT32 Reserved1:1;\r
///\r
- /// [Bit 1] Supports L3 Cache QoS Enforcement if 1.\r
+ /// [Bit 1] Supports L3 Cache Allocation Technology if 1.\r
///\r
- UINT32 L3CacheQosEnforcement:1;\r
- UINT32 Reserved2:30;\r
+ UINT32 L3CacheAllocation:1;\r
+ ///\r
+ /// [Bit 2] Supports L2 Cache Allocation Technology if 1.\r
+ ///\r
+ UINT32 L2CacheAllocation:1;\r
+ ///\r
+ /// [Bit 3] Supports Memory Bandwidth Allocation if 1.\r
+ ///\r
+ UINT32 MemoryBandwidth:1;\r
+ UINT32 Reserved3:28;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
UINT32 Uint32;\r
-} CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF_EBX;\r
+} CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF_EBX;\r
\r
\r
/**\r
- CPUID Platform QoS Enforcement Information\r
+ L3 Cache Allocation Technology Enumeration Sub-leaf\r
\r
- @param EAX CPUID_PLATFORM_QOS_ENFORCEMENT (0x10)\r
- @param ECX CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF (0x00)\r
- Additional sub leafs 1..n based in RESID from sub leaf 0x00.\r
+ @param EAX CPUID_INTEL_RDT_ALLOCATION (0x10)\r
+ @param ECX CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF (0x01)\r
\r
- @retval EAX RESID L3 Cache3 QoS Enforcement information described by the\r
- type CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_EAX.\r
+ @retval EAX RESID L3 Cache Allocation Technology information described by\r
+ the type CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EAX.\r
@retval EBX Bit-granular map of isolation/contention of allocation units.\r
- @retval ECX RESID L3 Cache3 QoS Enforcement information described by the\r
- type CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_ECX.\r
- @retval EDX RESID L3 Cache3 QoS Enforcement information described by the\r
- type CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_EDX.\r
+ @retval ECX RESID L3 Cache Allocation Technology information described by\r
+ the type CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_ECX.\r
+ @retval EDX RESID L3 Cache Allocation Technology information described by\r
+ the type CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EDX.\r
\r
<b>Example usage</b>\r
@code\r
- CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_EAX Eax;\r
+ CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EAX Eax;\r
UINT32 Ebx;\r
- CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_ECX Ecx;\r
- CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_EDX Edx;\r
+ CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_ECX Ecx;\r
+ CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EDX Edx;\r
\r
AsmCpuidEx (\r
- CPUID_PLATFORM_QOS_ENFORCEMENT, CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF,\r
+ CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF,\r
&Eax.Uint32, &Ebx, &Ecx.Uint32, &Edx.Uint32\r
);\r
@endcode\r
**/\r
-#define CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF 0x01\r
+#define CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF 0x01\r
\r
/**\r
- CPUID Platform QoS Enforcement Information EAX for CPUID leaf\r
- #CPUID_PLATFORM_QOS_ENFORCEMENT, sub-leaf\r
- #CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF.\r
+ CPUID L3 Cache Allocation Technology Information EAX for CPUID leaf\r
+ #CPUID_INTEL_RDT_ALLOCATION, sub-leaf\r
+ #CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF.\r
**/\r
typedef union {\r
///\r
///\r
struct {\r
///\r
- /// [Bits 3:0] Length of the capacity bit mask for the corresponding ResID.\r
+ /// [Bits 4:0] Length of the capacity bit mask for the corresponding ResID\r
+ /// using minus-one notation.\r
///\r
- UINT32 CapacityLength:4;\r
- UINT32 Reserved:28;\r
+ UINT32 CapacityLength:5;\r
+ UINT32 Reserved:27;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
UINT32 Uint32;\r
-} CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_EAX;\r
+} CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EAX;\r
\r
/**\r
- CPUID Platform QoS Enforcement Information ECX for CPUID leaf\r
- #CPUID_PLATFORM_QOS_ENFORCEMENT, sub-leaf\r
- #CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF.\r
+ CPUID L3 Cache Allocation Technology Information ECX for CPUID leaf\r
+ #CPUID_INTEL_RDT_ALLOCATION, sub-leaf\r
+ #CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF.\r
**/\r
typedef union {\r
///\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:1;\r
- ///\r
- /// [Bit 1] Updates of COS should be infrequent if 1.\r
- ///\r
- UINT32 CosUpdatesInfrequent:1;\r
+ UINT32 Reserved3:2;\r
///\r
/// [Bit 2] Code and Data Prioritization Technology supported if 1.\r
///\r
/// All bit fields as a 32-bit value\r
///\r
UINT32 Uint32;\r
-} CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_ECX;\r
+} CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_ECX;\r
\r
/**\r
- CPUID Platform QoS Enforcement Information EDX for CPUID leaf\r
- #CPUID_PLATFORM_QOS_ENFORCEMENT, sub-leaf\r
- #CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF.\r
+ CPUID L3 Cache Allocation Technology Information EDX for CPUID leaf\r
+ #CPUID_INTEL_RDT_ALLOCATION, sub-leaf\r
+ #CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF.\r
**/\r
typedef union {\r
///\r
/// All bit fields as a 32-bit value\r
///\r
UINT32 Uint32;\r
-} CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_EDX;\r
+} CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EDX;\r
+\r
+/**\r
+ L2 Cache Allocation Technology Enumeration Sub-leaf\r
+\r
+ @param EAX CPUID_INTEL_RDT_ALLOCATION (0x10)\r
+ @param ECX CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF (0x02)\r
+\r
+ @retval EAX RESID L2 Cache Allocation Technology information described by\r
+ the type CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EAX.\r
+ @retval EBX Bit-granular map of isolation/contention of allocation units.\r
+ @retval ECX Reserved.\r
+ @retval EDX RESID L2 Cache Allocation Technology information described by\r
+ the type CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EDX.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EAX Eax;\r
+ UINT32 Ebx;\r
+ CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EDX Edx;\r
+\r
+ AsmCpuidEx (\r
+ CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF,\r
+ &Eax.Uint32, &Ebx, NULL, &Edx.Uint32\r
+ );\r
+ @endcode\r
+**/\r
+#define CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF 0x02\r
+\r
+/**\r
+ CPUID L2 Cache Allocation Technology Information EAX for CPUID leaf\r
+ #CPUID_INTEL_RDT_ALLOCATION, sub-leaf\r
+ #CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 4:0] Length of the capacity bit mask for the corresponding ResID\r
+ /// using minus-one notation.\r
+ ///\r
+ UINT32 CapacityLength:5;\r
+ UINT32 Reserved:27;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EAX;\r
\r
+/**\r
+ CPUID L2 Cache Allocation Technology Information EDX for CPUID leaf\r
+ #CPUID_INTEL_RDT_ALLOCATION, sub-leaf\r
+ #CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 15:0] Highest COS number supported for this ResID.\r
+ ///\r
+ UINT32 HighestCosNumber:16;\r
+ UINT32 Reserved:16;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EDX;\r
+\r
+/**\r
+ Memory Bandwidth Allocation Enumeration Sub-leaf\r
+\r
+ @param EAX CPUID_INTEL_RDT_ALLOCATION (0x10)\r
+ @param ECX CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF (0x03)\r
+\r
+ @retval EAX RESID memory bandwidth Allocation Technology information\r
+ described by the type\r
+ CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_EAX.\r
+ @retval EBX Reserved.\r
+ @retval ECX RESID memory bandwidth Allocation Technology information\r
+ described by the type\r
+ CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_ECX.\r
+ @retval EDX RESID memory bandwidth Allocation Technology information\r
+ described by the type\r
+ CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_EDX.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_EAX Eax;\r
+ UINT32 Ebx;\r
+ CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_ECX Ecx;\r
+ CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_EDX Edx;\r
+\r
+\r
+ AsmCpuidEx (\r
+ CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF,\r
+ &Eax.Uint32, &Ebx, NULL, &Edx.Uint32\r
+ );\r
+ @endcode\r
+**/\r
+#define CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF 0x03\r
+\r
+/**\r
+ CPUID memory bandwidth Allocation Technology Information EAX for CPUID leaf\r
+ #CPUID_INTEL_RDT_ALLOCATION, sub-leaf\r
+ #CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 11:0] Reports the maximum MBA throttling value supported for\r
+ /// the corresponding ResID using minus-one notation.\r
+ ///\r
+ UINT32 MaximumMBAThrottling:12;\r
+ UINT32 Reserved:20;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_EAX;\r
+\r
+/**\r
+ CPUID memory bandwidth Allocation Technology Information ECX for CPUID leaf\r
+ #CPUID_INTEL_RDT_ALLOCATION, sub-leaf\r
+ #CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 1:0] Reserved.\r
+ ///\r
+ UINT32 Reserved1:2;\r
+ ///\r
+ /// [Bits 3] Reports whether the response of the delay values is linear.\r
+ ///\r
+ UINT32 Liner:1;\r
+ UINT32 Reserved2:29;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_ECX;\r
+\r
+/**\r
+ CPUID memory bandwidth Allocation Technology Information EDX for CPUID leaf\r
+ #CPUID_INTEL_RDT_ALLOCATION, sub-leaf\r
+ #CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 15:0] Highest COS number supported for this ResID.\r
+ ///\r
+ UINT32 HighestCosNumber:16;\r
+ UINT32 Reserved:16;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_EDX;\r
\r
/**\r
Intel SGX resource capability and configuration.\r
/// [Bit 1] If 1, indicates leaf functions of SGX2 instruction are supported.\r
///\r
UINT32 SGX2:1;\r
- UINT32 Reserved:30;\r
+ UINT32 Reserved1:3;\r
+ ///\r
+ /// [Bit 5] If 1, indicates Intel SGX supports ENCLV instruction leaves\r
+ /// EINCVIRTCHILD, EDECVIRTCHILD, and ESETCONTEXT.\r
+ ///\r
+ UINT32 ENCLV:1;\r
+ ///\r
+ /// [Bit 6] If 1, indicates Intel SGX supports ENCLS instruction leaves ETRACKC,\r
+ /// ERDINFO, ELDBC, and ELDUC.\r
+ ///\r
+ UINT32 ENCLS:1;\r
+ UINT32 Reserved2:25;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
struct {\r
///\r
- /// [Bit 0] If 1, Indicates that IA32_RTIT_CTL.CR3Filter can be set to 1,\r
+ /// [Bit 0] If 1, indicates that IA32_RTIT_CTL.CR3Filter can be set to 1,\r
/// and that IA32_RTIT_CR3_MATCH MSR can be accessed.\r
///\r
UINT32 Cr3Filter:1;\r
///\r
- /// [Bit 1] If 1, Indicates support of Configurable PSB and Cycle-Accurate\r
+ /// [Bit 1] If 1, indicates support of Configurable PSB and Cycle-Accurate\r
/// Mode.\r
///\r
UINT32 ConfigurablePsb:1;\r
///\r
- /// [Bit 2] If 1, Indicates support of IP Filtering, TraceStop filtering,\r
+ /// [Bit 2] If 1, indicates support of IP Filtering, TraceStop filtering,\r
/// and preservation of Intel PT MSRs across warm reset.\r
///\r
UINT32 IpTraceStopFiltering:1;\r
///\r
- /// [Bit 3] If 1, Indicates support of MTC timing packet and suppression of\r
+ /// [Bit 3] If 1, indicates support of MTC timing packet and suppression of\r
/// COFI-based packets.\r
///\r
UINT32 Mtc:1;\r
- UINT32 Reserved:28;\r
+ ///\r
+ /// [Bit 4] If 1, indicates support of PTWRITE. Writes can set\r
+ /// IA32_RTIT_CTL[12] (PTWEn) and IA32_RTIT_CTL[5] (FUPonPTW), and PTWRITE\r
+ /// can generate packets.\r
+ ///\r
+ UINT32 PTWrite:1;\r
+ ///\r
+ /// [Bit 5] If 1, indicates support of Power Event Trace. Writes can set\r
+ /// IA32_RTIT_CTL[4] (PwrEvtEn), enabling Power Event Trace packet\r
+ /// generation.\r
+ ///\r
+ UINT32 PowerEventTrace:1;\r
+ UINT32 Reserved:26;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
UINT32 ToPA:1;\r
///\r
- /// [Bit 2] If 1, Indicates support of Single-Range Output scheme.\r
+ /// [Bit 2] If 1, indicates support of Single-Range Output scheme.\r
///\r
UINT32 SingleRangeOutput:1;\r
///\r
- /// [Bit 3] If 1, Indicates support of output to Trace Transport subsystem.\r
+ /// [Bit 3] If 1, indicates support of output to Trace Transport subsystem.\r
///\r
UINT32 TraceTransportSubsystem:1;\r
UINT32 Reserved:27;\r
///\r
- /// [Bit 31] If 1, Generated packets which contain IP payloads have LIP\r
+ /// [Bit 31] If 1, generated packets which contain IP payloads have LIP\r
/// values, which include the CS base component.\r
///\r
UINT32 LIP:1;\r
\r
\r
/**\r
- CPUID Time Stamp Counter Information\r
+ CPUID Time Stamp Counter and Nominal Core Crystal Clock Information\r
\r
@note\r
If EBX[31:0] is 0, the TSC/"core crystal clock" ratio is not enumerated.\r
EBX[31:0]/EAX[31:0] indicates the ratio of the TSC frequency and the core\r
crystal clock frequency.\r
- "TSC frequency" = "core crystal clock frequency" * EBX/EAX.\r
+ If ECX is 0, the nominal core crystal clock frequency is not enumerated.\r
+ "TSC frequency" = "core crystal clock frequency" * EBX/EAX.\r
The core crystal clock may differ from the reference clock, bus clock, or core\r
clock frequencies.\r
\r
TSC/"core crystal clock" ratio\r
@retval EBX An unsigned integer which is the numerator of the\r
TSC/"core crystal clock" ratio.\r
- @retval ECX Reserved.\r
+ @retval ECX An unsigned integer which is the nominal frequency\r
+ of the core crystal clock in Hz.\r
@retval EDX Reserved.\r
\r
<b>Example usage</b>\r
@code\r
UINT32 Eax;\r
UINT32 Ebx;\r
+ UINT32 Ecx;\r
\r
- AsmCpuid (CPUID_TIME_STAMP_COUNTER, &Eax, &Ebx, NULL, NULL);\r
+ AsmCpuid (CPUID_TIME_STAMP_COUNTER, &Eax, &Ebx, &Ecx, NULL);\r
@endcode\r
**/\r
#define CPUID_TIME_STAMP_COUNTER 0x15\r
**/\r
#define CPUID_SOC_VENDOR_BRAND_STRING3 0x03\r
\r
+/**\r
+ CPUID Deterministic Address Translation Parameters\r
+\r
+ @note\r
+ Each sub-leaf enumerates a different address translation structure.\r
+ If ECX contains an invalid sub-leaf index, EAX/EBX/ECX/EDX return 0. Sub-leaf\r
+ index n is invalid if n exceeds the value that sub-leaf 0 returns in EAX. A\r
+ sub-leaf index is also invalid if EDX[4:0] returns 0.\r
+ Valid sub-leaves do not need to be contiguous or in any particular order. A\r
+ valid sub-leaf may be in a higher input ECX value than an invalid sub-leaf or\r
+ than a valid sub-leaf of a higher or lower-level structure.\r
+ * Some unified TLBs will allow a single TLB entry to satisfy data read/write\r
+ and instruction fetches. Others will require separate entries (e.g., one\r
+ loaded on data read/write and another loaded on an instruction fetch).\r
+ Please see the Intel 64 and IA-32 Architectures Optimization Reference Manual\r
+ for details of a particular product.\r
+ ** Add one to the return value to get the result.\r
+\r
+ @param EAX CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS (0x18)\r
+ @param ECX CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_MAIN_LEAF (0x00)\r
+ CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_SUB_LEAF (0x*)\r
+\r
+**/\r
+#define CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS 0x18\r
+\r
+/**\r
+ CPUID Deterministic Address Translation Parameters\r
+\r
+ @param EAX CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS (0x18)\r
+ @param ECX CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_MAIN_LEAF (0x00)\r
+\r
+ @retval EAX Reports the maximum input value of supported sub-leaf in leaf 18H.\r
+ @retval EBX Returns Deterministic Address Translation Parameters described by\r
+ the type CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_EBX.\r
+ @retval ECX Number of Sets.\r
+ @retval EDX Returns Deterministic Address Translation Parameters described by\r
+ the type CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_EDX.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT32 Eax;\r
+ CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_EBX Ebx;\r
+ UINT32 Ecx;\r
+ CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_EDX Edx;\r
+\r
+ AsmCpuidEx (\r
+ CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS,\r
+ CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_MAIN_LEAF,\r
+ &Eax, &Ebx.Uint32, &Ecx, &Edx.Uint32\r
+ );\r
+ @endcode\r
+**/\r
+#define CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_MAIN_LEAF 0x00\r
+\r
+/**\r
+ CPUID Deterministic Address Translation Parameters EBX for CPUID leafs.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 0] 4K page size entries supported by this structure.\r
+ ///\r
+ UINT32 Page4K:1;\r
+ ///\r
+ /// [Bits 1] 2MB page size entries supported by this structure.\r
+ ///\r
+ UINT32 Page2M:1;\r
+ ///\r
+ /// [Bits 2] 4MB page size entries supported by this structure.\r
+ ///\r
+ UINT32 Page4M:1;\r
+ ///\r
+ /// [Bits 3] 1 GB page size entries supported by this structure.\r
+ ///\r
+ UINT32 Page1G:1;\r
+ ///\r
+ /// [Bits 7:4] Reserved.\r
+ ///\r
+ UINT32 Reserved1:4;\r
+ ///\r
+ /// [Bits 10:8] Partitioning (0: Soft partitioning between the logical\r
+ /// processors sharing this structure)\r
+ ///\r
+ UINT32 Partitioning:3;\r
+ ///\r
+ /// [Bits 15:11] Reserved.\r
+ ///\r
+ UINT32 Reserved2:5;\r
+ ///\r
+ /// [Bits 31:16] W = Ways of associativity.\r
+ ///\r
+ UINT32 Way:16;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_EBX;\r
+\r
+/**\r
+ CPUID Deterministic Address Translation Parameters EDX for CPUID leafs.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 4:0] Translation cache type field.\r
+ ///\r
+ UINT32 TranslationCacheType:5;\r
+ ///\r
+ /// [Bits 7:5] Translation cache level (starts at 1).\r
+ ///\r
+ UINT32 TranslationCacheLevel:3;\r
+ ///\r
+ /// [Bits 8] Fully associative structure.\r
+ ///\r
+ UINT32 FullyAssociative:1;\r
+ ///\r
+ /// [Bits 13:9] Reserved.\r
+ ///\r
+ UINT32 Reserved1:5;\r
+ ///\r
+ /// [Bits 25:14] Maximum number of addressable IDs for logical\r
+ /// processors sharing this translation cache.\r
+ ///\r
+ UINT32 MaximumNum:12;\r
+ ///\r
+ /// [Bits 31:26] Reserved.\r
+ ///\r
+ UINT32 Reserved2:6;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_EDX;\r
+\r
+///\r
+/// @{ Define value for CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_EDX.TranslationCacheType\r
+///\r
+#define CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_TRANSLATION_CACHE_TYPE_INVALID 0x00\r
+#define CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_TRANSLATION_CACHE_TYPE_DATA_TLB 0x01\r
+#define CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_TRANSLATION_CACHE_TYPE_INSTRUCTION_TLB 0x02\r
+#define CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_TRANSLATION_CACHE_TYPE_UNIFIED_TLB 0x03\r
+///\r
+/// @}\r
+///\r
+\r
+\r
+/**\r
+ CPUID V2 Extended Topology Enumeration Leaf\r
+\r
+ @note\r
+ CPUID leaf 1FH is a preferred superset to leaf 0BH. Intel recommends first checking\r
+ for the existence of Leaf 1FH and using this if available.\r
+ Most of Leaf 1FH output depends on the initial value in ECX. The EDX output of leaf\r
+ 1FH is always valid and does not vary with input value in ECX. Output value in ECX[7:0]\r
+ always equals input value in ECX[7:0]. Sub-leaf index 0 enumerates SMT level. Each\r
+ subsequent higher sub-leaf index enumerates a higher-level topological entity in\r
+ hierarchical order. For sub-leaves that return an invalid level-type of 0 in ECX[15:8];\r
+ EAX and EBX will return 0. If an input value n in ECX returns the invalid level-type of\r
+ 0 in ECX[15:8], other input values with ECX > n also return 0 in ECX[15:8].\r
+\r
+ Software should use this field (EAX[4:0]) to enumerate processor topology of the system.\r
+ Software must not use EBX[15:0] to enumerate processor topology of the system. This value\r
+ in this field (EBX[15:0]) is only intended for display/diagnostic purposes. The actual\r
+ number of logical processors available to BIOS/OS/Applications may be different from the\r
+ value of EBX[15:0], depending on software and platform hardware configurations.\r
+\r
+ @param EAX CPUID_V2_EXTENDED_TOPOLOGY (0x1F)\r
+ @param ECX Level number\r
+\r
+**/\r
+#define CPUID_V2_EXTENDED_TOPOLOGY 0x1F\r
+\r
+///\r
+/// @{ Define value for CPUID_EXTENDED_TOPOLOGY_ECX.LevelType\r
+/// The value of the "level type" field is not related to level numbers in\r
+/// any way, higher "level type" values do not mean higher levels.\r
+///\r
+#define CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_MODULE 0x03\r
+#define CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_TILE 0x04\r
+#define CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE 0x05\r
+///\r
+/// @}\r
+///\r
\r
/**\r
CPUID Extended Function\r
#define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_4_WAY 0x04\r
#define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_8_WAY 0x06\r
#define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_16_WAY 0x08\r
+#define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_32_WAY 0x0A\r
+#define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_48_WAY 0x0B\r
+#define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_64_WAY 0x0C\r
+#define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_96_WAY 0x0D\r
+#define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_128_WAY 0x0E\r
#define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_FULL 0x0F\r
///\r
/// @}\r
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