//\r
// Definition for Local APIC registers and related values\r
//\r
-#define XAPIC_ID_OFFSET 0x0\r
+#define XAPIC_ID_OFFSET 0x20\r
+#define XAPIC_VERSION_OFFSET 0x30\r
#define XAPIC_EOI_OFFSET 0x0b0\r
#define XAPIC_ICR_DFR_OFFSET 0x0e0\r
#define XAPIC_SPURIOUS_VECTOR_OFFSET 0x0f0\r
#define XAPIC_ICR_LOW_OFFSET 0x300\r
#define XAPIC_ICR_HIGH_OFFSET 0x310\r
#define XAPIC_LVT_TIMER_OFFSET 0x320\r
-#define XAPIC_LINT0_VECTOR_OFFSET 0x350\r
-#define XAPIC_LINT1_VECTOR_OFFSET 0x360\r
+#define XAPIC_LVT_LINT0_OFFSET 0x350\r
+#define XAPIC_LVT_LINT1_OFFSET 0x360\r
#define XAPIC_TIMER_INIT_COUNT_OFFSET 0x380\r
#define XAPIC_TIMER_CURRENT_COUNT_OFFSET 0x390\r
#define XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET 0x3E0\r
UINT64 Uint64;\r
} MSR_IA32_APIC_BASE;\r
\r
+//\r
+// Local APIC Version Register.\r
+//\r
+typedef union {\r
+ struct {\r
+ UINT32 Version:8; ///< The version numbers of the local APIC.\r
+ UINT32 Reserved0:8; ///< Reserved.\r
+ UINT32 MaxLvtEntry:8; ///< Number of LVT entries minus 1.\r
+ UINT32 EoiBroadcastSuppression:1; ///< 1 if EOI-broadcast suppression supported.\r
+ UINT32 Reserved1:7; ///< Reserved.\r
+ } Bits;\r
+ UINT32 Uint32;\r
+} LOCAL_APIC_VERSION;\r
+\r
//\r
// Low half of Interrupt Command Register (ICR).\r
//\r