\r
This local APIC library instance supports xAPIC mode only.\r
\r
- Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
\r
**/\r
\r
+#include <Register/Cpuid.h>\r
+#include <Register/Msr.h>\r
#include <Register/LocalApic.h>\r
\r
#include <Library/BaseLib.h>\r
VOID\r
)\r
{\r
- MSR_IA32_APIC_BASE ApicBaseMsr;\r
+ MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr;\r
\r
if (!LocalApicBaseAddressMsrSupported ()) {\r
//\r
return PcdGet32 (PcdCpuLocalApicBaseAddress);\r
}\r
\r
- ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS);\r
+ ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);\r
\r
- return (UINTN)(LShiftU64 ((UINT64) ApicBaseMsr.Bits.ApicBaseHigh, 32)) +\r
- (((UINTN)ApicBaseMsr.Bits.ApicBaseLow) << 12);\r
+ return (UINTN)(LShiftU64 ((UINT64) ApicBaseMsr.Bits.ApicBaseHi, 32)) +\r
+ (((UINTN)ApicBaseMsr.Bits.ApicBase) << 12);\r
}\r
\r
/**\r
IN UINTN BaseAddress\r
)\r
{\r
- MSR_IA32_APIC_BASE ApicBaseMsr;\r
+ MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr;\r
\r
ASSERT ((BaseAddress & (SIZE_4KB - 1)) == 0);\r
\r
return;\r
}\r
\r
- ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS);\r
+ ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);\r
\r
- ApicBaseMsr.Bits.ApicBaseLow = (UINT32) (BaseAddress >> 12);\r
- ApicBaseMsr.Bits.ApicBaseHigh = (UINT32) (RShiftU64((UINT64) BaseAddress, 32));\r
+ ApicBaseMsr.Bits.ApicBase = (UINT32) (BaseAddress >> 12);\r
+ ApicBaseMsr.Bits.ApicBaseHi = (UINT32) (RShiftU64((UINT64) BaseAddress, 32));\r
\r
- AsmWriteMsr64 (MSR_IA32_APIC_BASE_ADDRESS, ApicBaseMsr.Uint64);\r
+ AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64);\r
}\r
\r
/**\r
{\r
DEBUG_CODE (\r
{\r
- MSR_IA32_APIC_BASE ApicBaseMsr;\r
+ MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr;\r
\r
//\r
// Check to see if the CPU supports the APIC Base Address MSR \r
//\r
if (LocalApicBaseAddressMsrSupported ()) {\r
- ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS);\r
+ ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);\r
//\r
// Local APIC should have been enabled\r
//\r
- ASSERT (ApicBaseMsr.Bits.En != 0);\r
- ASSERT (ApicBaseMsr.Bits.Extd == 0);\r
+ ASSERT (ApicBaseMsr.Bits.EN != 0);\r
+ ASSERT (ApicBaseMsr.Bits.EXTD == 0);\r
}\r
}\r
);\r
SendIpi (IcrLow.Uint32, 0);\r
}\r
\r
+/**\r
+ Initialize the state of the SoftwareEnable bit in the Local APIC\r
+ Spurious Interrupt Vector register.\r
+\r
+ @param Enable If TRUE, then set SoftwareEnable to 1\r
+ If FALSE, then set SoftwareEnable to 0.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+InitializeLocalApicSoftwareEnable (\r
+ IN BOOLEAN Enable\r
+ )\r
+{\r
+ LOCAL_APIC_SVR Svr;\r
+\r
+ //\r
+ // Set local APIC software-enabled bit.\r
+ //\r
+ Svr.Uint32 = ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET);\r
+ if (Enable) {\r
+ if (Svr.Bits.SoftwareEnable == 0) {\r
+ Svr.Bits.SoftwareEnable = 1;\r
+ WriteLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET, Svr.Uint32);\r
+ }\r
+ } else {\r
+ if (Svr.Bits.SoftwareEnable == 1) {\r
+ Svr.Bits.SoftwareEnable = 0;\r
+ WriteLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET, Svr.Uint32);\r
+ }\r
+ }\r
+}\r
+\r
/**\r
Programming Virtual Wire Mode.\r
\r
IN UINT8 Vector\r
)\r
{\r
- LOCAL_APIC_SVR Svr;\r
LOCAL_APIC_DCR Dcr;\r
LOCAL_APIC_LVT_TIMER LvtTimer;\r
UINT32 Divisor;\r
//\r
// Ensure local APIC is in software-enabled state.\r
//\r
- Svr.Uint32 = ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET);\r
- Svr.Bits.SoftwareEnable = 1;\r
- WriteLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET, Svr.Uint32);\r
+ InitializeLocalApicSoftwareEnable (TRUE);\r
\r
//\r
// Program init-count register.\r
/**\r
Get the state of the local APIC timer.\r
\r
+ This function will ASSERT if the local APIC is not software enabled.\r
+\r
@param DivideValue Return the divide value for the DCR. It is one of 1,2,4,8,16,32,64,128.\r
@param PeriodicMode Return the timer mode. If TRUE, timer mode is peridoic. Othewise, timer mode is one-shot.\r
@param Vector Return the timer interrupt vector number.\r
LOCAL_APIC_DCR Dcr;\r
LOCAL_APIC_LVT_TIMER LvtTimer;\r
\r
+ //\r
+ // Check the APIC Software Enable/Disable bit (bit 8) in Spurious-Interrupt\r
+ // Vector Register.\r
+ // This bit will be 1, if local APIC is software enabled.\r
+ //\r
+ ASSERT ((ReadLocalApicReg(XAPIC_SPURIOUS_VECTOR_OFFSET) & BIT8) != 0);\r
+\r
if (DivideValue != NULL) {\r
Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET);\r
Divisor = Dcr.Bits.DivideValue1 | (Dcr.Bits.DivideValue2 << 2);\r
}\r
return MsiData.Uint64;\r
}\r
+\r
+/**\r
+ Get Package ID/Core ID/Thread ID of a processor.\r
+\r
+ The algorithm assumes the target system has symmetry across physical\r
+ package boundaries with respect to the number of logical processors\r
+ per package, number of cores per package.\r
+\r
+ @param[in] InitialApicId Initial APIC ID of the target logical processor.\r
+ @param[out] Package Returns the processor package ID.\r
+ @param[out] Core Returns the processor core ID.\r
+ @param[out] Thread Returns the processor thread ID.\r
+**/\r
+VOID\r
+GetProcessorLocation(\r
+ IN UINT32 InitialApicId,\r
+ OUT UINT32 *Package OPTIONAL,\r
+ OUT UINT32 *Core OPTIONAL,\r
+ OUT UINT32 *Thread OPTIONAL\r
+ )\r
+{\r
+ BOOLEAN TopologyLeafSupported;\r
+ UINTN ThreadBits;\r
+ UINTN CoreBits;\r
+ CPUID_VERSION_INFO_EBX VersionInfoEbx;\r
+ CPUID_VERSION_INFO_EDX VersionInfoEdx;\r
+ CPUID_CACHE_PARAMS_EAX CacheParamsEax;\r
+ CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax;\r
+ CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx;\r
+ CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx;\r
+ UINT32 MaxCpuIdIndex;\r
+ UINT32 SubIndex;\r
+ UINTN LevelType;\r
+ UINT32 MaxLogicProcessorsPerPackage;\r
+ UINT32 MaxCoresPerPackage;\r
+\r
+ //\r
+ // Check if the processor is capable of supporting more than one logical processor.\r
+ //\r
+ AsmCpuid(CPUID_VERSION_INFO, NULL, NULL, NULL, &VersionInfoEdx.Uint32);\r
+ if (VersionInfoEdx.Bits.HTT == 0) {\r
+ if (Thread != NULL) {\r
+ *Thread = 0;\r
+ }\r
+ if (Core != NULL) {\r
+ *Core = 0;\r
+ }\r
+ if (Package != NULL) {\r
+ *Package = 0;\r
+ }\r
+ return;\r
+ }\r
+\r
+ ThreadBits = 0;\r
+ CoreBits = 0;\r
+\r
+ //\r
+ // Assume three-level mapping of APIC ID: Package:Core:SMT.\r
+ //\r
+ TopologyLeafSupported = FALSE;\r
+\r
+ //\r
+ // Get the max index of basic CPUID\r
+ //\r
+ AsmCpuid(CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);\r
+\r
+ //\r
+ // If the extended topology enumeration leaf is available, it\r
+ // is the preferred mechanism for enumerating topology.\r
+ //\r
+ if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {\r
+ AsmCpuidEx(\r
+ CPUID_EXTENDED_TOPOLOGY,\r
+ 0,\r
+ &ExtendedTopologyEax.Uint32,\r
+ &ExtendedTopologyEbx.Uint32,\r
+ &ExtendedTopologyEcx.Uint32,\r
+ NULL\r
+ );\r
+ //\r
+ // If CPUID.(EAX=0BH, ECX=0H):EBX returns zero and maximum input value for\r
+ // basic CPUID information is greater than 0BH, then CPUID.0BH leaf is not\r
+ // supported on that processor.\r
+ //\r
+ if (ExtendedTopologyEbx.Uint32 != 0) {\r
+ TopologyLeafSupported = TRUE;\r
+\r
+ //\r
+ // Sub-leaf index 0 (ECX= 0 as input) provides enumeration parameters to extract\r
+ // the SMT sub-field of x2APIC ID.\r
+ //\r
+ LevelType = ExtendedTopologyEcx.Bits.LevelType;\r
+ ASSERT(LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT);\r
+ ThreadBits = ExtendedTopologyEax.Bits.ApicIdShift;\r
+\r
+ //\r
+ // Software must not assume any "level type" encoding\r
+ // value to be related to any sub-leaf index, except sub-leaf 0.\r
+ //\r
+ SubIndex = 1;\r
+ do {\r
+ AsmCpuidEx(\r
+ CPUID_EXTENDED_TOPOLOGY,\r
+ SubIndex,\r
+ &ExtendedTopologyEax.Uint32,\r
+ NULL,\r
+ &ExtendedTopologyEcx.Uint32,\r
+ NULL\r
+ );\r
+ LevelType = ExtendedTopologyEcx.Bits.LevelType;\r
+ if (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) {\r
+ CoreBits = ExtendedTopologyEax.Bits.ApicIdShift - ThreadBits;\r
+ break;\r
+ }\r
+ SubIndex++;\r
+ } while (LevelType != CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);\r
+ }\r
+ }\r
+\r
+ if (!TopologyLeafSupported) {\r
+ AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL);\r
+ MaxLogicProcessorsPerPackage = VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;\r
+ if (MaxCpuIdIndex >= CPUID_CACHE_PARAMS) {\r
+ AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL, NULL);\r
+ MaxCoresPerPackage = CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1;\r
+ }\r
+ else {\r
+ //\r
+ // Must be a single-core processor.\r
+ //\r
+ MaxCoresPerPackage = 1;\r
+ }\r
+\r
+ ThreadBits = (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1);\r
+ CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1); }\r
+\r
+ if (Thread != NULL) {\r
+ *Thread = InitialApicId & ((1 << ThreadBits) - 1);\r
+ }\r
+ if (Core != NULL) {\r
+ *Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);\r
+ }\r
+ if (Package != NULL) {\r
+ *Package = (InitialApicId >> (ThreadBits + CoreBits));\r
+ }\r
+}\r
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