\r
AsmCpuid (1, &RegEax, NULL, NULL, NULL);\r
FamilyId = BitFieldRead32 (RegEax, 8, 11);\r
- if (FamilyId == 0x04 || FamilyId == 0x05) {\r
+ if ((FamilyId == 0x04) || (FamilyId == 0x05)) {\r
//\r
// CPUs with a FamilyId of 0x04 or 0x05 do not support the\r
// Local APIC Base Address MSR\r
//\r
return FALSE;\r
}\r
+\r
return TRUE;\r
}\r
\r
\r
ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);\r
\r
- return (UINTN)(LShiftU64 ((UINT64) ApicBaseMsr.Bits.ApicBaseHi, 32)) +\r
- (((UINTN)ApicBaseMsr.Bits.ApicBase) << 12);\r
+ return (UINTN)(LShiftU64 ((UINT64)ApicBaseMsr.Bits.ApicBaseHi, 32)) +\r
+ (((UINTN)ApicBaseMsr.Bits.ApicBase) << 12);\r
}\r
\r
/**\r
VOID\r
EFIAPI\r
SetLocalApicBaseAddress (\r
- IN UINTN BaseAddress\r
+ IN UINTN BaseAddress\r
)\r
{\r
MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr;\r
\r
ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);\r
\r
- ApicBaseMsr.Bits.ApicBase = (UINT32) (BaseAddress >> 12);\r
- ApicBaseMsr.Bits.ApicBaseHi = (UINT32) (RShiftU64((UINT64) BaseAddress, 32));\r
+ ApicBaseMsr.Bits.ApicBase = (UINT32)(BaseAddress >> 12);\r
+ ApicBaseMsr.Bits.ApicBaseHi = (UINT32)(RShiftU64 ((UINT64)BaseAddress, 32));\r
\r
AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64);\r
}\r
IN UINTN MmioOffset\r
)\r
{\r
- UINT32 MsrIndex;\r
+ UINT32 MsrIndex;\r
\r
ASSERT ((MmioOffset & 0xf) == 0);\r
\r
if (GetApicMode () == LOCAL_APIC_MODE_XAPIC) {\r
- return MmioRead32 (GetLocalApicBaseAddress() + MmioOffset);\r
+ return MmioRead32 (GetLocalApicBaseAddress () + MmioOffset);\r
} else {\r
//\r
// DFR is not supported in x2APIC mode.\r
VOID\r
EFIAPI\r
WriteLocalApicReg (\r
- IN UINTN MmioOffset,\r
- IN UINT32 Value\r
+ IN UINTN MmioOffset,\r
+ IN UINT32 Value\r
)\r
{\r
- UINT32 MsrIndex;\r
+ UINT32 MsrIndex;\r
\r
ASSERT ((MmioOffset & 0xf) == 0);\r
\r
if (GetApicMode () == LOCAL_APIC_MODE_XAPIC) {\r
- MmioWrite32 (GetLocalApicBaseAddress() + MmioOffset, Value);\r
+ MmioWrite32 (GetLocalApicBaseAddress () + MmioOffset, Value);\r
} else {\r
//\r
// DFR is not supported in x2APIC mode.\r
**/\r
VOID\r
SendIpi (\r
- IN UINT32 IcrLow,\r
- IN UINT32 ApicId\r
+ IN UINT32 IcrLow,\r
+ IN UINT32 ApicId\r
)\r
{\r
- UINT64 MsrValue;\r
- LOCAL_APIC_ICR_LOW IcrLowReg;\r
- UINTN LocalApciBaseAddress;\r
- UINT32 IcrHigh;\r
- BOOLEAN InterruptState;\r
+ UINT64 MsrValue;\r
+ LOCAL_APIC_ICR_LOW IcrLowReg;\r
+ UINTN LocalApciBaseAddress;\r
+ UINT32 IcrHigh;\r
+ BOOLEAN InterruptState;\r
\r
//\r
// Legacy APIC or X2APIC?\r
//\r
// Get base address of this LAPIC\r
//\r
- LocalApciBaseAddress = GetLocalApicBaseAddress();\r
+ LocalApciBaseAddress = GetLocalApicBaseAddress ();\r
\r
//\r
// Save existing contents of ICR high 32 bits\r
MmioWrite32 (LocalApciBaseAddress + XAPIC_ICR_HIGH_OFFSET, IcrHigh);\r
\r
SetInterruptState (InterruptState);\r
-\r
} else {\r
//\r
// For x2APIC, A single MSR write to the Interrupt Command Register is required for dispatching an\r
// interrupt in x2APIC mode.\r
//\r
- MsrValue = LShiftU64 ((UINT64) ApicId, 32) | IcrLow;\r
+ MsrValue = LShiftU64 ((UINT64)ApicId, 32) | IcrLow;\r
AsmWriteMsr64 (X2APIC_MSR_ICR_ADDRESS, MsrValue);\r
}\r
}\r
case LOCAL_APIC_MODE_XAPIC:\r
break;\r
case LOCAL_APIC_MODE_X2APIC:\r
- ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);\r
+ ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);\r
ApicBaseMsr.Bits.EXTD = 1;\r
AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64);\r
break;\r
// Transition from x2APIC mode to xAPIC mode is a two-step process:\r
// x2APIC -> Local APIC disabled -> xAPIC\r
//\r
- ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);\r
+ ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);\r
ApicBaseMsr.Bits.EXTD = 0;\r
- ApicBaseMsr.Bits.EN = 0;\r
+ ApicBaseMsr.Bits.EN = 0;\r
AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64);\r
ApicBaseMsr.Bits.EN = 1;\r
AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64);\r
VOID\r
)\r
{\r
- UINT32 ApicId;\r
- UINT32 MaxCpuIdIndex;\r
- UINT32 RegEbx;\r
+ UINT32 ApicId;\r
+ UINT32 MaxCpuIdIndex;\r
+ UINT32 RegEbx;\r
\r
if (GetApicMode () == LOCAL_APIC_MODE_XAPIC) {\r
//\r
return ApicId;\r
}\r
}\r
+\r
AsmCpuid (CPUID_VERSION_INFO, NULL, &RegEbx, NULL, NULL);\r
return RegEbx >> 24;\r
} else {\r
VOID\r
)\r
{\r
- UINT32 ApicId;\r
- UINT32 InitApicId;\r
+ UINT32 ApicId;\r
+ UINT32 InitApicId;\r
\r
ApicId = ReadLocalApicReg (XAPIC_ID_OFFSET);\r
if (GetApicMode () == LOCAL_APIC_MODE_XAPIC) {\r
VOID\r
EFIAPI\r
SendFixedIpi (\r
- IN UINT32 ApicId,\r
- IN UINT8 Vector\r
+ IN UINT32 ApicId,\r
+ IN UINT8 Vector\r
)\r
{\r
- LOCAL_APIC_ICR_LOW IcrLow;\r
+ LOCAL_APIC_ICR_LOW IcrLow;\r
\r
- IcrLow.Uint32 = 0;\r
+ IcrLow.Uint32 = 0;\r
IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_FIXED;\r
- IcrLow.Bits.Level = 1;\r
- IcrLow.Bits.Vector = Vector;\r
+ IcrLow.Bits.Level = 1;\r
+ IcrLow.Bits.Vector = Vector;\r
SendIpi (IcrLow.Uint32, ApicId);\r
}\r
\r
VOID\r
EFIAPI\r
SendFixedIpiAllExcludingSelf (\r
- IN UINT8 Vector\r
+ IN UINT8 Vector\r
)\r
{\r
- LOCAL_APIC_ICR_LOW IcrLow;\r
+ LOCAL_APIC_ICR_LOW IcrLow;\r
\r
- IcrLow.Uint32 = 0;\r
- IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_FIXED;\r
- IcrLow.Bits.Level = 1;\r
+ IcrLow.Uint32 = 0;\r
+ IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_FIXED;\r
+ IcrLow.Bits.Level = 1;\r
IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;\r
- IcrLow.Bits.Vector = Vector;\r
+ IcrLow.Bits.Vector = Vector;\r
SendIpi (IcrLow.Uint32, 0);\r
}\r
\r
VOID\r
EFIAPI\r
SendSmiIpi (\r
- IN UINT32 ApicId\r
+ IN UINT32 ApicId\r
)\r
{\r
- LOCAL_APIC_ICR_LOW IcrLow;\r
+ LOCAL_APIC_ICR_LOW IcrLow;\r
\r
- IcrLow.Uint32 = 0;\r
+ IcrLow.Uint32 = 0;\r
IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_SMI;\r
- IcrLow.Bits.Level = 1;\r
+ IcrLow.Bits.Level = 1;\r
SendIpi (IcrLow.Uint32, ApicId);\r
}\r
\r
VOID\r
)\r
{\r
- LOCAL_APIC_ICR_LOW IcrLow;\r
+ LOCAL_APIC_ICR_LOW IcrLow;\r
\r
- IcrLow.Uint32 = 0;\r
- IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_SMI;\r
- IcrLow.Bits.Level = 1;\r
+ IcrLow.Uint32 = 0;\r
+ IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_SMI;\r
+ IcrLow.Bits.Level = 1;\r
IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;\r
SendIpi (IcrLow.Uint32, 0);\r
}\r
VOID\r
EFIAPI\r
SendInitIpi (\r
- IN UINT32 ApicId\r
+ IN UINT32 ApicId\r
)\r
{\r
- LOCAL_APIC_ICR_LOW IcrLow;\r
+ LOCAL_APIC_ICR_LOW IcrLow;\r
\r
- IcrLow.Uint32 = 0;\r
+ IcrLow.Uint32 = 0;\r
IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_INIT;\r
- IcrLow.Bits.Level = 1;\r
+ IcrLow.Bits.Level = 1;\r
SendIpi (IcrLow.Uint32, ApicId);\r
}\r
\r
VOID\r
)\r
{\r
- LOCAL_APIC_ICR_LOW IcrLow;\r
+ LOCAL_APIC_ICR_LOW IcrLow;\r
\r
- IcrLow.Uint32 = 0;\r
- IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_INIT;\r
- IcrLow.Bits.Level = 1;\r
+ IcrLow.Uint32 = 0;\r
+ IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_INIT;\r
+ IcrLow.Bits.Level = 1;\r
IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;\r
SendIpi (IcrLow.Uint32, 0);\r
}\r
VOID\r
EFIAPI\r
SendInitSipiSipi (\r
- IN UINT32 ApicId,\r
- IN UINT32 StartupRoutine\r
+ IN UINT32 ApicId,\r
+ IN UINT32 StartupRoutine\r
)\r
{\r
- LOCAL_APIC_ICR_LOW IcrLow;\r
+ LOCAL_APIC_ICR_LOW IcrLow;\r
\r
ASSERT (StartupRoutine < 0x100000);\r
ASSERT ((StartupRoutine & 0xfff) == 0);\r
\r
SendInitIpi (ApicId);\r
- MicroSecondDelay (PcdGet32(PcdCpuInitIpiDelayInMicroSeconds));\r
- IcrLow.Uint32 = 0;\r
- IcrLow.Bits.Vector = (StartupRoutine >> 12);\r
+ MicroSecondDelay (PcdGet32 (PcdCpuInitIpiDelayInMicroSeconds));\r
+ IcrLow.Uint32 = 0;\r
+ IcrLow.Bits.Vector = (StartupRoutine >> 12);\r
IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_STARTUP;\r
- IcrLow.Bits.Level = 1;\r
+ IcrLow.Bits.Level = 1;\r
SendIpi (IcrLow.Uint32, ApicId);\r
if (!StandardSignatureIsAuthenticAMD ()) {\r
MicroSecondDelay (200);\r
VOID\r
EFIAPI\r
SendInitSipiSipiAllExcludingSelf (\r
- IN UINT32 StartupRoutine\r
+ IN UINT32 StartupRoutine\r
)\r
{\r
- LOCAL_APIC_ICR_LOW IcrLow;\r
+ LOCAL_APIC_ICR_LOW IcrLow;\r
\r
ASSERT (StartupRoutine < 0x100000);\r
ASSERT ((StartupRoutine & 0xfff) == 0);\r
\r
SendInitIpiAllExcludingSelf ();\r
- MicroSecondDelay (PcdGet32(PcdCpuInitIpiDelayInMicroSeconds));\r
- IcrLow.Uint32 = 0;\r
- IcrLow.Bits.Vector = (StartupRoutine >> 12);\r
- IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_STARTUP;\r
- IcrLow.Bits.Level = 1;\r
+ MicroSecondDelay (PcdGet32 (PcdCpuInitIpiDelayInMicroSeconds));\r
+ IcrLow.Uint32 = 0;\r
+ IcrLow.Bits.Vector = (StartupRoutine >> 12);\r
+ IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_STARTUP;\r
+ IcrLow.Bits.Level = 1;\r
IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;\r
SendIpi (IcrLow.Uint32, 0);\r
if (!StandardSignatureIsAuthenticAMD ()) {\r
VOID\r
)\r
{\r
- LOCAL_APIC_SVR Svr;\r
- LOCAL_APIC_LVT_LINT Lint;\r
+ LOCAL_APIC_SVR Svr;\r
+ LOCAL_APIC_LVT_LINT Lint;\r
\r
//\r
// Enable the APIC via SVR and set the spurious interrupt to use Int 00F.\r
//\r
- Svr.Uint32 = ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET);\r
+ Svr.Uint32 = ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET);\r
Svr.Bits.SpuriousVector = 0xf;\r
Svr.Bits.SoftwareEnable = 1;\r
WriteLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET, Svr.Uint32);\r
//\r
// Program the LINT0 vector entry as ExtInt. Not masked, edge, active high.\r
//\r
- Lint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT0_OFFSET);\r
- Lint.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_EXTINT;\r
+ Lint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT0_OFFSET);\r
+ Lint.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_EXTINT;\r
Lint.Bits.InputPinPolarity = 0;\r
- Lint.Bits.TriggerMode = 0;\r
- Lint.Bits.Mask = 0;\r
+ Lint.Bits.TriggerMode = 0;\r
+ Lint.Bits.Mask = 0;\r
WriteLocalApicReg (XAPIC_LVT_LINT0_OFFSET, Lint.Uint32);\r
\r
//\r
// Program the LINT0 vector entry as NMI. Not masked, edge, active high.\r
//\r
- Lint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT1_OFFSET);\r
- Lint.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_NMI;\r
+ Lint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT1_OFFSET);\r
+ Lint.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_NMI;\r
Lint.Bits.InputPinPolarity = 0;\r
- Lint.Bits.TriggerMode = 0;\r
- Lint.Bits.Mask = 0;\r
+ Lint.Bits.TriggerMode = 0;\r
+ Lint.Bits.Mask = 0;\r
WriteLocalApicReg (XAPIC_LVT_LINT1_OFFSET, Lint.Uint32);\r
}\r
\r
VOID\r
)\r
{\r
- LOCAL_APIC_LVT_LINT LvtLint;\r
+ LOCAL_APIC_LVT_LINT LvtLint;\r
\r
- LvtLint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT0_OFFSET);\r
+ LvtLint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT0_OFFSET);\r
LvtLint.Bits.Mask = 1;\r
WriteLocalApicReg (XAPIC_LVT_LINT0_OFFSET, LvtLint.Uint32);\r
\r
- LvtLint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT1_OFFSET);\r
+ LvtLint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT1_OFFSET);\r
LvtLint.Bits.Mask = 1;\r
WriteLocalApicReg (XAPIC_LVT_LINT1_OFFSET, LvtLint.Uint32);\r
}\r
VOID\r
EFIAPI\r
InitializeApicTimer (\r
- IN UINTN DivideValue,\r
- IN UINT32 InitCount,\r
- IN BOOLEAN PeriodicMode,\r
- IN UINT8 Vector\r
+ IN UINTN DivideValue,\r
+ IN UINT32 InitCount,\r
+ IN BOOLEAN PeriodicMode,\r
+ IN UINT8 Vector\r
)\r
{\r
- LOCAL_APIC_DCR Dcr;\r
- LOCAL_APIC_LVT_TIMER LvtTimer;\r
- UINT32 Divisor;\r
+ LOCAL_APIC_DCR Dcr;\r
+ LOCAL_APIC_LVT_TIMER LvtTimer;\r
+ UINT32 Divisor;\r
\r
//\r
// Ensure local APIC is in software-enabled state.\r
\r
if (DivideValue != 0) {\r
ASSERT (DivideValue <= 128);\r
- ASSERT (DivideValue == GetPowerOfTwo32((UINT32)DivideValue));\r
+ ASSERT (DivideValue == GetPowerOfTwo32 ((UINT32)DivideValue));\r
Divisor = (UINT32)((HighBitSet32 ((UINT32)DivideValue) - 1) & 0x7);\r
\r
- Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET);\r
+ Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET);\r
Dcr.Bits.DivideValue1 = (Divisor & 0x3);\r
Dcr.Bits.DivideValue2 = (Divisor >> 2);\r
WriteLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET, Dcr.Uint32);\r
} else {\r
LvtTimer.Bits.TimerMode = 0;\r
}\r
- LvtTimer.Bits.Mask = 0;\r
+\r
+ LvtTimer.Bits.Mask = 0;\r
LvtTimer.Bits.Vector = Vector;\r
WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32);\r
}\r
OUT UINT8 *Vector OPTIONAL\r
)\r
{\r
- UINT32 Divisor;\r
- LOCAL_APIC_DCR Dcr;\r
- LOCAL_APIC_LVT_TIMER LvtTimer;\r
+ UINT32 Divisor;\r
+ LOCAL_APIC_DCR Dcr;\r
+ LOCAL_APIC_LVT_TIMER LvtTimer;\r
\r
//\r
// Check the APIC Software Enable/Disable bit (bit 8) in Spurious-Interrupt\r
// Vector Register.\r
// This bit will be 1, if local APIC is software enabled.\r
//\r
- ASSERT ((ReadLocalApicReg(XAPIC_SPURIOUS_VECTOR_OFFSET) & BIT8) != 0);\r
+ ASSERT ((ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET) & BIT8) != 0);\r
\r
if (DivideValue != NULL) {\r
- Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET);\r
- Divisor = Dcr.Bits.DivideValue1 | (Dcr.Bits.DivideValue2 << 2);\r
- Divisor = (Divisor + 1) & 0x7;\r
+ Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET);\r
+ Divisor = Dcr.Bits.DivideValue1 | (Dcr.Bits.DivideValue2 << 2);\r
+ Divisor = (Divisor + 1) & 0x7;\r
*DivideValue = ((UINTN)1) << Divisor;\r
}\r
\r
- if (PeriodicMode != NULL || Vector != NULL) {\r
+ if ((PeriodicMode != NULL) || (Vector != NULL)) {\r
LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);\r
if (PeriodicMode != NULL) {\r
if (LvtTimer.Bits.TimerMode == 1) {\r
*PeriodicMode = FALSE;\r
}\r
}\r
+\r
if (Vector != NULL) {\r
- *Vector = (UINT8) LvtTimer.Bits.Vector;\r
+ *Vector = (UINT8)LvtTimer.Bits.Vector;\r
}\r
}\r
}\r
VOID\r
)\r
{\r
- LOCAL_APIC_LVT_TIMER LvtTimer;\r
+ LOCAL_APIC_LVT_TIMER LvtTimer;\r
\r
- LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);\r
+ LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);\r
LvtTimer.Bits.Mask = 0;\r
WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32);\r
}\r
VOID\r
)\r
{\r
- LOCAL_APIC_LVT_TIMER LvtTimer;\r
+ LOCAL_APIC_LVT_TIMER LvtTimer;\r
\r
- LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);\r
+ LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);\r
LvtTimer.Bits.Mask = 1;\r
WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32);\r
}\r
VOID\r
)\r
{\r
- LOCAL_APIC_LVT_TIMER LvtTimer;\r
+ LOCAL_APIC_LVT_TIMER LvtTimer;\r
\r
LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);\r
return (BOOLEAN)(LvtTimer.Bits.Mask == 0);\r
MsiData.Bits.Level = 1;\r
}\r
}\r
+\r
return MsiData.Uint64;\r
}\r
\r
if (Thread != NULL) {\r
*Thread = 0;\r
}\r
+\r
if (Core != NULL) {\r
*Core = 0;\r
}\r
+\r
if (Package != NULL) {\r
*Package = 0;\r
}\r
+\r
return;\r
}\r
\r
// Assume three-level mapping of APIC ID: Package|Core|Thread.\r
//\r
ThreadBits = 0;\r
- CoreBits = 0;\r
+ CoreBits = 0;\r
\r
//\r
// Get max index of CPUID\r
//\r
TopologyLeafSupported = FALSE;\r
if (MaxStandardCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {\r
- AsmCpuidEx(\r
+ AsmCpuidEx (\r
CPUID_EXTENDED_TOPOLOGY,\r
0,\r
&ExtendedTopologyEax.Uint32,\r
CoreBits = ExtendedTopologyEax.Bits.ApicIdShift - ThreadBits;\r
break;\r
}\r
+\r
SubIndex++;\r
} while (LevelType != CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);\r
}\r
//\r
// Check for topology extensions on AMD processor\r
//\r
- if (StandardSignatureIsAuthenticAMD()) {\r
+ if (StandardSignatureIsAuthenticAMD ()) {\r
if (MaxExtendedCpuIdIndex >= CPUID_AMD_PROCESSOR_TOPOLOGY) {\r
AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, &AmdExtendedCpuSigEcx.Uint32, NULL);\r
if (AmdExtendedCpuSigEcx.Bits.TopologyExtensions != 0) {\r
MaxCoresPerPackage = MaxLogicProcessorsPerPackage / (AmdProcessorTopologyEbx.Bits.ThreadsPerCore + 1);\r
}\r
}\r
- }\r
- else {\r
+ } else {\r
//\r
// Extract core count based on CACHE information\r
//\r
}\r
}\r
\r
- ThreadBits = (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1);\r
- CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1);\r
+ ThreadBits = (UINTN)(HighBitSet32 (MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1);\r
+ CoreBits = (UINTN)(HighBitSet32 (MaxCoresPerPackage - 1) + 1);\r
}\r
\r
if (Thread != NULL) {\r
*Thread = InitialApicId & ((1 << ThreadBits) - 1);\r
}\r
+\r
if (Core != NULL) {\r
*Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);\r
}\r
+\r
if (Package != NULL) {\r
*Package = (InitialApicId >> (ThreadBits + CoreBits));\r
}\r
OUT UINT32 *Thread OPTIONAL\r
)\r
{\r
- CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax;\r
- CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx;\r
- UINT32 MaxStandardCpuIdIndex;\r
- UINT32 Index;\r
- UINTN LevelType;\r
- UINT32 Bits[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 2];\r
- UINT32 *Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 2];\r
+ CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax;\r
+ CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx;\r
+ UINT32 MaxStandardCpuIdIndex;\r
+ UINT32 Index;\r
+ UINTN LevelType;\r
+ UINT32 Bits[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 2];\r
+ UINT32 *Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 2];\r
\r
for (LevelType = 0; LevelType < ARRAY_SIZE (Bits); LevelType++) {\r
Bits[LevelType] = 0;\r
if (Die != NULL) {\r
*Die = 0;\r
}\r
+\r
if (Tile != NULL) {\r
*Tile = 0;\r
}\r
+\r
if (Module != NULL) {\r
*Module = 0;\r
}\r
+\r
GetProcessorLocationByApicId (InitialApicId, Package, Core, Thread);\r
return;\r
}\r
// is the preferred mechanism for enumerating topology.\r
//\r
for (Index = 0; ; Index++) {\r
- AsmCpuidEx(\r
+ AsmCpuidEx (\r
CPUID_V2_EXTENDED_TOPOLOGY,\r
Index,\r
&ExtendedTopologyEax.Uint32,\r
if (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID) {\r
break;\r
}\r
+\r
ASSERT (LevelType < ARRAY_SIZE (Bits));\r
Bits[LevelType] = ExtendedTopologyEax.Bits.ApicIdShift;\r
}\r
}\r
\r
Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 1] = Package;\r
- Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE ] = Die;\r
- Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_TILE ] = Tile;\r
- Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_MODULE ] = Module;\r
- Location[CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE ] = Core;\r
- Location[CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT ] = Thread;\r
+ Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE] = Die;\r
+ Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_TILE] = Tile;\r
+ Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_MODULE] = Module;\r
+ Location[CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE] = Core;\r
+ Location[CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT] = Thread;\r
\r
Bits[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 1] = 32;\r
\r
for ( LevelType = CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT\r
- ; LevelType <= CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 1\r
- ; LevelType ++\r
- ) {\r
+ ; LevelType <= CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 1\r
+ ; LevelType++\r
+ )\r
+ {\r
if (Location[LevelType] != NULL) {\r
//\r
// Bits[i] holds the number of bits to shift right on x2APIC ID to get a unique\r
projects / mirror_edk2.git / blobdiff