which have xAPIC and x2APIC modes.\r
\r
Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2017, AMD Inc. All rights reserved.<BR>\r
+\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
**/\r
\r
#include <Register/Cpuid.h>\r
+#include <Register/Amd/Cpuid.h>\r
#include <Register/Msr.h>\r
#include <Register/LocalApic.h>\r
\r
// Library internal functions\r
//\r
\r
+/**\r
+ Determine if the standard CPU signature is "AuthenticAMD".\r
+\r
+ @retval TRUE The CPU signature matches.\r
+ @retval FALSE The CPU signature does not match.\r
+\r
+**/\r
+BOOLEAN\r
+StandardSignatureIsAuthenticAMD (\r
+ VOID\r
+ )\r
+{\r
+ UINT32 RegEbx;\r
+ UINT32 RegEcx;\r
+ UINT32 RegEdx;\r
+\r
+ AsmCpuid(CPUID_SIGNATURE, NULL, &RegEbx, &RegEcx, &RegEdx);\r
+ return (RegEbx == CPUID_SIGNATURE_AUTHENTIC_AMD_EBX &&\r
+ RegEcx == CPUID_SIGNATURE_AUTHENTIC_AMD_ECX &&\r
+ RegEdx == CPUID_SIGNATURE_AUTHENTIC_AMD_EDX);\r
+}\r
+\r
/**\r
Determine if the CPU supports the Local APIC Base Address MSR.\r
\r
OUT UINT32 *Thread OPTIONAL\r
)\r
{\r
- BOOLEAN TopologyLeafSupported;\r
- UINTN ThreadBits;\r
- UINTN CoreBits;\r
- CPUID_VERSION_INFO_EBX VersionInfoEbx;\r
- CPUID_VERSION_INFO_EDX VersionInfoEdx;\r
- CPUID_CACHE_PARAMS_EAX CacheParamsEax;\r
- CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax;\r
- CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx;\r
- CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx;\r
- UINT32 MaxCpuIdIndex;\r
- UINT32 SubIndex;\r
- UINTN LevelType;\r
- UINT32 MaxLogicProcessorsPerPackage;\r
- UINT32 MaxCoresPerPackage;\r
+ BOOLEAN TopologyLeafSupported;\r
+ CPUID_VERSION_INFO_EBX VersionInfoEbx;\r
+ CPUID_VERSION_INFO_EDX VersionInfoEdx;\r
+ CPUID_CACHE_PARAMS_EAX CacheParamsEax;\r
+ CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax;\r
+ CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx;\r
+ CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx;\r
+ CPUID_AMD_EXTENDED_CPU_SIG_ECX AmdExtendedCpuSigEcx;\r
+ CPUID_AMD_PROCESSOR_TOPOLOGY_EBX AmdProcessorTopologyEbx;\r
+ CPUID_AMD_PROCESSOR_TOPOLOGY_ECX AmdProcessorTopologyEcx;\r
+ CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX AmdVirPhyAddressSizeEcx;\r
+ UINT32 MaxStandardCpuIdIndex;\r
+ UINT32 MaxExtendedCpuIdIndex;\r
+ UINT32 SubIndex;\r
+ UINTN LevelType;\r
+ UINT32 MaxLogicProcessorsPerPackage;\r
+ UINT32 MaxCoresPerPackage;\r
+ UINT32 MaxThreadPerPackageMask;\r
+ UINT32 ActualThreadPerPackageMask;\r
+ UINT32 MaxCoresPerNode;\r
+ UINT32 CorePerNodeMask;\r
+ UINT32 ApicIdShift;\r
+ UINTN ThreadBits;\r
+ UINTN CoreBits;\r
\r
//\r
// Check if the processor is capable of supporting more than one logical processor.\r
AsmCpuid(CPUID_VERSION_INFO, NULL, NULL, NULL, &VersionInfoEdx.Uint32);\r
if (VersionInfoEdx.Bits.HTT == 0) {\r
if (Thread != NULL) {\r
- *Thread = 0;\r
+ *Thread = 0;\r
}\r
if (Core != NULL) {\r
- *Core = 0;\r
+ *Core = 0;\r
}\r
if (Package != NULL) {\r
*Package = 0;\r
return;\r
}\r
\r
- ThreadBits = 0;\r
- CoreBits = 0;\r
-\r
//\r
- // Assume three-level mapping of APIC ID: Package:Core:SMT.\r
+ // Assume three-level mapping of APIC ID: Package|Core|Thread.\r
//\r
- TopologyLeafSupported = FALSE;\r
+ ThreadBits = 0;\r
+ CoreBits = 0;\r
\r
//\r
- // Get the max index of basic CPUID\r
+ // Get max index of CPUID\r
//\r
- AsmCpuid(CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);\r
+ AsmCpuid(CPUID_SIGNATURE, &MaxStandardCpuIdIndex, NULL, NULL, NULL);\r
+ AsmCpuid(CPUID_EXTENDED_FUNCTION, &MaxExtendedCpuIdIndex, NULL, NULL, NULL);\r
\r
//\r
// If the extended topology enumeration leaf is available, it\r
// is the preferred mechanism for enumerating topology.\r
//\r
- if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {\r
+ TopologyLeafSupported = FALSE;\r
+ if (MaxStandardCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {\r
AsmCpuidEx(\r
CPUID_EXTENDED_TOPOLOGY,\r
0,\r
}\r
\r
if (!TopologyLeafSupported) {\r
+ //\r
+ // Get logical processor count\r
+ //\r
AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL);\r
MaxLogicProcessorsPerPackage = VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;\r
- if (MaxCpuIdIndex >= CPUID_CACHE_PARAMS) {\r
- AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL, NULL);\r
- MaxCoresPerPackage = CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1;\r
+\r
+ //\r
+ // Assume single-core processor\r
+ //\r
+ MaxCoresPerPackage = 1;\r
+\r
+ //\r
+ // Check for topology extensions on AMD processor\r
+ //\r
+ if (StandardSignatureIsAuthenticAMD()) {\r
+ if (MaxExtendedCpuIdIndex >= CPUID_AMD_PROCESSOR_TOPOLOGY) {\r
+ AsmCpuid(CPUID_EXTENDED_CPU_SIG, NULL, NULL, &AmdExtendedCpuSigEcx.Uint32, NULL);\r
+ if (AmdExtendedCpuSigEcx.Bits.TopologyExtensions != 0) {\r
+ AsmCpuid(CPUID_AMD_PROCESSOR_TOPOLOGY, NULL, &AmdProcessorTopologyEbx.Uint32,\r
+ &AmdProcessorTopologyEcx.Uint32, NULL);\r
+ //\r
+ // Get cores per processor package\r
+ //\r
+ MaxCoresPerPackage = MaxLogicProcessorsPerPackage / (AmdProcessorTopologyEbx.Bits.ThreadsPerCore + 1);\r
+\r
+ //\r
+ // Account for actual thread count (e.g., SMT disabled)\r
+ //\r
+ AsmCpuid(CPUID_VIR_PHY_ADDRESS_SIZE, NULL, NULL, &AmdVirPhyAddressSizeEcx.Uint32, NULL);\r
+ MaxThreadPerPackageMask = 1 << AmdVirPhyAddressSizeEcx.Bits.ApicIdCoreIdSize;\r
+ ActualThreadPerPackageMask = 1;\r
+ while (ActualThreadPerPackageMask < MaxLogicProcessorsPerPackage) {\r
+ ActualThreadPerPackageMask <<= 1;\r
+ }\r
+\r
+ //\r
+ // Adjust APIC Id to report concatenation of Package|Core|Thread.\r
+ //\r
+ if (ActualThreadPerPackageMask < MaxThreadPerPackageMask) {\r
+ MaxCoresPerNode = MaxCoresPerPackage / (AmdProcessorTopologyEcx.Bits.NodesPerProcessor + 1);\r
+\r
+ CorePerNodeMask = 1;\r
+ while (CorePerNodeMask < MaxCoresPerNode) {\r
+ CorePerNodeMask <<= 1;\r
+ }\r
+ CorePerNodeMask -= 1;\r
+\r
+ ApicIdShift = 0;\r
+ do {\r
+ ApicIdShift += 1;\r
+ ActualThreadPerPackageMask <<= 1;\r
+ } while (ActualThreadPerPackageMask < MaxThreadPerPackageMask);\r
+\r
+ InitialApicId = ((InitialApicId & ~CorePerNodeMask) >> ApicIdShift) | (InitialApicId & CorePerNodeMask);\r
+ }\r
+ }\r
+ }\r
}\r
else {\r
//\r
- // Must be a single-core processor.\r
+ // Extract core count based on CACHE information\r
//\r
- MaxCoresPerPackage = 1;\r
+ if (MaxStandardCpuIdIndex >= CPUID_CACHE_PARAMS) {\r
+ AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL, NULL);\r
+ if (CacheParamsEax.Uint32 != 0) {\r
+ MaxCoresPerPackage = CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1;\r
+ }\r
+ }\r
}\r
\r
ThreadBits = (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1);\r
- CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1); }\r
+ CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1);\r
+ }\r
\r
if (Thread != NULL) {\r
- *Thread = InitialApicId & ((1 << ThreadBits) - 1);\r
+ *Thread = InitialApicId & ((1 << ThreadBits) - 1);\r
}\r
if (Core != NULL) {\r
- *Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);\r
+ *Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);\r
}\r
if (Package != NULL) {\r
*Package = (InitialApicId >> (ThreadBits + CoreBits));\r
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