This local APIC library instance supports x2APIC capable processors\r
which have xAPIC and x2APIC modes.\r
\r
- Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>\r
Copyright (c) 2017, AMD Inc. All rights reserved.<BR>\r
\r
This program and the accompanying materials\r
{\r
UINT32 RegEax;\r
UINTN FamilyId;\r
- \r
+\r
AsmCpuid (1, &RegEax, NULL, NULL, NULL);\r
FamilyId = BitFieldRead32 (RegEax, 8, 11);\r
if (FamilyId == 0x04 || FamilyId == 0x05) {\r
//\r
- // CPUs with a FamilyId of 0x04 or 0x05 do not support the \r
+ // CPUs with a FamilyId of 0x04 or 0x05 do not support the\r
// Local APIC Base Address MSR\r
//\r
return FALSE;\r
}\r
\r
ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);\r
- \r
+\r
return (UINTN)(LShiftU64 ((UINT64) ApicBaseMsr.Bits.ApicBaseHi, 32)) +\r
(((UINTN)ApicBaseMsr.Bits.ApicBase) << 12);\r
}\r
/**\r
Send an IPI by writing to ICR.\r
\r
- This function returns after the IPI has been accepted by the target processor. \r
+ This function returns after the IPI has been accepted by the target processor.\r
\r
@param IcrLow 32-bit value to be written to the low half of ICR.\r
@param ApicId APIC ID of the target processor if this IPI is targeted for a specific processor.\r
\r
} else {\r
//\r
- // For x2APIC, A single MSR write to the Interrupt Command Register is required for dispatching an \r
+ // For x2APIC, A single MSR write to the Interrupt Command Register is required for dispatching an\r
// interrupt in x2APIC mode.\r
//\r
MsrValue = LShiftU64 ((UINT64) ApicId, 32) | IcrLow;\r
Get the initial local APIC ID of the executing processor assigned by hardware upon power on or reset.\r
\r
In xAPIC mode, the initial local APIC ID may be different from current APIC ID.\r
- In x2APIC mode, the local APIC ID can't be changed and there is no concept of initial APIC ID. In this case, \r
+ In x2APIC mode, the local APIC ID can't be changed and there is no concept of initial APIC ID. In this case,\r
the 32-bit local APIC ID is returned as initial APIC ID.\r
\r
@return 32-bit initial local APIC ID of the executing processor.\r
//\r
AsmCpuid (CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);\r
//\r
- // If CPUID Leaf B is supported, \r
+ // If CPUID Leaf B is supported,\r
// And CPUID.0BH:EBX[15:0] reports a non-zero value,\r
// Then the initial 32-bit APIC ID = CPUID.0BH:EDX\r
// Else the initial 8-bit APIC ID = CPUID.1:EBX[31:24]\r
/**\r
Send a Fixed IPI to a specified target processor.\r
\r
- This function returns after the IPI has been accepted by the target processor. \r
+ This function returns after the IPI has been accepted by the target processor.\r
\r
@param ApicId The local APIC ID of the target processor.\r
@param Vector The vector number of the interrupt being sent.\r
/**\r
Send a Fixed IPI to all processors excluding self.\r
\r
- This function returns after the IPI has been accepted by the target processors. \r
+ This function returns after the IPI has been accepted by the target processors.\r
\r
@param Vector The vector number of the interrupt being sent.\r
**/\r
/**\r
Send a SMI IPI to a specified target processor.\r
\r
- This function returns after the IPI has been accepted by the target processor. \r
+ This function returns after the IPI has been accepted by the target processor.\r
\r
@param ApicId Specify the local APIC ID of the target processor.\r
**/\r
/**\r
Send a SMI IPI to all processors excluding self.\r
\r
- This function returns after the IPI has been accepted by the target processors. \r
+ This function returns after the IPI has been accepted by the target processors.\r
**/\r
VOID\r
EFIAPI\r
/**\r
Send an INIT IPI to a specified target processor.\r
\r
- This function returns after the IPI has been accepted by the target processor. \r
+ This function returns after the IPI has been accepted by the target processor.\r
\r
@param ApicId Specify the local APIC ID of the target processor.\r
**/\r
/**\r
Send an INIT IPI to all processors excluding self.\r
\r
- This function returns after the IPI has been accepted by the target processors. \r
+ This function returns after the IPI has been accepted by the target processors.\r
**/\r
VOID\r
EFIAPI\r
/**\r
Send an INIT-Start-up-Start-up IPI sequence to a specified target processor.\r
\r
- This function returns after the IPI has been accepted by the target processor. \r
+ This function returns after the IPI has been accepted by the target processor.\r
\r
if StartupRoutine >= 1M, then ASSERT.\r
if StartupRoutine is not multiple of 4K, then ASSERT.\r
/**\r
Send an INIT-Start-up-Start-up IPI sequence to all processors excluding self.\r
\r
- This function returns after the IPI has been accepted by the target processors. \r
+ This function returns after the IPI has been accepted by the target processors.\r
\r
if StartupRoutine >= 1M, then ASSERT.\r
if StartupRoutine is not multiple of 4K, then ASSERT.\r
Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET);\r
Dcr.Bits.DivideValue1 = (Divisor & 0x3);\r
Dcr.Bits.DivideValue2 = (Divisor >> 2);\r
- WriteLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET, Dcr.Uint32); \r
+ WriteLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET, Dcr.Uint32);\r
}\r
\r
//\r
}\r
\r
/**\r
- Get the 32-bit address that a device should use to send a Message Signaled \r
+ Get the 32-bit address that a device should use to send a Message Signaled\r
Interrupt (MSI) to the Local APIC of the currently executing processor.\r
\r
@return 32-bit address used to send an MSI to the Local APIC.\r
**/\r
UINT32\r
-EFIAPI \r
+EFIAPI\r
GetApicMsiAddress (\r
VOID\r
)\r
LOCAL_APIC_MSI_ADDRESS MsiAddress;\r
\r
//\r
- // Return address for an MSI interrupt to be delivered only to the APIC ID \r
+ // Return address for an MSI interrupt to be delivered only to the APIC ID\r
// of the currently executing processor.\r
//\r
MsiAddress.Uint32 = 0;\r
MsiAddress.Bits.DestinationId = GetApicId ();\r
return MsiAddress.Uint32;\r
}\r
- \r
+\r
/**\r
- Get the 64-bit data value that a device should use to send a Message Signaled \r
+ Get the 64-bit data value that a device should use to send a Message Signaled\r
Interrupt (MSI) to the Local APIC of the currently executing processor.\r
\r
If Vector is not in range 0x10..0xFE, then ASSERT().\r
If DeliveryMode is not supported, then ASSERT().\r
- \r
- @param Vector The 8-bit interrupt vector associated with the MSI. \r
+\r
+ @param Vector The 8-bit interrupt vector associated with the MSI.\r
Must be in the range 0x10..0xFE\r
- @param DeliveryMode A 3-bit value that specifies how the recept of the MSI \r
+ @param DeliveryMode A 3-bit value that specifies how the recept of the MSI\r
is handled. The only supported values are:\r
0: LOCAL_APIC_DELIVERY_MODE_FIXED\r
1: LOCAL_APIC_DELIVERY_MODE_LOWEST_PRIORITY\r
4: LOCAL_APIC_DELIVERY_MODE_NMI\r
5: LOCAL_APIC_DELIVERY_MODE_INIT\r
7: LOCAL_APIC_DELIVERY_MODE_EXTINT\r
- \r
- @param LevelTriggered TRUE specifies a level triggered interrupt. \r
+\r
+ @param LevelTriggered TRUE specifies a level triggered interrupt.\r
FALSE specifies an edge triggered interrupt.\r
@param AssertionLevel Ignored if LevelTriggered is FALSE.\r
- TRUE specifies a level triggered interrupt that active \r
+ TRUE specifies a level triggered interrupt that active\r
when the interrupt line is asserted.\r
- FALSE specifies a level triggered interrupt that active \r
+ FALSE specifies a level triggered interrupt that active\r
when the interrupt line is deasserted.\r
\r
@return 64-bit data value used to send an MSI to the Local APIC.\r
**/\r
UINT64\r
-EFIAPI \r
+EFIAPI\r
GetApicMsiValue (\r
IN UINT8 Vector,\r
IN UINTN DeliveryMode,\r
\r
ASSERT (Vector >= 0x10 && Vector <= 0xFE);\r
ASSERT (DeliveryMode < 8 && DeliveryMode != 6 && DeliveryMode != 3);\r
- \r
+\r
MsiData.Uint64 = 0;\r
MsiData.Bits.Vector = Vector;\r
MsiData.Bits.DeliveryMode = (UINT32)DeliveryMode;\r
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