// For x2APIC, A single MSR write to the Interrupt Command Register is required for dispatching an \r
// interrupt in x2APIC mode.\r
//\r
- MsrValue = (((UINT64)ApicId) << 32) | IcrLow;\r
+ MsrValue = LShiftU64 ((UINT64) ApicId, 32) | IcrLow;\r
AsmWriteMsr64 (X2APIC_MSR_ICR_ADDRESS, MsrValue);\r
}\r
}\r
WriteLocalApicReg (XAPIC_LVT_LINT1_OFFSET, Lint.Uint32);\r
}\r
\r
+/**\r
+ Disable LINT0 & LINT1 interrupts.\r
+\r
+ This function sets the mask flag in the LVT LINT0 & LINT1 registers.\r
+**/\r
+VOID\r
+EFIAPI\r
+DisableLvtInterrupts (\r
+ VOID\r
+ )\r
+{\r
+ LOCAL_APIC_LVT_LINT LvtLint;\r
+\r
+ LvtLint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT0_OFFSET);\r
+ LvtLint.Bits.Mask = 1;\r
+ WriteLocalApicReg (XAPIC_LVT_LINT0_OFFSET, LvtLint.Uint32);\r
+\r
+ LvtLint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT1_OFFSET);\r
+ LvtLint.Bits.Mask = 1;\r
+ WriteLocalApicReg (XAPIC_LVT_LINT1_OFFSET, LvtLint.Uint32);\r
+}\r
+\r
/**\r
Read the initial count value from the init-count register.\r
\r