/** @file\r
Intel Processor Trace feature.\r
\r
- Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>\r
- This program and the accompanying materials\r
- are licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+ Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.<BR>\r
+ SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
\r
///\r
/// This macro define the max entries in the Topa table.\r
-/// Each entry in the table contains some attribute bits, a pointer to an output region, and the size of the region. \r
-/// The last entry in the table may hold a pointer to the next table. This pointer can either point to the top of the \r
-/// current table (for circular array) or to the base of another table. \r
-/// At least 2 entries are needed because the list of entries must \r
-/// be terminated by an entry with the END bit set to 1, so 2 \r
+/// Each entry in the table contains some attribute bits, a pointer to an output region, and the size of the region.\r
+/// The last entry in the table may hold a pointer to the next table. This pointer can either point to the top of the\r
+/// current table (for circular array) or to the base of another table.\r
+/// At least 2 entries are needed because the list of entries must\r
+/// be terminated by an entry with the END bit set to 1, so 2\r
/// entries are required to use a single valid entry.\r
///\r
#define MAX_TOPA_ENTRY_COUNT 2\r
/// Processor trace output scheme selection.\r
///\r
typedef enum {\r
- OutputSchemeSingleRange = 0,\r
- OutputSchemeToPA,\r
- OutputSchemeInvalid\r
-} PROC_TRACE_OUTPUT_SCHEME;\r
+ RtitOutputSchemeSingleRange = 0,\r
+ RtitOutputSchemeToPA\r
+} RTIT_OUTPUT_SCHEME;\r
\r
typedef struct {\r
BOOLEAN ProcTraceSupported;\r
typedef struct {\r
UINT32 NumberOfProcessors;\r
\r
- UINT8 ProcTraceOutputScheme; \r
+ UINT8 ProcTraceOutputScheme;\r
UINT32 ProcTraceMemSize;\r
\r
UINTN *ThreadMemRegionTable;\r
}\r
\r
/**\r
- Detects if Intel Processor Trace feature supported on current \r
+ Detects if Intel Processor Trace feature supported on current\r
processor.\r
\r
@param[in] ProcessorNumber The index of the CPU executing this function.\r
// Check if ProcTraceMemorySize option is enabled (0xFF means disable by user)\r
//\r
ProcTraceData = (PROC_TRACE_DATA *) ConfigData;\r
+ ASSERT (ProcTraceData != NULL);\r
if ((ProcTraceData->ProcTraceMemSize > RtitTopaMemorySize128M) ||\r
- (ProcTraceData->ProcTraceOutputScheme > ProcTraceOutputSchemeToPA)) {\r
+ (ProcTraceData->ProcTraceOutputScheme > RtitOutputSchemeToPA)) {\r
return FALSE;\r
}\r
\r
AsmCpuidEx (CPUID_INTEL_PROCESSOR_TRACE, CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF, NULL, NULL, &Ecx.Uint32, NULL);\r
ProcTraceData->ProcessorData[ProcessorNumber].TopaSupported = (BOOLEAN) (Ecx.Bits.RTIT == 1);\r
ProcTraceData->ProcessorData[ProcessorNumber].SingleRangeSupported = (BOOLEAN) (Ecx.Bits.SingleRangeOutput == 1);\r
- if (ProcTraceData->ProcessorData[ProcessorNumber].TopaSupported || \r
- ProcTraceData->ProcessorData[ProcessorNumber].SingleRangeSupported) {\r
+ if ((ProcTraceData->ProcessorData[ProcessorNumber].TopaSupported && (ProcTraceData->ProcTraceOutputScheme == RtitOutputSchemeToPA)) ||\r
+ (ProcTraceData->ProcessorData[ProcessorNumber].SingleRangeSupported && (ProcTraceData->ProcTraceOutputScheme == RtitOutputSchemeSingleRange))) {\r
return TRUE;\r
}\r
\r
MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER OutputMaskPtrsReg;\r
RTIT_TOPA_TABLE_ENTRY *TopaEntryPtr;\r
\r
- ProcTraceData = (PROC_TRACE_DATA *) ConfigData;\r
-\r
- MemRegionBaseAddr = 0;\r
- FirstIn = FALSE;\r
-\r
- if (ProcTraceData->ThreadMemRegionTable == NULL) {\r
- FirstIn = TRUE;\r
- DEBUG ((DEBUG_INFO, "Initialize Processor Trace\n"));\r
+ //\r
+ // The scope of the MSR_IA32_RTIT_* is core for below processor type, only program\r
+ // MSR_IA32_RTIT_* for thread 0 in each core.\r
+ //\r
+ if (IS_GOLDMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||\r
+ IS_GOLDMONT_PLUS_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) {\r
+ if (CpuInfo->ProcessorInfo.Location.Thread != 0) {\r
+ return RETURN_SUCCESS;\r
+ }\r
}\r
\r
- ///\r
- /// Refer to PROC_TRACE_MEM_SIZE Table for Size Encoding\r
- ///\r
- MemRegionSize = (UINT32) (1 << (ProcTraceData->ProcTraceMemSize + 12));\r
- if (FirstIn) {\r
- DEBUG ((DEBUG_INFO, "ProcTrace: MemSize requested: 0x%X \n", MemRegionSize));\r
- }\r
+ ProcTraceData = (PROC_TRACE_DATA *) ConfigData;\r
+ ASSERT (ProcTraceData != NULL);\r
\r
//\r
// Clear MSR_IA32_RTIT_CTL[0] and IA32_RTIT_STS only if MSR_IA32_RTIT_CTL[0]==1b\r
);\r
}\r
\r
+ if (!State) {\r
+ return RETURN_SUCCESS;\r
+ }\r
+\r
+ MemRegionBaseAddr = 0;\r
+ FirstIn = FALSE;\r
+\r
+ if (ProcTraceData->ThreadMemRegionTable == NULL) {\r
+ FirstIn = TRUE;\r
+ DEBUG ((DEBUG_INFO, "Initialize Processor Trace\n"));\r
+ }\r
+\r
+ ///\r
+ /// Refer to PROC_TRACE_MEM_SIZE Table for Size Encoding\r
+ ///\r
+ MemRegionSize = (UINT32) (1 << (ProcTraceData->ProcTraceMemSize + 12));\r
+ if (FirstIn) {\r
+ DEBUG ((DEBUG_INFO, "ProcTrace: MemSize requested: 0x%X \n", MemRegionSize));\r
+ }\r
+\r
if (FirstIn) {\r
//\r
// Let BSP allocate and create the necessary memory region (Aligned to the size of\r
//\r
// Single Range output scheme\r
//\r
- if (ProcTraceData->ProcessorData[ProcessorNumber].SingleRangeSupported && \r
- (ProcTraceData->ProcTraceOutputScheme == OutputSchemeSingleRange)) {\r
+ if (ProcTraceData->ProcessorData[ProcessorNumber].SingleRangeSupported &&\r
+ (ProcTraceData->ProcTraceOutputScheme == RtitOutputSchemeSingleRange)) {\r
if (FirstIn) {\r
DEBUG ((DEBUG_INFO, "ProcTrace: Enabling Single Range Output scheme \n"));\r
}\r
// Program the Mask bits for the Memory Region to MSR IA32_RTIT_OUTPUT_MASK_PTRS (561h)\r
//\r
OutputMaskPtrsReg.Bits.MaskOrTableOffset = ((MemRegionSize - 1) >> 7) & 0x01FFFFFF;\r
- OutputMaskPtrsReg.Bits.OutputOffset = RShiftU64 ((UINT64) (MemRegionSize - 1), 32) & 0xFFFFFFFF;\r
+ OutputMaskPtrsReg.Bits.OutputOffset = RShiftU64 (MemRegionSize - 1, 32) & 0xFFFFFFFF;\r
CPU_REGISTER_TABLE_WRITE64 (\r
ProcessorNumber,\r
Msr,\r
//\r
// ToPA(Table of physical address) scheme\r
//\r
- if (ProcTraceData->ProcessorData[ProcessorNumber].TopaSupported && \r
- (ProcTraceData->ProcTraceOutputScheme == OutputSchemeToPA)) {\r
+ if (ProcTraceData->ProcessorData[ProcessorNumber].TopaSupported &&\r
+ (ProcTraceData->ProcTraceOutputScheme == RtitOutputSchemeToPA)) {\r
//\r
// Create ToPA structure aligned at 4KB for each logical thread\r
// with at least 2 entries by 8 bytes size each. The first entry\r
CtrlReg.Bits.OS = 1;\r
CtrlReg.Bits.User = 1;\r
CtrlReg.Bits.BranchEn = 1;\r
- if (!State) {\r
- CtrlReg.Bits.TraceEn = 0;\r
- } else {\r
- CtrlReg.Bits.TraceEn = 1;\r
- }\r
+ CtrlReg.Bits.TraceEn = 1;\r
CPU_REGISTER_TABLE_WRITE64 (\r
ProcessorNumber,\r
Msr,\r
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