/** @file\r
CPU MP Initialize Library common functions.\r
\r
- Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
\r
/**\r
The function will check if BSP Execute Disable is enabled.\r
- DxeIpl may have enabled Execute Disable for BSP,\r
- APs need to get the status and sync up the settings.\r
+\r
+ DxeIpl may have enabled Execute Disable for BSP, APs need to\r
+ get the status and sync up the settings.\r
+ If BSP's CR0.Paging is not set, BSP execute Disble feature is\r
+ not working actually.\r
\r
@retval TRUE BSP Execute Disable is enabled.\r
@retval FALSE BSP Execute Disable is not enabled.\r
CPUID_EXTENDED_CPU_SIG_EDX Edx;\r
MSR_IA32_EFER_REGISTER EferMsr;\r
BOOLEAN Enabled;\r
+ IA32_CR0 Cr0;\r
\r
Enabled = FALSE;\r
- AsmCpuid (CPUID_EXTENDED_FUNCTION, &Eax, NULL, NULL, NULL);\r
- if (Eax >= CPUID_EXTENDED_CPU_SIG) {\r
- AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, NULL, &Edx.Uint32);\r
+ Cr0.UintN = AsmReadCr0 ();\r
+ if (Cr0.Bits.PG != 0) {\r
//\r
- // CPUID 0x80000001\r
- // Bit 20: Execute Disable Bit available.\r
+ // If CR0 Paging bit is set\r
//\r
- if (Edx.Bits.NX != 0) {\r
- EferMsr.Uint64 = AsmReadMsr64 (MSR_IA32_EFER);\r
+ AsmCpuid (CPUID_EXTENDED_FUNCTION, &Eax, NULL, NULL, NULL);\r
+ if (Eax >= CPUID_EXTENDED_CPU_SIG) {\r
+ AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, NULL, &Edx.Uint32);\r
//\r
- // MSR 0xC0000080\r
- // Bit 11: Execute Disable Bit enable.\r
+ // CPUID 0x80000001\r
+ // Bit 20: Execute Disable Bit available.\r
//\r
- if (EferMsr.Bits.NXE != 0) {\r
- Enabled = TRUE;\r
+ if (Edx.Bits.NX != 0) {\r
+ EferMsr.Uint64 = AsmReadMsr64 (MSR_IA32_EFER);\r
+ //\r
+ // MSR 0xC0000080\r
+ // Bit 11: Execute Disable Bit enable.\r
+ //\r
+ if (EferMsr.Bits.NXE != 0) {\r
+ Enabled = TRUE;\r
+ }\r
}\r
}\r
}\r
}\r
\r
/**\r
- Save BSP's local APIC timer setting\r
+ Save BSP's local APIC timer setting.\r
\r
@param[in] CpuMpData Pointer to CPU MP Data\r
**/\r
VolatileRegisters->Dr6 = AsmReadDr6 ();\r
VolatileRegisters->Dr7 = AsmReadDr7 ();\r
}\r
+\r
+ AsmReadGdtr (&VolatileRegisters->Gdtr);\r
+ AsmReadIdtr (&VolatileRegisters->Idtr);\r
+ VolatileRegisters->Tr = AsmReadTr ();\r
}\r
\r
/**\r
)\r
{\r
CPUID_VERSION_INFO_EDX VersionInfoEdx;\r
+ IA32_TSS_DESCRIPTOR *Tss;\r
\r
AsmWriteCr0 (VolatileRegisters->Cr0);\r
AsmWriteCr3 (VolatileRegisters->Cr3);\r
AsmWriteDr7 (VolatileRegisters->Dr7);\r
}\r
}\r
+\r
+ AsmWriteGdtr (&VolatileRegisters->Gdtr);\r
+ AsmWriteIdtr (&VolatileRegisters->Idtr);\r
+ if (VolatileRegisters->Tr != 0 &&\r
+ VolatileRegisters->Tr < VolatileRegisters->Gdtr.Limit) {\r
+ Tss = (IA32_TSS_DESCRIPTOR *)(VolatileRegisters->Gdtr.Base +\r
+ VolatileRegisters->Tr);\r
+ if (Tss->Bits.P == 1) {\r
+ Tss->Bits.Type &= 0xD; // 1101 - Clear busy bit just in case\r
+ AsmWriteTr (VolatileRegisters->Tr);\r
+ }\r
+ }\r
}\r
\r
/**\r
CPU_INFO_IN_HOB CpuInfo;\r
UINT32 ApCount;\r
CPU_INFO_IN_HOB *CpuInfoInHob;\r
+ volatile UINT32 *StartupApSignal;\r
\r
ApCount = CpuMpData->CpuCount - 1;\r
CpuInfoInHob = (CPU_INFO_IN_HOB *) (UINTN) CpuMpData->CpuInfoInHob;\r
sizeof (CPU_INFO_IN_HOB)\r
);\r
CopyMem (&CpuInfoInHob[Index1], &CpuInfo, sizeof (CPU_INFO_IN_HOB));\r
+\r
+ //\r
+ // Also exchange the StartupApSignal.\r
+ //\r
+ StartupApSignal = CpuMpData->CpuData[Index3].StartupApSignal;\r
+ CpuMpData->CpuData[Index3].StartupApSignal =\r
+ CpuMpData->CpuData[Index1].StartupApSignal;\r
+ CpuMpData->CpuData[Index1].StartupApSignal = StartupApSignal;\r
}\r
}\r
\r
\r
CpuMpData = (CPU_MP_DATA *) Buffer;\r
//\r
- // Sync BSP's MTRR table to AP\r
+ // Load microcode on AP\r
//\r
- MtrrSetAllMtrrs (&CpuMpData->MtrrTable);\r
+ MicrocodeDetect (CpuMpData, FALSE);\r
//\r
- // Load microcode on AP\r
+ // Sync BSP's MTRR table to AP\r
//\r
- MicrocodeDetect (CpuMpData);\r
+ MtrrSetAllMtrrs (&CpuMpData->MtrrTable);\r
}\r
\r
/**\r
UINTN TotalProcessorNumber;\r
UINTN Index;\r
CPU_INFO_IN_HOB *CpuInfoInHob;\r
+ UINT32 CurrentApicId;\r
\r
CpuInfoInHob = (CPU_INFO_IN_HOB *) (UINTN) CpuMpData->CpuInfoInHob;\r
\r
TotalProcessorNumber = CpuMpData->CpuCount;\r
+ CurrentApicId = GetApicId ();\r
for (Index = 0; Index < TotalProcessorNumber; Index ++) {\r
- if (CpuInfoInHob[Index].ApicId == GetApicId ()) {\r
+ if (CpuInfoInHob[Index].ApicId == CurrentApicId) {\r
*ProcessorNumber = Index;\r
return EFI_SUCCESS;\r
}\r
}\r
+\r
return EFI_NOT_FOUND;\r
}\r
\r
IN CPU_MP_DATA *CpuMpData\r
)\r
{\r
+ UINTN Index;\r
+\r
//\r
// Send 1st broadcast IPI to APs to wakeup APs\r
//\r
CpuPause ();\r
}\r
\r
+ if (CpuMpData->CpuCount > 255) {\r
+ //\r
+ // If there are more than 255 processor found, force to enable X2APIC\r
+ //\r
+ CpuMpData->X2ApicEnable = TRUE;\r
+ }\r
if (CpuMpData->X2ApicEnable) {\r
DEBUG ((DEBUG_INFO, "Force x2APIC mode!\n"));\r
//\r
// Enable x2APIC on BSP\r
//\r
SetApicMode (LOCAL_APIC_MODE_X2APIC);\r
+ //\r
+ // Set BSP/Aps state to IDLE\r
+ //\r
+ for (Index = 0; Index < CpuMpData->CpuCount; Index++) {\r
+ SetApState (&CpuMpData->CpuData[Index], CpuStateIdle);\r
+ }\r
}\r
DEBUG ((DEBUG_INFO, "APIC MODE is %d\n", GetApicMode ()));\r
//\r
This function will be called from AP reset code if BSP uses WakeUpAP.\r
\r
@param[in] ExchangeInfo Pointer to the MP exchange info buffer\r
- @param[in] NumApsExecuting Number of current executing AP\r
+ @param[in] ApIndex Number of current executing AP\r
**/\r
VOID\r
EFIAPI\r
ApWakeupFunction (\r
IN MP_CPU_EXCHANGE_INFO *ExchangeInfo,\r
- IN UINTN NumApsExecuting\r
+ IN UINTN ApIndex\r
)\r
{\r
CPU_MP_DATA *CpuMpData;\r
volatile UINT32 *ApStartupSignalBuffer;\r
CPU_INFO_IN_HOB *CpuInfoInHob;\r
UINT64 ApTopOfStack;\r
+ UINTN CurrentApicMode;\r
\r
//\r
// AP finished assembly code and begin to execute C code\r
// We need to re-initialize them at here\r
//\r
ProgramVirtualWireMode ();\r
+ //\r
+ // Mask the LINT0 and LINT1 so that AP doesn't enter the system timer interrupt handler.\r
+ //\r
+ DisableLvtInterrupts ();\r
SyncLocalApicTimerSetting (CpuMpData);\r
\r
+ CurrentApicMode = GetApicMode ();\r
while (TRUE) {\r
if (CpuMpData->InitFlag == ApInitConfig) {\r
//\r
// Add CPU number\r
//\r
InterlockedIncrement ((UINT32 *) &CpuMpData->CpuCount);\r
- ProcessorNumber = NumApsExecuting;\r
+ ProcessorNumber = ApIndex;\r
//\r
// This is first time AP wakeup, get BIST information from AP stack\r
//\r
//\r
ApInitializeSync (CpuMpData);\r
//\r
- // Sync BSP's Control registers to APs\r
+ // CpuMpData->CpuData[0].VolatileRegisters is initialized based on BSP environment,\r
+ // to initialize AP in InitConfig path.\r
+ // NOTE: IDTR.BASE stored in CpuMpData->CpuData[0].VolatileRegisters points to a different IDT shared by all APs.\r
//\r
RestoreVolatileRegisters (&CpuMpData->CpuData[0].VolatileRegisters, FALSE);\r
InitializeApData (CpuMpData, ProcessorNumber, BistData, ApTopOfStack);\r
// Restore AP's volatile registers saved\r
//\r
RestoreVolatileRegisters (&CpuMpData->CpuData[ProcessorNumber].VolatileRegisters, TRUE);\r
+ } else {\r
+ //\r
+ // The CPU driver might not flush TLB for APs on spot after updating\r
+ // page attributes. AP in mwait loop mode needs to take care of it when\r
+ // woken up.\r
+ //\r
+ CpuFlushTlb ();\r
}\r
\r
if (GetApState (&CpuMpData->CpuData[ProcessorNumber]) == CpuStateReady) {\r
SetApState (&CpuMpData->CpuData[ProcessorNumber], CpuStateBusy);\r
//\r
// Enable source debugging on AP function\r
- // \r
+ //\r
EnableDebugAgent ();\r
//\r
// Invoke AP function here\r
ApStartupSignalBuffer = CpuMpData->CpuData[ProcessorNumber].StartupApSignal;\r
CpuInfoInHob[ProcessorNumber].ApTopOfStack = CpuInfoInHob[CpuMpData->NewBspNumber].ApTopOfStack;\r
} else {\r
- //\r
- // Re-get the CPU APICID and Initial APICID\r
- //\r
- CpuInfoInHob[ProcessorNumber].ApicId = GetApicId ();\r
- CpuInfoInHob[ProcessorNumber].InitialApicId = GetInitialApicId ();\r
+ if (CpuInfoInHob[ProcessorNumber].ApicId != GetApicId () ||\r
+ CpuInfoInHob[ProcessorNumber].InitialApicId != GetInitialApicId ()) {\r
+ if (CurrentApicMode != GetApicMode ()) {\r
+ //\r
+ // If APIC mode change happened during AP function execution,\r
+ // we do not support APIC ID value changed.\r
+ //\r
+ ASSERT (FALSE);\r
+ CpuDeadLoop ();\r
+ } else {\r
+ //\r
+ // Re-get the CPU APICID and Initial APICID if they are changed\r
+ //\r
+ CpuInfoInHob[ProcessorNumber].ApicId = GetApicId ();\r
+ CpuInfoInHob[ProcessorNumber].InitialApicId = GetInitialApicId ();\r
+ }\r
+ }\r
}\r
}\r
SetApState (&CpuMpData->CpuData[ProcessorNumber], CpuStateFinished);\r
// AP finished executing C code\r
//\r
InterlockedIncrement ((UINT32 *) &CpuMpData->FinishedCount);\r
+ InterlockedDecrement ((UINT32 *) &CpuMpData->MpCpuExchangeInfo->NumApsExecuting);\r
\r
//\r
// Place AP is specified loop mode\r
)\r
{\r
volatile MP_CPU_EXCHANGE_INFO *ExchangeInfo;\r
+ UINTN Size;\r
+ IA32_SEGMENT_DESCRIPTOR *Selector;\r
\r
ExchangeInfo = CpuMpData->MpCpuExchangeInfo;\r
ExchangeInfo->Lock = 0;\r
ExchangeInfo->Cr3 = AsmReadCr3 ();\r
\r
ExchangeInfo->CFunction = (UINTN) ApWakeupFunction;\r
+ ExchangeInfo->ApIndex = 0;\r
ExchangeInfo->NumApsExecuting = 0;\r
ExchangeInfo->InitFlag = (UINTN) CpuMpData->InitFlag;\r
ExchangeInfo->CpuInfo = (CPU_INFO_IN_HOB *) (UINTN) CpuMpData->CpuInfoInHob;\r
\r
ExchangeInfo->EnableExecuteDisable = IsBspExecuteDisableEnabled ();\r
\r
+ ExchangeInfo->InitializeFloatingPointUnitsAddress = (UINTN)InitializeFloatingPointUnits;\r
+\r
//\r
// Get the BSP's data of GDT and IDT\r
//\r
AsmReadGdtr ((IA32_DESCRIPTOR *) &ExchangeInfo->GdtrProfile);\r
AsmReadIdtr ((IA32_DESCRIPTOR *) &ExchangeInfo->IdtrProfile);\r
+\r
+ //\r
+ // Find a 32-bit code segment\r
+ //\r
+ Selector = (IA32_SEGMENT_DESCRIPTOR *)ExchangeInfo->GdtrProfile.Base;\r
+ Size = ExchangeInfo->GdtrProfile.Limit + 1;\r
+ while (Size > 0) {\r
+ if (Selector->Bits.L == 0 && Selector->Bits.Type >= 8) {\r
+ ExchangeInfo->ModeTransitionSegment =\r
+ (UINT16)((UINTN)Selector - ExchangeInfo->GdtrProfile.Base);\r
+ break;\r
+ }\r
+ Selector += 1;\r
+ Size -= sizeof (IA32_SEGMENT_DESCRIPTOR);\r
+ }\r
+\r
+ //\r
+ // Copy all 32-bit code and 64-bit code into memory with type of\r
+ // EfiBootServicesCode to avoid page fault if NX memory protection is enabled.\r
+ //\r
+ if (CpuMpData->WakeupBufferHigh != 0) {\r
+ Size = CpuMpData->AddressMap.RendezvousFunnelSize -\r
+ CpuMpData->AddressMap.ModeTransitionOffset;\r
+ CopyMem (\r
+ (VOID *)CpuMpData->WakeupBufferHigh,\r
+ CpuMpData->AddressMap.RendezvousFunnelAddress +\r
+ CpuMpData->AddressMap.ModeTransitionOffset,\r
+ Size\r
+ );\r
+\r
+ ExchangeInfo->ModeTransitionMemory = (UINT32)CpuMpData->WakeupBufferHigh;\r
+ } else {\r
+ ExchangeInfo->ModeTransitionMemory = (UINT32)\r
+ (ExchangeInfo->BufferStart + CpuMpData->AddressMap.ModeTransitionOffset);\r
+ }\r
+\r
+ ExchangeInfo->ModeHighMemory = ExchangeInfo->ModeTransitionMemory +\r
+ (UINT32)ExchangeInfo->ModeOffset -\r
+ (UINT32)CpuMpData->AddressMap.ModeTransitionOffset;\r
+ ExchangeInfo->ModeHighSegment = (UINT16)ExchangeInfo->CodeSegment;\r
}\r
\r
/**\r
IN UINT32 TimeLimit\r
);\r
\r
+/**\r
+ Get available system memory below 1MB by specified size.\r
+\r
+ @param[in] CpuMpData The pointer to CPU MP Data structure.\r
+**/\r
+VOID\r
+BackupAndPrepareWakeupBuffer(\r
+ IN CPU_MP_DATA *CpuMpData\r
+ )\r
+{\r
+ CopyMem (\r
+ (VOID *) CpuMpData->BackupBuffer,\r
+ (VOID *) CpuMpData->WakeupBuffer,\r
+ CpuMpData->BackupBufferSize\r
+ );\r
+ CopyMem (\r
+ (VOID *) CpuMpData->WakeupBuffer,\r
+ (VOID *) CpuMpData->AddressMap.RendezvousFunnelAddress,\r
+ CpuMpData->AddressMap.RendezvousFunnelSize\r
+ );\r
+}\r
+\r
+/**\r
+ Restore wakeup buffer data.\r
+\r
+ @param[in] CpuMpData The pointer to CPU MP Data structure.\r
+**/\r
+VOID\r
+RestoreWakeupBuffer(\r
+ IN CPU_MP_DATA *CpuMpData\r
+ )\r
+{\r
+ CopyMem (\r
+ (VOID *) CpuMpData->WakeupBuffer,\r
+ (VOID *) CpuMpData->BackupBuffer,\r
+ CpuMpData->BackupBufferSize\r
+ );\r
+}\r
+\r
+/**\r
+ Allocate reset vector buffer.\r
+\r
+ @param[in, out] CpuMpData The pointer to CPU MP Data structure.\r
+**/\r
+VOID\r
+AllocateResetVector (\r
+ IN OUT CPU_MP_DATA *CpuMpData\r
+ )\r
+{\r
+ UINTN ApResetVectorSize;\r
+\r
+ if (CpuMpData->WakeupBuffer == (UINTN) -1) {\r
+ ApResetVectorSize = CpuMpData->AddressMap.RendezvousFunnelSize +\r
+ sizeof (MP_CPU_EXCHANGE_INFO);\r
+\r
+ CpuMpData->WakeupBuffer = GetWakeupBuffer (ApResetVectorSize);\r
+ CpuMpData->MpCpuExchangeInfo = (MP_CPU_EXCHANGE_INFO *) (UINTN)\r
+ (CpuMpData->WakeupBuffer + CpuMpData->AddressMap.RendezvousFunnelSize);\r
+ CpuMpData->WakeupBufferHigh = GetModeTransitionBuffer (\r
+ CpuMpData->AddressMap.RendezvousFunnelSize -\r
+ CpuMpData->AddressMap.ModeTransitionOffset\r
+ );\r
+ }\r
+ BackupAndPrepareWakeupBuffer (CpuMpData);\r
+}\r
+\r
+/**\r
+ Free AP reset vector buffer.\r
+\r
+ @param[in] CpuMpData The pointer to CPU MP Data structure.\r
+**/\r
+VOID\r
+FreeResetVector (\r
+ IN CPU_MP_DATA *CpuMpData\r
+ )\r
+{\r
+ RestoreWakeupBuffer (CpuMpData);\r
+}\r
+\r
/**\r
This function will be called by BSP to wakeup AP.\r
\r
CpuMpData->FinishedCount = 0;\r
ResetVectorRequired = FALSE;\r
\r
- if (CpuMpData->ApLoopMode == ApInHltLoop ||\r
+ if (CpuMpData->WakeUpByInitSipiSipi ||\r
CpuMpData->InitFlag != ApInitDone) {\r
ResetVectorRequired = TRUE;\r
AllocateResetVector (CpuMpData);\r
FillExchangeInfoData (CpuMpData);\r
SaveLocalApicTimerSetting (CpuMpData);\r
- } else if (CpuMpData->ApLoopMode == ApInMwaitLoop) {\r
+ }\r
+\r
+ if (CpuMpData->ApLoopMode == ApInMwaitLoop) {\r
//\r
// Get AP target C-state each time when waking up AP,\r
// for it maybe updated by platform again\r
}\r
if (CpuMpData->InitFlag == ApInitConfig) {\r
//\r
- // Wait for all potential APs waken up in one specified period\r
+ // Here support two methods to collect AP count through adjust\r
+ // PcdCpuApInitTimeOutInMicroSeconds values.\r
+ //\r
+ // one way is set a value to just let the first AP to start the\r
+ // initialization, then through the later while loop to wait all Aps\r
+ // finsh the initialization.\r
+ // The other way is set a value to let all APs finished the initialzation.\r
+ // In this case, the later while loop is useless.\r
//\r
TimedWaitForApFinish (\r
CpuMpData,\r
PcdGet32 (PcdCpuMaxLogicalProcessorNumber) - 1,\r
PcdGet32 (PcdCpuApInitTimeOutInMicroSeconds)\r
);\r
+\r
+ while (CpuMpData->MpCpuExchangeInfo->NumApsExecuting != 0) {\r
+ CpuPause();\r
+ }\r
} else {\r
//\r
// Wait all APs waken up if this is not the 1st broadcast of SIPI\r
if (ResetVectorRequired) {\r
FreeResetVector (CpuMpData);\r
}\r
+\r
+ //\r
+ // After one round of Wakeup Ap actions, need to re-sync ApLoopMode with\r
+ // WakeUpByInitSipiSipi flag. WakeUpByInitSipiSipi flag maybe changed by\r
+ // S3SmmInitDone Ppi.\r
+ //\r
+ CpuMpData->WakeUpByInitSipiSipi = (CpuMpData->ApLoopMode == ApInHltLoop);\r
}\r
\r
/**\r
OUT UINT64 *CurrentTime\r
)\r
{\r
+ UINT64 TimeoutInSeconds;\r
+ UINT64 TimestampCounterFreq;\r
+\r
//\r
// Read the current value of the performance counter\r
//\r
\r
//\r
// GetPerformanceCounterProperties () returns the timestamp counter's frequency\r
- // in Hz. So multiply the return value with TimeoutInMicroseconds and then divide\r
- // it by 1,000,000, to get the number of ticks for the timeout value.\r
- //\r
- return DivU64x32 (\r
- MultU64x64 (\r
- GetPerformanceCounterProperties (NULL, NULL),\r
- TimeoutInMicroseconds\r
- ),\r
- 1000000\r
- );\r
+ // in Hz.\r
+ //\r
+ TimestampCounterFreq = GetPerformanceCounterProperties (NULL, NULL);\r
+\r
+ //\r
+ // Check the potential overflow before calculate the number of ticks for the timeout value.\r
+ //\r
+ if (DivU64x64Remainder (MAX_UINT64, TimeoutInMicroseconds, NULL) < TimestampCounterFreq) {\r
+ //\r
+ // Convert microseconds into seconds if direct multiplication overflows\r
+ //\r
+ TimeoutInSeconds = DivU64x32 (TimeoutInMicroseconds, 1000000);\r
+ //\r
+ // Assertion if the final tick count exceeds MAX_UINT64\r
+ //\r
+ ASSERT (DivU64x64Remainder (MAX_UINT64, TimeoutInSeconds, NULL) >= TimestampCounterFreq);\r
+ return MultU64x64 (TimestampCounterFreq, TimeoutInSeconds);\r
+ } else {\r
+ //\r
+ // No overflow case, multiply the return value with TimeoutInMicroseconds and then divide\r
+ // it by 1,000,000, to get the number of ticks for the timeout value.\r
+ //\r
+ return DivU64x32 (\r
+ MultU64x64 (\r
+ TimestampCounterFreq,\r
+ TimeoutInMicroseconds\r
+ ),\r
+ 1000000\r
+ );\r
+ }\r
}\r
\r
/**\r
UINT32 MaxLogicalProcessorNumber;\r
UINT32 ApStackSize;\r
MP_ASSEMBLY_ADDRESS_MAP AddressMap;\r
+ CPU_VOLATILE_REGISTERS VolatileRegisters;\r
UINTN BufferSize;\r
UINT32 MonitorFilterSize;\r
VOID *MpBuffer;\r
UINTN Index;\r
UINTN ApResetVectorSize;\r
UINTN BackupBufferAddr;\r
+ UINTN ApIdtBase;\r
+ VOID *MicrocodePatchInRam;\r
\r
OldCpuMpData = GetCpuMpDataFromGuidedHob ();\r
if (OldCpuMpData == NULL) {\r
ApStackSize = PcdGet32(PcdCpuApStackSize);\r
ApLoopMode = GetApLoopMode (&MonitorFilterSize);\r
\r
+ //\r
+ // Save BSP's Control registers for APs\r
+ //\r
+ SaveVolatileRegisters (&VolatileRegisters);\r
+\r
BufferSize = ApStackSize * MaxLogicalProcessorNumber;\r
BufferSize += MonitorFilterSize * MaxLogicalProcessorNumber;\r
- BufferSize += sizeof (CPU_MP_DATA);\r
BufferSize += ApResetVectorSize;\r
+ BufferSize = ALIGN_VALUE (BufferSize, 8);\r
+ BufferSize += VolatileRegisters.Idtr.Limit + 1;\r
+ BufferSize += sizeof (CPU_MP_DATA);\r
BufferSize += (sizeof (CPU_AP_DATA) + sizeof (CPU_INFO_IN_HOB))* MaxLogicalProcessorNumber;\r
MpBuffer = AllocatePages (EFI_SIZE_TO_PAGES (BufferSize));\r
ASSERT (MpBuffer != NULL);\r
ZeroMem (MpBuffer, BufferSize);\r
Buffer = (UINTN) MpBuffer;\r
\r
+ //\r
+ // The layout of the Buffer is as below:\r
+ //\r
+ // +--------------------+ <-- Buffer\r
+ // AP Stacks (N)\r
+ // +--------------------+ <-- MonitorBuffer\r
+ // AP Monitor Filters (N)\r
+ // +--------------------+ <-- BackupBufferAddr (CpuMpData->BackupBuffer)\r
+ // Backup Buffer\r
+ // +--------------------+\r
+ // Padding\r
+ // +--------------------+ <-- ApIdtBase (8-byte boundary)\r
+ // AP IDT All APs share one separate IDT. So AP can get address of CPU_MP_DATA from IDT Base.\r
+ // +--------------------+ <-- CpuMpData\r
+ // CPU_MP_DATA\r
+ // +--------------------+ <-- CpuMpData->CpuData\r
+ // CPU_AP_DATA (N)\r
+ // +--------------------+ <-- CpuMpData->CpuInfoInHob\r
+ // CPU_INFO_IN_HOB (N)\r
+ // +--------------------+\r
+ //\r
MonitorBuffer = (UINT8 *) (Buffer + ApStackSize * MaxLogicalProcessorNumber);\r
BackupBufferAddr = (UINTN) MonitorBuffer + MonitorFilterSize * MaxLogicalProcessorNumber;\r
- CpuMpData = (CPU_MP_DATA *) (BackupBufferAddr + ApResetVectorSize);\r
+ ApIdtBase = ALIGN_VALUE (BackupBufferAddr + ApResetVectorSize, 8);\r
+ CpuMpData = (CPU_MP_DATA *) (ApIdtBase + VolatileRegisters.Idtr.Limit + 1);\r
CpuMpData->Buffer = Buffer;\r
CpuMpData->CpuApStackSize = ApStackSize;\r
CpuMpData->BackupBuffer = BackupBufferAddr;\r
CpuMpData->BackupBufferSize = ApResetVectorSize;\r
- CpuMpData->SaveRestoreFlag = FALSE;\r
CpuMpData->WakeupBuffer = (UINTN) -1;\r
CpuMpData->CpuCount = 1;\r
CpuMpData->BspNumber = 0;\r
CpuMpData->SwitchBspFlag = FALSE;\r
CpuMpData->CpuData = (CPU_AP_DATA *) (CpuMpData + 1);\r
CpuMpData->CpuInfoInHob = (UINT64) (UINTN) (CpuMpData->CpuData + MaxLogicalProcessorNumber);\r
+ CpuMpData->MicrocodePatchRegionSize = PcdGet64 (PcdCpuMicrocodePatchRegionSize);\r
+ //\r
+ // If platform has more than one CPU, relocate microcode to memory to reduce\r
+ // loading microcode time.\r
+ //\r
+ MicrocodePatchInRam = NULL;\r
+ if (MaxLogicalProcessorNumber > 1) {\r
+ MicrocodePatchInRam = AllocatePages (\r
+ EFI_SIZE_TO_PAGES (\r
+ (UINTN)CpuMpData->MicrocodePatchRegionSize\r
+ )\r
+ );\r
+ }\r
+ if (MicrocodePatchInRam == NULL) {\r
+ //\r
+ // there is only one processor, or no microcode patch is available, or\r
+ // memory allocation failed\r
+ //\r
+ CpuMpData->MicrocodePatchAddress = PcdGet64 (PcdCpuMicrocodePatchAddress);\r
+ } else {\r
+ //\r
+ // there are multiple processors, and a microcode patch is available, and\r
+ // memory allocation succeeded\r
+ //\r
+ CopyMem (\r
+ MicrocodePatchInRam,\r
+ (VOID *)(UINTN)PcdGet64 (PcdCpuMicrocodePatchAddress),\r
+ (UINTN)CpuMpData->MicrocodePatchRegionSize\r
+ );\r
+ CpuMpData->MicrocodePatchAddress = (UINTN)MicrocodePatchInRam;\r
+ }\r
+\r
InitializeSpinLock(&CpuMpData->MpLock);\r
+\r
+ //\r
+ // Make sure no memory usage outside of the allocated buffer.\r
+ //\r
+ ASSERT ((CpuMpData->CpuInfoInHob + sizeof (CPU_INFO_IN_HOB) * MaxLogicalProcessorNumber) ==\r
+ Buffer + BufferSize);\r
+\r
//\r
- // Save BSP's Control registers to APs\r
+ // Duplicate BSP's IDT to APs.\r
+ // All APs share one separate IDT. So AP can get the address of CpuMpData by using IDTR.BASE + IDTR.LIMIT + 1\r
//\r
- SaveVolatileRegisters (&CpuMpData->CpuData[0].VolatileRegisters);\r
+ CopyMem ((VOID *)ApIdtBase, (VOID *)VolatileRegisters.Idtr.Base, VolatileRegisters.Idtr.Limit + 1);\r
+ VolatileRegisters.Idtr.Base = ApIdtBase;\r
+ CopyMem (&CpuMpData->CpuData[0].VolatileRegisters, &VolatileRegisters, sizeof (VolatileRegisters));\r
//\r
// Set BSP basic information\r
//\r
- InitializeApData (CpuMpData, 0, 0, CpuMpData->Buffer);\r
+ InitializeApData (CpuMpData, 0, 0, CpuMpData->Buffer + ApStackSize);\r
//\r
// Save assembly code information\r
//\r
//\r
CpuMpData->ApLoopMode = ApLoopMode;\r
DEBUG ((DEBUG_INFO, "AP Loop Mode is %d\n", CpuMpData->ApLoopMode));\r
+\r
+ CpuMpData->WakeUpByInitSipiSipi = (CpuMpData->ApLoopMode == ApInHltLoop);\r
+\r
//\r
// Set up APs wakeup signal buffer\r
//\r
//\r
// Load Microcode on BSP\r
//\r
- MicrocodeDetect (CpuMpData);\r
+ MicrocodeDetect (CpuMpData, TRUE);\r
//\r
// Store BSP's MTRR setting\r
//\r
MtrrGetAllMtrrs (&CpuMpData->MtrrTable);\r
+ //\r
+ // Enable the local APIC for Virtual Wire Mode.\r
+ //\r
+ ProgramVirtualWireMode ();\r
\r
if (OldCpuMpData == NULL) {\r
if (MaxLogicalProcessorNumber > 1) {\r
CpuInfoInHob = (CPU_INFO_IN_HOB *) (UINTN) CpuMpData->CpuInfoInHob;\r
for (Index = 0; Index < CpuMpData->CpuCount; Index++) {\r
InitializeSpinLock(&CpuMpData->CpuData[Index].ApLock);\r
- if (CpuInfoInHob[Index].InitialApicId >= 255) {\r
+ if (CpuInfoInHob[Index].InitialApicId >= 255 || Index > 254) {\r
CpuMpData->X2ApicEnable = TRUE;\r
}\r
CpuMpData->CpuData[Index].CpuHealthy = (CpuInfoInHob[Index].Health == 0)? TRUE:FALSE;\r
CpuMpData->CpuData[Index].ApFunction = 0;\r
- CopyMem (\r
- &CpuMpData->CpuData[Index].VolatileRegisters,\r
- &CpuMpData->CpuData[0].VolatileRegisters,\r
- sizeof (CPU_VOLATILE_REGISTERS)\r
- );\r
+ CopyMem (&CpuMpData->CpuData[Index].VolatileRegisters, &VolatileRegisters, sizeof (CPU_VOLATILE_REGISTERS));\r
}\r
if (MaxLogicalProcessorNumber > 1) {\r
//\r
enabled AP. Otherwise, it will be disabled.\r
\r
@retval EFI_SUCCESS BSP successfully switched.\r
- @retval others Failed to switch BSP. \r
+ @retval others Failed to switch BSP.\r
\r
**/\r
EFI_STATUS\r
UINTN CallerNumber;\r
CPU_STATE State;\r
MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr;\r
+ BOOLEAN OldInterruptState;\r
+ BOOLEAN OldTimerInterruptState;\r
+\r
+ //\r
+ // Save and Disable Local APIC timer interrupt\r
+ //\r
+ OldTimerInterruptState = GetApicTimerInterruptState ();\r
+ DisableApicTimerInterrupt ();\r
+ //\r
+ // Before send both BSP and AP to a procedure to exchange their roles,\r
+ // interrupt must be disabled. This is because during the exchange role\r
+ // process, 2 CPU may use 1 stack. If interrupt happens, the stack will\r
+ // be corrupted, since interrupt return address will be pushed to stack\r
+ // by hardware.\r
+ //\r
+ OldInterruptState = SaveAndDisableInterrupts ();\r
+\r
+ //\r
+ // Mask LINT0 & LINT1 for the old BSP\r
+ //\r
+ DisableLvtInterrupts ();\r
\r
CpuMpData = GetCpuMpData ();\r
\r
//\r
MpInitLibWhoAmI (&CallerNumber);\r
if (CallerNumber != CpuMpData->BspNumber) {\r
- return EFI_SUCCESS;\r
+ return EFI_DEVICE_ERROR;\r
}\r
\r
if (ProcessorNumber >= CpuMpData->CpuCount) {\r
ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);\r
ApicBaseMsr.Bits.BSP = 1;\r
AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64);\r
+ ProgramVirtualWireMode ();\r
\r
//\r
// Wait for old BSP finished AP task\r
//\r
if (!EnableOldBSP) {\r
SetApState (&CpuMpData->CpuData[CallerNumber], CpuStateDisabled);\r
+ } else {\r
+ SetApState (&CpuMpData->CpuData[CallerNumber], CpuStateIdle);\r
}\r
//\r
// Save new BSP number\r
//\r
CpuMpData->BspNumber = (UINT32) ProcessorNumber;\r
\r
+ //\r
+ // Restore interrupt state.\r
+ //\r
+ SetInterruptState (OldInterruptState);\r
+\r
+ if (OldTimerInterruptState) {\r
+ EnableApicTimerInterrupt ();\r
+ }\r
+\r
return EFI_SUCCESS;\r
}\r
\r
if (!EnableAP) {\r
SetApState (&CpuMpData->CpuData[ProcessorNumber], CpuStateDisabled);\r
} else {\r
- SetApState (&CpuMpData->CpuData[ProcessorNumber], CpuStateIdle);\r
+ ResetProcessorToIdleState (ProcessorNumber);\r
}\r
\r
if (HealthFlag != NULL) {\r
return CpuMpData;\r
}\r
\r
-/**\r
- Get available system memory below 1MB by specified size.\r
-\r
- @param[in] CpuMpData The pointer to CPU MP Data structure.\r
-**/\r
-VOID\r
-BackupAndPrepareWakeupBuffer(\r
- IN CPU_MP_DATA *CpuMpData\r
- )\r
-{\r
- CopyMem (\r
- (VOID *) CpuMpData->BackupBuffer,\r
- (VOID *) CpuMpData->WakeupBuffer,\r
- CpuMpData->BackupBufferSize\r
- );\r
- CopyMem (\r
- (VOID *) CpuMpData->WakeupBuffer,\r
- (VOID *) CpuMpData->AddressMap.RendezvousFunnelAddress,\r
- CpuMpData->AddressMap.RendezvousFunnelSize\r
- );\r
-}\r
-\r
-/**\r
- Restore wakeup buffer data.\r
-\r
- @param[in] CpuMpData The pointer to CPU MP Data structure.\r
-**/\r
-VOID\r
-RestoreWakeupBuffer(\r
- IN CPU_MP_DATA *CpuMpData\r
- )\r
-{\r
- CopyMem (\r
- (VOID *) CpuMpData->WakeupBuffer,\r
- (VOID *) CpuMpData->BackupBuffer,\r
- CpuMpData->BackupBufferSize\r
- );\r
-}\r
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