UefiCpuPkg: Move GetProcessorLocation() to LocalApicLib library

[mirror_edk2.git] / UefiCpuPkg / Library / MpInitLib / MpLib.c

diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c b/UefiCpuPkg/Library/MpInitLib/MpLib.c
index c3fe72138fb564f5e42488d64e72fc427ef3c005..f205b6bad4ccff9018a593f9d4c78e03d69530c8 100644 (file)
--- a/UefiCpuPkg/Library/MpInitLib/MpLib.c
+++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c
@@ -57,132 +57,6 @@ IsBspExecuteDisableEnabled (
   return Enabled;\r
 }\r
 \r
-/**\r
-  Get CPU Package/Core/Thread location information.\r
-\r
-  @param[in]  InitialApicId     CPU APIC ID\r
-  @param[out] Location          Pointer to CPU location information\r
-**/\r
-VOID\r
-ExtractProcessorLocation (\r
-  IN  UINT32                     InitialApicId,\r
-  OUT EFI_CPU_PHYSICAL_LOCATION  *Location\r
-  )\r
-{\r
-  BOOLEAN                        TopologyLeafSupported;\r
-  UINTN                          ThreadBits;\r
-  UINTN                          CoreBits;\r
-  CPUID_VERSION_INFO_EBX         VersionInfoEbx;\r
-  CPUID_VERSION_INFO_EDX         VersionInfoEdx;\r
-  CPUID_CACHE_PARAMS_EAX         CacheParamsEax;\r
-  CPUID_EXTENDED_TOPOLOGY_EAX    ExtendedTopologyEax;\r
-  CPUID_EXTENDED_TOPOLOGY_EBX    ExtendedTopologyEbx;\r
-  CPUID_EXTENDED_TOPOLOGY_ECX    ExtendedTopologyEcx;\r
-  UINT32                         MaxCpuIdIndex;\r
-  UINT32                         SubIndex;\r
-  UINTN                          LevelType;\r
-  UINT32                         MaxLogicProcessorsPerPackage;\r
-  UINT32                         MaxCoresPerPackage;\r
-\r
-  //\r
-  // Check if the processor is capable of supporting more than one logical processor.\r
-  //\r
-  AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, &VersionInfoEdx.Uint32);\r
-  if (VersionInfoEdx.Bits.HTT == 0) {\r
-    Location->Thread  = 0;\r
-    Location->Core    = 0;\r
-    Location->Package = 0;\r
-    return;\r
-  }\r
-\r
-  ThreadBits = 0;\r
-  CoreBits = 0;\r
-\r
-  //\r
-  // Assume three-level mapping of APIC ID: Package:Core:SMT.\r
-  //\r
-\r
-  TopologyLeafSupported = FALSE;\r
-  //\r
-  // Get the max index of basic CPUID\r
-  //\r
-  AsmCpuid (CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);\r
-\r
-  //\r
-  // If the extended topology enumeration leaf is available, it\r
-  // is the preferred mechanism for enumerating topology.\r
-  //\r
-  if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {\r
-    AsmCpuidEx (\r
-      CPUID_EXTENDED_TOPOLOGY,\r
-      0,\r
-      &ExtendedTopologyEax.Uint32,\r
-      &ExtendedTopologyEbx.Uint32,\r
-      &ExtendedTopologyEcx.Uint32,\r
-      NULL\r
-      );\r
-    //\r
-    // If CPUID.(EAX=0BH, ECX=0H):EBX returns zero and maximum input value for\r
-    // basic CPUID information is greater than 0BH, then CPUID.0BH leaf is not\r
-    // supported on that processor.\r
-    //\r
-    if (ExtendedTopologyEbx.Uint32 != 0) {\r
-      TopologyLeafSupported = TRUE;\r
-\r
-      //\r
-      // Sub-leaf index 0 (ECX= 0 as input) provides enumeration parameters to extract\r
-      // the SMT sub-field of x2APIC ID.\r
-      //\r
-      LevelType = ExtendedTopologyEcx.Bits.LevelType;\r
-      ASSERT (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT);\r
-      ThreadBits = ExtendedTopologyEax.Bits.ApicIdShift;\r
-\r
-      //\r
-      // Software must not assume any "level type" encoding\r
-      // value to be related to any sub-leaf index, except sub-leaf 0.\r
-      //\r
-      SubIndex = 1;\r
-      do {\r
-        AsmCpuidEx (\r
-          CPUID_EXTENDED_TOPOLOGY,\r
-          SubIndex,\r
-          &ExtendedTopologyEax.Uint32,\r
-          NULL,\r
-          &ExtendedTopologyEcx.Uint32,\r
-          NULL\r
-          );\r
-        LevelType = ExtendedTopologyEcx.Bits.LevelType;\r
-        if (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) {\r
-          CoreBits = ExtendedTopologyEax.Bits.ApicIdShift - ThreadBits;\r
-          break;\r
-        }\r
-        SubIndex++;\r
-      } while (LevelType != CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);\r
-    }\r
-  }\r
-\r
-  if (!TopologyLeafSupported) {\r
-    AsmCpuid (CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL);\r
-    MaxLogicProcessorsPerPackage = VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;\r
-    if (MaxCpuIdIndex >= CPUID_CACHE_PARAMS) {\r
-      AsmCpuidEx (CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL, NULL);\r
-      MaxCoresPerPackage = CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1;\r
-    } else {\r
-      //\r
-      // Must be a single-core processor.\r
-      //\r
-      MaxCoresPerPackage = 1;\r
-    }\r
-\r
-    ThreadBits = (UINTN) (HighBitSet32 (MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1);\r
-    CoreBits = (UINTN) (HighBitSet32 (MaxCoresPerPackage - 1) + 1);\r
-  }\r
-\r
-  Location->Thread  = InitialApicId & ((1 << ThreadBits) - 1);\r
-  Location->Core    = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);\r
-  Location->Package = (InitialApicId >> (ThreadBits + CoreBits));\r
-}\r
-\r
 /**\r
   Worker function for SwitchBSP().\r
 \r
@@ -1451,7 +1325,12 @@ MpInitLibGetProcessorInfo (
   //\r
   // Get processor location information\r
   //\r
-  ExtractProcessorLocation (CpuMpData->CpuData[ProcessorNumber].ApicId, &ProcessorInfoBuffer->Location);\r
+  GetProcessorLocation (\r
+    CpuMpData->CpuData[ProcessorNumber].ApicId,\r
+    &ProcessorInfoBuffer->Location.Package,\r
+    &ProcessorInfoBuffer->Location.Core,\r
+    &ProcessorInfoBuffer->Location.Thread\r
+    );\r
 \r
   if (HealthData != NULL) {\r
     HealthData->Uint32 = CpuMpData->CpuData[ProcessorNumber].Health;\r