/** @file\r
Common header file for MP Initialize Library.\r
\r
- Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r
- This program and the accompanying materials\r
- are licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php\r
+ Copyright (c) 2016 - 2020, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2020, AMD Inc. All rights reserved.<BR>\r
\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+ SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
\r
#include <PiPei.h>\r
\r
-#include <Register/Cpuid.h>\r
-#include <Register/Msr.h>\r
-#include <Register/LocalApic.h>\r
-#include <Register/Microcode.h>\r
+#include <Register/Intel/Cpuid.h>\r
+#include <Register/Amd/Cpuid.h>\r
+#include <Register/Intel/Msr.h>\r
+#include <Register/Intel/LocalApic.h>\r
+#include <Register/Intel/Microcode.h>\r
\r
#include <Library/MpInitLib.h>\r
#include <Library/BaseLib.h>\r
#include <Library/SynchronizationLib.h>\r
#include <Library/MtrrLib.h>\r
#include <Library/HobLib.h>\r
+#include <Library/PcdLib.h>\r
+\r
+#include <Guid/MicrocodePatchHob.h>\r
\r
#define WAKEUP_AP_SIGNAL SIGNATURE_32 ('S', 'T', 'A', 'P')\r
\r
#define CPU_SWITCH_STATE_STORED 1\r
#define CPU_SWITCH_STATE_LOADED 2\r
\r
+//\r
+// Default maximum number of entries to store the microcode patches information\r
+//\r
+#define DEFAULT_MAX_MICROCODE_PATCH_NUM 8\r
+\r
+//\r
+// Data structure for microcode patch information\r
+//\r
+typedef struct {\r
+ UINTN Address;\r
+ UINTN Size;\r
+} MICROCODE_PATCH_INFO;\r
+\r
//\r
// CPU exchange information for switch BSP\r
//\r
CpuStateIdle,\r
CpuStateReady,\r
CpuStateBusy,\r
+ CpuStateFinished,\r
CpuStateDisabled\r
} CPU_STATE;\r
\r
UINT64 CurrentTime;\r
UINT64 TotalTime;\r
EFI_EVENT WaitEvent;\r
+ UINT32 ProcessorSignature;\r
+ UINT8 PlatformId;\r
+ UINT64 MicrocodeEntryAddr;\r
} CPU_AP_DATA;\r
\r
//\r
UINT16 ModeTransitionSegment;\r
UINT32 ModeHighMemory;\r
UINT16 ModeHighSegment;\r
+ //\r
+ // Enable5LevelPaging indicates whether 5-level paging is enabled in long mode.\r
+ //\r
+ BOOLEAN Enable5LevelPaging;\r
} MP_CPU_EXCHANGE_INFO;\r
\r
#pragma pack()\r
UINTN **FailedCpuList;\r
\r
AP_INIT_STATE InitFlag;\r
- BOOLEAN X2ApicEnable;\r
BOOLEAN SwitchBspFlag;\r
UINTN NewBspNumber;\r
CPU_EXCHANGE_ROLE_INFO BSPInfo;\r
UINT64 MicrocodePatchAddress;\r
UINT64 MicrocodePatchRegionSize;\r
\r
- UINT32 ProcessorSignature;\r
- UINT32 ProcessorFlags;\r
- UINT64 MicrocodeDataAddress;\r
- UINT32 MicrocodeRevision;\r
-\r
//\r
// Whether need to use Init-Sipi-Sipi to wake up the APs.\r
// Two cases need to set this value to TRUE. One is in HLT\r
number. If FALSE, then all the enabled APs\r
execute the function specified by Procedure\r
simultaneously.\r
+ @param[in] ExcludeBsp Whether let BSP also trig this task.\r
@param[in] WaitEvent The event created by the caller with CreateEvent()\r
service.\r
@param[in] TimeoutInMicroseconds Indicates the time limit in microseconds for\r
\r
**/\r
EFI_STATUS\r
-StartupAllAPsWorker (\r
+StartupAllCPUsWorker (\r
IN EFI_AP_PROCEDURE Procedure,\r
IN BOOLEAN SingleThread,\r
+ IN BOOLEAN ExcludeBsp,\r
IN EFI_EVENT WaitEvent OPTIONAL,\r
IN UINTN TimeoutInMicroseconds,\r
IN VOID *ProcedureArgument OPTIONAL,\r
/**\r
Detect whether specified processor can find matching microcode patch and load it.\r
\r
- @param[in] CpuMpData The pointer to CPU MP Data structure.\r
- @param[in] IsBspCallIn Indicate whether the caller is BSP or not.\r
+ @param[in] CpuMpData The pointer to CPU MP Data structure.\r
+ @param[in] ProcessorNumber The handle number of the processor. The range is\r
+ from 0 to the total number of logical processors\r
+ minus 1.\r
**/\r
VOID\r
MicrocodeDetect (\r
IN CPU_MP_DATA *CpuMpData,\r
- IN BOOLEAN IsBspCallIn\r
+ IN UINTN ProcessorNumber\r
+ );\r
+\r
+/**\r
+ Shadow the required microcode patches data into memory.\r
+\r
+ @param[in, out] CpuMpData The pointer to CPU MP Data structure.\r
+**/\r
+VOID\r
+ShadowMicrocodeUpdatePatch (\r
+ IN OUT CPU_MP_DATA *CpuMpData\r
+ );\r
+\r
+/**\r
+ Get the cached microcode patch base address and size from the microcode patch\r
+ information cache HOB.\r
+\r
+ @param[out] Address Base address of the microcode patches data.\r
+ It will be updated if the microcode patch\r
+ information cache HOB is found.\r
+ @param[out] RegionSize Size of the microcode patches data.\r
+ It will be updated if the microcode patch\r
+ information cache HOB is found.\r
+\r
+ @retval TRUE The microcode patch information cache HOB is found.\r
+ @retval FALSE The microcode patch information cache HOB is not found.\r
+\r
+**/\r
+BOOLEAN\r
+GetMicrocodePatchInfoFromHob (\r
+ UINT64 *Address,\r
+ UINT64 *RegionSize\r
);\r
\r
/**\r
VOID\r
);\r
\r
+/**\r
+ Find the current Processor number by APIC ID.\r
+\r
+ @param[in] CpuMpData Pointer to PEI CPU MP Data\r
+ @param[out] ProcessorNumber Return the pocessor number found\r
+\r
+ @retval EFI_SUCCESS ProcessorNumber is found and returned.\r
+ @retval EFI_NOT_FOUND ProcessorNumber is not found.\r
+**/\r
+EFI_STATUS\r
+GetProcessorNumber (\r
+ IN CPU_MP_DATA *CpuMpData,\r
+ OUT UINTN *ProcessorNumber\r
+ );\r
+\r
+/**\r
+ This funtion will try to invoke platform specific microcode shadow logic to\r
+ relocate microcode update patches into memory.\r
+\r
+ @param[in, out] CpuMpData The pointer to CPU MP Data structure.\r
+\r
+ @retval EFI_SUCCESS Shadow microcode success.\r
+ @retval EFI_OUT_OF_RESOURCES No enough resource to complete the operation.\r
+ @retval EFI_UNSUPPORTED Can't find platform specific microcode shadow\r
+ PPI/Protocol.\r
+**/\r
+EFI_STATUS\r
+PlatformShadowMicrocode (\r
+ IN OUT CPU_MP_DATA *CpuMpData\r
+ );\r
+\r
#endif\r
\r
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