/** @file\r
MTRR setting library\r
\r
- Copyright (c) 2008 - 2010, Intel Corporation\r
- All rights reserved. This program and the accompanying materials\r
+ Copyright (c) 2008 - 2010, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
http://opensource.org/licenses/bsd-license.php\r
\r
**/\r
UINT32\r
+EFIAPI\r
GetVariableMtrrCount (\r
VOID\r
)\r
{\r
+ if (!IsMtrrSupported ()) {\r
+ return 0;\r
+ }\r
+\r
return (UINT32)(AsmReadMsr64 (MTRR_LIB_IA32_MTRR_CAP) & MTRR_LIB_IA32_MTRR_CAP_VCNT_MASK);\r
}\r
\r
\r
**/\r
UINT32\r
+EFIAPI\r
GetFirmwareVariableMtrrCount (\r
VOID\r
)\r
{\r
- return GetVariableMtrrCount () - RESERVED_FIRMWARE_VARIABLE_MTRR_NUMBER;\r
+ UINT32 VariableMtrrCount;\r
+\r
+ VariableMtrrCount = GetVariableMtrrCount ();\r
+ if (VariableMtrrCount < RESERVED_FIRMWARE_VARIABLE_MTRR_NUMBER) {\r
+ return 0;\r
+ }\r
+\r
+ return VariableMtrrCount - RESERVED_FIRMWARE_VARIABLE_MTRR_NUMBER;\r
}\r
\r
/**\r
//\r
// Enter no fill cache mode, CD=1(Bit30), NW=0 (Bit29)\r
//\r
- Value = AsmReadCr0 ();\r
- Value = (UINTN) BitFieldWrite64 (Value, 30, 30, 1);\r
- Value = (UINTN) BitFieldWrite64 (Value, 29, 29, 0);\r
- AsmWriteCr0 (Value);\r
- //\r
- // Flush cache\r
- //\r
- AsmWbinvd ();\r
+ AsmDisableCache ();\r
+\r
//\r
- // Clear PGE flag Bit 7\r
+ // Save original CR4 value and clear PGE flag (Bit 7)\r
//\r
Value = AsmReadCr4 ();\r
- AsmWriteCr4 ((UINTN) BitFieldWrite64 (Value, 7, 7, 0));\r
+ AsmWriteCr4 (Value & (~BIT7));\r
+\r
//\r
// Flush all TLBs\r
//\r
CpuFlushTlb ();\r
+\r
//\r
// Disable Mtrrs\r
//\r
AsmMsrBitFieldWrite64 (MTRR_LIB_IA32_MTRR_DEF_TYPE, 10, 11, 0);\r
\r
+ //\r
+ // Return original CR4 value\r
+ //\r
return Value;\r
}\r
\r
UINTN Cr4\r
)\r
{\r
- UINTN Value;\r
-\r
//\r
// Enable Cache MTRR\r
//\r
AsmMsrBitFieldWrite64 (MTRR_LIB_IA32_MTRR_DEF_TYPE, 10, 11, 3);\r
\r
//\r
- // Flush all TLBs and cache the second time\r
+ // Flush all TLBs \r
//\r
- AsmWbinvd ();\r
CpuFlushTlb ();\r
\r
//\r
// Enable Normal Mode caching CD=NW=0, CD(Bit30), NW(Bit29)\r
//\r
- Value = AsmReadCr0 ();\r
- Value = (UINTN) BitFieldWrite64 (Value, 30, 30, 0);\r
- Value = (UINTN) BitFieldWrite64 (Value, 29, 29, 0);\r
- AsmWriteCr0 (Value);\r
+ AsmEnableCache ();\r
\r
+ //\r
+ // Restore original CR4 value\r
+ //\r
AsmWriteCr4 (Cr4);\r
-\r
- return ;\r
}\r
\r
\r
/**\r
Get the attribute of variable MTRRs.\r
\r
- This function shadows the content of variable MTRRs into\r
- an internal array: VariableMtrr\r
+ This function shadows the content of variable MTRRs into an\r
+ internal array: VariableMtrr.\r
\r
- @param MtrrValidBitsMask The mask for the valid bit of the MTRR\r
- @param MtrrValidAddressMask The valid address mask for MTRR since the base address in\r
- MTRR must align to 4K, so valid address mask equal to\r
- MtrrValidBitsMask & 0xfffffffffffff000ULL\r
- @param VariableMtrrCount On input, it means the array number of variable MTRRs passed in.\r
- On output, it means the number of MTRRs which has been used if EFI_SUCCESS,\r
- or the number of MTRR required if BUFFER_TOO_SMALL.\r
- @param VariableMtrr The array to shadow variable MTRRs content\r
+ @param MtrrValidBitsMask The mask for the valid bit of the MTRR\r
+ @param MtrrValidAddressMask The valid address mask for MTRR\r
+ @param VariableMtrr The array to shadow variable MTRRs content\r
\r
- @retval RETURN_SUCCESS The variable MTRRs are returned.\r
- @retval RETURN_BUFFER_TOO_SMALL The input buffer is too small to hold the variable MTRRs.\r
+ @return The return value of this paramter indicates the\r
+ number of MTRRs which has been used.\r
\r
**/\r
-RETURN_STATUS\r
+UINT32\r
EFIAPI\r
MtrrGetMemoryAttributeInVariableMtrr (\r
IN UINT64 MtrrValidBitsMask,\r
IN UINT64 MtrrValidAddressMask,\r
- IN OUT UINT32 *VariableMtrrCount,\r
OUT VARIABLE_MTRR *VariableMtrr\r
)\r
{\r
UINTN Index;\r
UINT32 MsrNum;\r
UINT32 UsedMtrr;\r
- UINTN FirmwareVariableMtrrCount;\r
+ UINT32 FirmwareVariableMtrrCount;\r
UINT32 VariableMtrrEnd;\r
\r
- //\r
- // Check if input buffer is large enough\r
- //\r
- FirmwareVariableMtrrCount = GetFirmwareVariableMtrrCount ();\r
- if (*VariableMtrrCount < FirmwareVariableMtrrCount) {\r
- *VariableMtrrCount = (UINT32)FirmwareVariableMtrrCount;\r
- return RETURN_BUFFER_TOO_SMALL;\r
+ if (!IsMtrrSupported ()) {\r
+ return 0;\r
}\r
\r
+ FirmwareVariableMtrrCount = GetFirmwareVariableMtrrCount ();\r
VariableMtrrEnd = MTRR_LIB_IA32_VARIABLE_MTRR_BASE + (2 * GetVariableMtrrCount ()) - 1;\r
\r
- ZeroMem (VariableMtrr, sizeof (VARIABLE_MTRR) * (*VariableMtrrCount));\r
+ ZeroMem (VariableMtrr, sizeof (VARIABLE_MTRR) * MTRR_NUMBER_OF_VARIABLE_MTRR);\r
UsedMtrr = 0;\r
\r
for (MsrNum = MTRR_LIB_IA32_VARIABLE_MTRR_BASE, Index = 0;\r
Index++;\r
}\r
}\r
- *VariableMtrrCount = UsedMtrr;\r
- return RETURN_SUCCESS;\r
+ return UsedMtrr;\r
}\r
\r
\r
BOOLEAN Positive;\r
UINT32 MsrNum;\r
UINTN MtrrNumber;\r
- VARIABLE_MTRR VariableMtrr[MAX_MTRR_NUMBER_OF_VARIABLE_MTRR];\r
+ VARIABLE_MTRR VariableMtrr[MTRR_NUMBER_OF_VARIABLE_MTRR];\r
UINT32 UsedMtrr;\r
UINT64 MtrrValidBitsMask;\r
UINT64 MtrrValidAddressMask;\r
UINT32 FirmwareVariableMtrrCount;\r
UINT32 VariableMtrrEnd;\r
\r
+ if (!IsMtrrSupported ()) {\r
+ return RETURN_UNSUPPORTED;\r
+ }\r
+\r
FirmwareVariableMtrrCount = GetFirmwareVariableMtrrCount ();\r
VariableMtrrEnd = MTRR_LIB_IA32_VARIABLE_MTRR_BASE + (2 * GetVariableMtrrCount ()) - 1;\r
\r
//\r
// Check for overlap\r
//\r
- UsedMtrr = MAX_MTRR_NUMBER_OF_VARIABLE_MTRR;\r
- MtrrGetMemoryAttributeInVariableMtrr (MtrrValidBitsMask, MtrrValidAddressMask, &UsedMtrr, VariableMtrr);\r
+ UsedMtrr = MtrrGetMemoryAttributeInVariableMtrr (MtrrValidBitsMask, MtrrValidAddressMask, VariableMtrr);\r
OverLap = CheckMemoryAttributeOverlap (BaseAddress, BaseAddress + Length - 1, VariableMtrr);\r
if (OverLap) {\r
Status = CombineMemoryAttribute (MemoryType, &BaseAddress, &Length, VariableMtrr, &UsedMtrr, &OverwriteExistingMtrr);\r
UINT64 MtrrType;\r
UINT64 TempMtrrType;\r
MTRR_MEMORY_CACHE_TYPE CacheType;\r
- VARIABLE_MTRR VariableMtrr[MAX_MTRR_NUMBER_OF_VARIABLE_MTRR];\r
+ VARIABLE_MTRR VariableMtrr[MTRR_NUMBER_OF_VARIABLE_MTRR];\r
UINT64 MtrrValidBitsMask;\r
UINT64 MtrrValidAddressMask;\r
UINTN VariableMtrrCount;\r
- UINT32 UsedMtrr;\r
+\r
+ if (!IsMtrrSupported ()) {\r
+ return CacheUncacheable;\r
+ }\r
\r
//\r
// Check if MTRR is enabled, if not, return UC as attribute\r
}\r
}\r
MtrrLibInitializeMtrrMask(&MtrrValidBitsMask, &MtrrValidAddressMask);\r
- UsedMtrr = MAX_MTRR_NUMBER_OF_VARIABLE_MTRR;\r
MtrrGetMemoryAttributeInVariableMtrr(\r
MtrrValidBitsMask,\r
MtrrValidAddressMask,\r
- &UsedMtrr,\r
VariableMtrr\r
);\r
\r
// Go through the variable MTRR\r
//\r
VariableMtrrCount = GetVariableMtrrCount ();\r
+ ASSERT (VariableMtrrCount <= MTRR_NUMBER_OF_VARIABLE_MTRR);\r
+\r
for (Index = 0; Index < VariableMtrrCount; Index++) {\r
if (VariableMtrr[Index].Valid) {\r
if (Address >= VariableMtrr[Index].BaseAddress &&\r
UINT32 Index;\r
UINT32 VariableMtrrCount;\r
\r
+ if (!IsMtrrSupported ()) {\r
+ return VariableSettings;\r
+ }\r
+\r
VariableMtrrCount = GetVariableMtrrCount ();\r
+ ASSERT (VariableMtrrCount <= MTRR_NUMBER_OF_VARIABLE_MTRR);\r
+\r
for (Index = 0; Index < VariableMtrrCount; Index++) {\r
VariableSettings->Mtrr[Index].Base =\r
AsmReadMsr64 (MTRR_LIB_IA32_VARIABLE_MTRR_BASE + (Index << 1));\r
UINT32 VariableMtrrCount;\r
\r
VariableMtrrCount = GetVariableMtrrCount ();\r
+ ASSERT (VariableMtrrCount <= MTRR_NUMBER_OF_VARIABLE_MTRR);\r
+\r
for (Index = 0; Index < VariableMtrrCount; Index++) {\r
AsmWriteMsr64 (\r
MTRR_LIB_IA32_VARIABLE_MTRR_BASE + (Index << 1),\r
{\r
UINTN Cr4;\r
\r
+ if (!IsMtrrSupported ()) {\r
+ return VariableSettings;\r
+ }\r
+\r
Cr4 = PreMtrrChange ();\r
MtrrSetVariableMtrrWorker (VariableSettings);\r
PostMtrrChange (Cr4);\r
{\r
UINT32 Index;\r
\r
+ if (!IsMtrrSupported ()) {\r
+ return FixedSettings;\r
+ }\r
+\r
for (Index = 0; Index < MTRR_NUMBER_OF_FIXED_MTRR; Index++) {\r
FixedSettings->Mtrr[Index] =\r
AsmReadMsr64 (MtrrLibFixedMtrrTable[Index].Msr);\r
{\r
UINTN Cr4;\r
\r
+ if (!IsMtrrSupported ()) {\r
+ return FixedSettings;\r
+ }\r
+\r
Cr4 = PreMtrrChange ();\r
MtrrSetFixedMtrrWorker (FixedSettings);\r
PostMtrrChange (Cr4);\r
OUT MTRR_SETTINGS *MtrrSetting\r
)\r
{\r
+ if (!IsMtrrSupported ()) {\r
+ return MtrrSetting;\r
+ }\r
+\r
//\r
// Get fixed MTRRs\r
//\r
{\r
UINTN Cr4;\r
\r
+ if (!IsMtrrSupported ()) {\r
+ return MtrrSetting;\r
+ }\r
+\r
Cr4 = PreMtrrChange ();\r
\r
//\r
UINTN Index;\r
UINTN VariableMtrrCount;\r
\r
+ if (!IsMtrrSupported ()) {\r
+ return;\r
+ }\r
+\r
MtrrGetAllMtrrs (&MtrrSettings);\r
DEBUG((EFI_D_ERROR, "DefaultType = %016lx\n", MtrrSettings.MtrrDefType));\r
for (Index = 0; Index < MTRR_NUMBER_OF_FIXED_MTRR; Index++) {\r
);\r
}\r
\r
+/**\r
+ Checks if MTRR is supported.\r
+\r
+ @retval TRUE MTRR is supported.\r
+ @retval FALSE MTRR is not supported.\r
+\r
+**/\r
+BOOLEAN\r
+EFIAPI\r
+IsMtrrSupported (\r
+ VOID\r
+ )\r
+{\r
+ UINT32 RegEdx;\r
+ UINT64 MtrrCap;\r
+\r
+ //\r
+ // Check CPUID(1).EDX[12] for MTRR capability\r
+ //\r
+ AsmCpuid (1, NULL, NULL, NULL, &RegEdx);\r
+ if (BitFieldRead32 (RegEdx, 12, 12) == 0) {\r
+ return FALSE;\r
+ }\r
+\r
+ //\r
+ // Check IA32_MTRRCAP.[0..7] for number of variable MTRRs and IA32_MTRRCAP[8] for\r
+ // fixed MTRRs existence. If number of variable MTRRs is zero, or fixed MTRRs do not\r
+ // exist, return false.\r
+ //\r
+ MtrrCap = AsmReadMsr64 (MTRR_LIB_IA32_MTRR_CAP);\r
+ if ((BitFieldRead64 (MtrrCap, 0, 7) == 0) || (BitFieldRead64 (MtrrCap, 8, 8) == 0)) {\r
+ return FALSE;\r
+ }\r
+\r
+ return TRUE;\r
+}\r
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