UefiCpuPkg: Update SmmCpuFeatureLib pass XCODE5 tool chain

[mirror_edk2.git] / UefiCpuPkg / Library / SmmCpuFeaturesLib / Ia32 / SmiEntry.nasm

diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm
index b1c84a494f7b4c64090899c3772d2101da2544a2..057ec6d10582aa6fde200120fa0384c7dfffffeb 100644 (file)
--- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm
+++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm
@@ -1,5 +1,5 @@
 ;------------------------------------------------------------------------------ ;\r
-; Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r
 ; This program and the accompanying materials\r
 ; are licensed and made available under the terms and conditions of the BSD License\r
 ; which accompanies this distribution.  The full text of the license may be found at\r
@@ -51,6 +51,11 @@ global ASM_PFX(gStmSmbase)
 global ASM_PFX(gStmXdSupported)\r
 extern ASM_PFX(gStmSmiHandlerIdtr)\r
 \r
+ASM_PFX(gStmSmiCr3)      EQU StmSmiCr3Patch - 4\r
+ASM_PFX(gStmSmiStack)    EQU StmSmiStackPatch - 4\r
+ASM_PFX(gStmSmbase)      EQU StmSmbasePatch - 4\r
+ASM_PFX(gStmXdSupported) EQU StmXdSupportedPatch - 1\r
+\r
     SECTION .text\r
 \r
 BITS 16\r
@@ -66,8 +71,8 @@ _StmSmiEntryPoint:
 o32 lgdt    [cs:bx]                       ; lgdt fword ptr cs:[bx]\r
     mov     ax, PROTECT_MODE_CS\r
     mov     [cs:bx-0x2],ax\r
-    DB      0x66, 0xbf                   ; mov edi, SMBASE\r
-ASM_PFX(gStmSmbase): DD 0\r
+o32 mov     edi, strict dword 0\r
+StmSmbasePatch:\r
     lea     eax, [edi + (@32bit - _StmSmiEntryPoint) + 0x8000]\r
     mov     [cs:bx-0x6],eax\r
     mov     ebx, cr0\r
@@ -87,15 +92,15 @@ o16 mov     es, ax
 o16 mov     fs, ax\r
 o16 mov     gs, ax\r
 o16 mov     ss, ax\r
-    DB      0xbc                   ; mov esp, imm32\r
-ASM_PFX(gStmSmiStack): DD 0\r
+    mov     esp, strict dword 0\r
+StmSmiStackPatch:\r
     mov     eax, ASM_PFX(gStmSmiHandlerIdtr)\r
     lidt    [eax]\r
     jmp     ProtFlatMode\r
 \r
 ProtFlatMode:\r
-    DB      0xb8                        ; mov eax, imm32\r
-ASM_PFX(gStmSmiCr3): DD 0\r
+    mov eax, strict dword 0\r
+StmSmiCr3Patch:\r
     mov     cr3, eax\r
 ;\r
 ; Need to test for CR4 specific bit support\r
@@ -134,8 +139,8 @@ ASM_PFX(gStmSmiCr3): DD 0
 .6:\r
 \r
 ; enable NXE if supported\r
-    DB      0b0h                        ; mov al, imm8\r
-ASM_PFX(gStmXdSupported):     DB      1\r
+    mov     al, strict byte 1\r
+StmXdSupportedPatch:\r
     cmp     al, 0\r
     jz      @SkipXd\r
 ;\r
@@ -269,3 +274,6 @@ _StmSmiHandler:
 ASM_PFX(gcStmSmiHandlerSize)   : DW        $ - _StmSmiEntryPoint\r
 ASM_PFX(gcStmSmiHandlerOffset) : DW        _StmSmiHandler - _StmSmiEntryPoint\r
 \r
+global ASM_PFX(SmmCpuFeaturesLibStmSmiEntryFixupAddress)\r
+ASM_PFX(SmmCpuFeaturesLibStmSmiEntryFixupAddress):\r
+    ret\r