UefiCpuPkg/SmmCpuFeaturesLibStm: Add STM library instance

[mirror_edk2.git] / UefiCpuPkg / Library / SmmCpuFeaturesLib / Ia32 / SmiException.S

diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiException.S b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiException.S
new file mode 100644 (file)
index 0000000..7d0057a
--- /dev/null
+++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiException.S
@@ -0,0 +1,174 @@
+#------------------------------------------------------------------------------\r
+#\r
+# Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution.  The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php.\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+# Module Name:\r
+#\r
+#   SmiException.S\r
+#\r
+# Abstract:\r
+#\r
+#   Exception handlers used in SM mode\r
+#\r
+#------------------------------------------------------------------------------\r
+\r
+ASM_GLOBAL  ASM_PFX(gcStmPsd)\r
+\r
+ASM_GLOBAL  ASM_PFX(SmmStmExceptionHandler)\r
+ASM_GLOBAL  ASM_PFX(SmmStmSetup)\r
+ASM_GLOBAL  ASM_PFX(SmmStmTeardown)\r
+\r
+.equ  MSR_IA32_MISC_ENABLE, 0x1A0\r
+.equ  MSR_EFER,             0xc0000080\r
+.equ  MSR_EFER_XD,          0x800\r
+\r
+.equ  CODE_SEL,          0x08\r
+.equ  DATA_SEL,          0x20\r
+.equ  TSS_SEL,           0x40\r
+\r
+    .data\r
+\r
+ASM_PFX(gcStmPsd):\r
+            .ascii  "TXTPSSIG"\r
+            .word      PSD_SIZE\r
+            .word      1              # Version\r
+            .long      0              # LocalApicId\r
+            .byte      0x5            # Cr4Pse;Cr4Pae;Intel64Mode;ExecutionDisableOutsideSmrr\r
+            .byte      0              # BIOS to STM\r
+            .byte      0              # STM to BIOS\r
+            .byte      0\r
+            .word      CODE_SEL\r
+            .word      DATA_SEL\r
+            .word      DATA_SEL\r
+            .word      DATA_SEL\r
+            .word      TSS_SEL\r
+            .word      0\r
+            .quad      0              # SmmCr3\r
+            .long      ASM_PFX(_OnStmSetup)\r
+            .long      0\r
+            .long      ASM_PFX(_OnStmTeardown)\r
+            .long      0\r
+            .quad      0              # SmmSmiHandlerRip - SMM guest entrypoint\r
+            .quad      0              # SmmSmiHandlerRsp\r
+            .quad      0\r
+            .long      0\r
+            .long      0x80010100     # RequiredStmSmmRevId\r
+            .long      ASM_PFX(_OnException)\r
+            .long      0\r
+            .quad      0              # ExceptionStack\r
+            .word      DATA_SEL\r
+            .word      0x1F           # ExceptionFilter\r
+            .long      0\r
+            .quad      0\r
+            .quad      0              # BiosHwResourceRequirementsPtr\r
+            .quad      0              # AcpiRsdp\r
+            .byte      0              # PhysicalAddressBits\r
+.equ  PSD_SIZE,  . - ASM_PFX(gcStmPsd)\r
+\r
+    .text\r
+\r
+#------------------------------------------------------------------------------\r
+# SMM Exception handlers\r
+#------------------------------------------------------------------------------\r
+ASM_GLOBAL ASM_PFX(_OnException)\r
+ASM_PFX(_OnException):\r
+    movl  %esp, %ecx\r
+    pushl %ecx\r
+    call  ASM_PFX(SmmStmExceptionHandler)\r
+    addl  $4, %esp\r
+\r
+    movl  %eax, %ebx\r
+    movl  $4, %eax\r
+    .byte 0xf, 0x1, 0xc1 # VMCALL\r
+    jmp .\r
+\r
+ASM_GLOBAL ASM_PFX(_OnStmSetup)\r
+ASM_PFX(_OnStmSetup):\r
+#\r
+# Check XD disable bit\r
+#\r
+    xorl    %esi, %esi\r
+    movl    $ASM_PFX(gStmXdSupported), %eax\r
+    movb    (%eax), %al\r
+    cmpb    $0, %al\r
+    jz      StmXdDone1\r
+    movl    $MSR_IA32_MISC_ENABLE, %ecx\r
+    rdmsr\r
+    movl    %edx, %esi                     # save MSR_IA32_MISC_ENABLE[63-32]\r
+    testl   $BIT2, %edx                    # MSR_IA32_MISC_ENABLE[34]\r
+    jz      L13\r
+    andw    $0x0FFFB, %dx                  # clear XD Disable bit if it is set\r
+    wrmsr\r
+L13:\r
+    movl    $MSR_EFER, %ecx\r
+    rdmsr\r
+    orw     $MSR_EFER_XD,%ax               # enable NXE\r
+    wrmsr\r
+StmXdDone1:\r
+    push    %esi\r
+\r
+  call ASM_PFX(SmmStmSetup)\r
+\r
+    movl    $ASM_PFX(gStmXdSupported), %eax\r
+    movb    (%eax), %al\r
+    cmpb    $0, %al\r
+    jz      L14\r
+    popl    %edx                        # get saved MSR_IA32_MISC_ENABLE[63-32]\r
+    testl   $BIT2, %edx\r
+    jz      L14\r
+    movl    $MSR_IA32_MISC_ENABLE, %ecx\r
+    rdmsr\r
+    orw     $BIT2, %dx                  # set XD Disable bit if it was set before entering into SMM\r
+    wrmsr\r
+L14:\r
+\r
+  rsm\r
+\r
+ASM_GLOBAL ASM_PFX(_OnStmTeardown)\r
+ASM_PFX(_OnStmTeardown):\r
+#\r
+# Check XD disable bit\r
+#\r
+    xorl    %esi, %esi\r
+    movl    $ASM_PFX(gStmXdSupported), %eax\r
+    movb    (%eax), %al\r
+    cmpb    $0, %al\r
+    jz      StmXdDone2\r
+    movl    $MSR_IA32_MISC_ENABLE, %ecx\r
+    rdmsr\r
+    movl    %edx, %esi                     # save MSR_IA32_MISC_ENABLE[63-32]\r
+    testl   $BIT2, %edx                    # MSR_IA32_MISC_ENABLE[34]\r
+    jz      L15\r
+    andw    $0x0FFFB, %dx                  # clear XD Disable bit if it is set\r
+    wrmsr\r
+L15:\r
+    movl    $MSR_EFER, %ecx\r
+    rdmsr\r
+    orw     $MSR_EFER_XD,%ax               # enable NXE\r
+    wrmsr\r
+StmXdDone2:\r
+    push    %esi\r
+\r
+  call ASM_PFX(SmmStmTeardown)\r
+\r
+    movl    $ASM_PFX(gStmXdSupported), %eax\r
+    movb    (%eax), %al\r
+    cmpb    $0, %al\r
+    jz      L16\r
+    popl    %edx                        # get saved MSR_IA32_MISC_ENABLE[63-32]\r
+    testl   $BIT2, %edx\r
+    jz      L16\r
+    movl    $MSR_IA32_MISC_ENABLE, %ecx\r
+    rdmsr\r
+    orw     $BIT2, %dx                  # set XD Disable bit if it was set before entering into SMM\r
+    wrmsr\r
+L16:\r
+\r
+  rsm\r