UefiCpuPkg/SmmCpuFeaturesLib: Add SMRR PhysBase/PhysMask fields check

[mirror_edk2.git] / UefiCpuPkg / Library / SmmCpuFeaturesLib / SmmCpuFeaturesLib.c

diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c
index b839d3192f563c263f5dfe893e212039ae7b0276..1754f2df5f5789fd41be6f6f98fdffe7b895f1cd 100644 (file)
--- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c
+++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c
@@ -1,7 +1,7 @@
 /** @file\r
 The CPU specific programming for PiSmmCpuDxeSmm module.\r
 \r
-Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR>\r
 This program and the accompanying materials\r
 are licensed and made available under the terms and conditions of the BSD License\r
 which accompanies this distribution.  The full text of the license may be found at\r
@@ -245,9 +245,26 @@ SmmCpuFeaturesInitializeProcessor (
   // is protected and the normal mode code execution will fail.\r
   //\r
   if (mSmrrSupported) {\r
-    AsmWriteMsr64 (mSmrrPhysBaseMsr, CpuHotPlugData->SmrrBase | MTRR_CACHE_WRITE_BACK);\r
-    AsmWriteMsr64 (mSmrrPhysMaskMsr, (~(CpuHotPlugData->SmrrSize - 1) & EFI_MSR_SMRR_MASK));\r
-    mSmrrEnabled[CpuIndex] = FALSE;\r
+    //\r
+    // SMRR size cannot be less than 4-KBytes\r
+    // SMRR size must be of length 2^n\r
+    // SMRR base alignment cannot be less than SMRR length\r
+    //\r
+    if ((CpuHotPlugData->SmrrSize < SIZE_4KB) ||\r
+        (CpuHotPlugData->SmrrSize != GetPowerOfTwo32 (CpuHotPlugData->SmrrSize)) ||\r
+        ((CpuHotPlugData->SmrrBase & ~(CpuHotPlugData->SmrrSize - 1)) != CpuHotPlugData->SmrrBase)) {\r
+      //\r
+      // Print message and halt if CPU is Monarch\r
+      //\r
+      if (IsMonarch) {\r
+        DEBUG ((EFI_D_ERROR, "SMM Base/Size does not meet alignment/size requirement!\n"));\r
+        CpuDeadLoop ();\r
+      }\r
+    } else {\r
+      AsmWriteMsr64 (mSmrrPhysBaseMsr, CpuHotPlugData->SmrrBase | MTRR_CACHE_WRITE_BACK);\r
+      AsmWriteMsr64 (mSmrrPhysMaskMsr, (~(CpuHotPlugData->SmrrSize - 1) & EFI_MSR_SMRR_MASK));\r
+      mSmrrEnabled[CpuIndex] = FALSE;\r
+    }\r
   }\r
 \r
   //\r
@@ -615,3 +632,44 @@ SmmCpuFeaturesWriteSaveStateRegister (
 {\r
   return EFI_UNSUPPORTED;\r
 }\r
+\r
+/**\r
+  This function is hook point called after the gEfiSmmReadyToLockProtocolGuid\r
+  notification is completely processed.\r
+**/\r
+VOID\r
+EFIAPI\r
+SmmCpuFeaturesCompleteSmmReadyToLock (\r
+  VOID\r
+  )\r
+{\r
+}\r
+\r
+/**\r
+  This API provides a method for a CPU to allocate a specific region for storing page tables.\r
+\r
+  This API can be called more once to allocate memory for page tables.\r
+\r
+  Allocates the number of 4KB pages of type EfiRuntimeServicesData and returns a pointer to the\r
+  allocated buffer.  The buffer returned is aligned on a 4KB boundary.  If Pages is 0, then NULL\r
+  is returned.  If there is not enough memory remaining to satisfy the request, then NULL is\r
+  returned.\r
+\r
+  This function can also return NULL if there is no preference on where the page tables are allocated in SMRAM.\r
+\r
+  @param  Pages                 The number of 4 KB pages to allocate.\r
+\r
+  @return A pointer to the allocated buffer for page tables.\r
+  @retval NULL      Fail to allocate a specific region for storing page tables,\r
+                    Or there is no preference on where the page tables are allocated in SMRAM.\r
+\r
+**/\r
+VOID *\r
+EFIAPI\r
+SmmCpuFeaturesAllocatePageTableMemory (\r
+  IN UINTN           Pages\r
+  )\r
+{\r
+  return NULL;\r
+}\r
+\r